KR102268813B1 - Method and System for design of field programmable gate array for deep learning algorithm - Google Patents

Abstract

Provided are a method and system for designing a field programmable gate array (FPGA) optimized for a deep learning algorithm. The method of the present invention comprises: a module architecture designing step of setting a module architecture including at least one of a convolution operation, an addition operation, a pooling operation, and an activation operation for each layer in accordance with a ResNet algorithm layer structure; a control architecture designing step of connecting input data and weight data in parallel to one or more module architecture to set a data path in accordance with the operation within the one or more module architectures; and an FPGA designing step of determining a location where the overall architecture including the one or more module architecture and the control architecture for the one or more module architecture is disposed within the FPGA, based on a resource size of the FPGA.

Description

FPGA design method and system for deep learning algorithm {Method and System for design of field programmable gate array for deep learning algorithm}

The present invention relates to a method and system for designing an FPGA (Field Programmable Gate Array) for a deep learning algorithm.

Deep learning is a field of artificial intelligence that uses artificial neural networks that mimic human neurons. Machine learning (machine learning) has the strength to gradually learn meaningful expressions from successive layers and extract expressions and features from data. ) is one of the methods. When sufficient training/learning is performed, according to the deep learning, classification and prediction of very high performance are possible compared to the existing algorithms, and various methods for applying the deep learning to various fields have been proposed.

However, since such a deep learning algorithm has a very large amount of computation in nature, it requires a computational device that handles it exclusively. Accordingly, research on a dedicated computing device for the deep learning algorithm is being actively conducted, and one of these methods is to design a deep learning algorithm operator using a field programmable gate array (FPGA).

Laid-open Patent Publication No. 10-2018-0125843, 2018.11.26

The problem to be solved by the present invention is to provide an FPGA design method and system optimized for a deep learning algorithm.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A field programmable gate array (FPGA) design method for a deep learning algorithm according to an aspect of the present invention for solving the above-described problems is a convolution (field programmable gate array) for each layer according to the layer structure of a ResNet neural network. designing one or more module architectures including operators for performing a convolution) operation, an addition operation, a pooling operation, and an activation operation, respectively; designing a control architecture by setting a path for the flow of computation data to be performed by the operators in the designed one or more module architectures; and based on the resource size of a field programmable gate array (FPGA), designing the entire architecture by determining a location where the entire architecture including the designed one or more module architectures and the designed control architecture will be placed in the FPGA; wherein the module architecture design step includes, when the same module architecture as the one or more module architectures is added, the added module architecture is connected in parallel to a loop operated by the one or more module architectures, and the control architecture design step Detects a module architecture in which no operation is performed among the designed one or more module architectures, and provides an intermediate sequence of operations to the detected module architecture so that the path is merged into the designed one or more module architectures after a corresponding operation is performed. characterized in that it is set.

In addition, in the module architecture design step, the convolution operation is set to be performed in one cycle, and whenever input data input to the one or more module architectures passes through two layers, input data before the two layers and It is characterized in that the addition operation is set to be summed.

In addition, the convolution operation is a 3 * 3 multiplication operation, the addition operation is the sum of the result values of the 3 * 3 multiplication operation, and the pooling operation is to extract the largest value among the summed result values. operation, and the activation operation is an operation that adds a nonlinear characteristic to the extracted value.

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In addition, the overall architecture design step, calculating the total resource size of the FPGA and the resource size for each block; determining a block type and the number of blocks for the designed one module architecture based on the calculated resource size; And based on the determined block type and the number of blocks, the overall architecture including the designed one or more module architectures and the designed control architecture in the overall structure of the FPGA to determine the location in the FPGA to design the overall architecture step; may include

In addition, the overall architecture design step, based on the determined block type and the number of blocks, it is characterized in that the position where the entire architecture is arranged in the FPGA so that the maximum number of module architectures are arranged in the FPGA.

FPGA) design system for a deep learning algorithm according to an aspect of the present invention for solving the above-mentioned problems, according to the layer structure of the ResNet neural network, convolution operation, addition for each layer (add) a module architecture design unit for designing one or more module architectures including operators for performing each operation, a pooling operation, and an activation operation; a control architecture design unit for designing a control architecture by setting a path for the flow of operation data to be performed by the operators in the designed one or more module architectures; And based on the resource size of the FPGA (field programmable gate array), an FPGA design unit for designing the entire architecture by determining a position in which the entire architecture including the designed one or more module architectures and the designed control architecture will be placed in the FPGA The module architecture design unit includes, when the same module architecture as the one or more module architectures is added, the added module architecture is connected in parallel to a loop operated by the one or more module architectures, and the control architecture design unit, Detects a module architecture in which no operation is performed among the designed one or more module architectures, provides an intermediate sequence of operations to the detected module architecture, and sets the path to be merged into the designed one or more module architectures after a corresponding operation is performed characterized in that

In addition, the convolution operation is a 3 * 3 multiplication operation, the addition operation is the sum of the result values of the 3 * 3 multiplication operation, and the pooling operation is to extract the largest value among the summed result values. operation, and the activation operation is an operation for adding a nonlinear characteristic to the extracted value.

In addition, the FPGA design unit, a resource size calculation unit for calculating the total resource size of the FPGA and the resource size for each block; a module block determining unit for determining a block type and the number of blocks for the designed one module architecture, based on the calculated resource size; And on the basis of the determined block type and the number of blocks, the overall structure of the FPGA including the designed one or more module architecture and the designed control architecture in the overall structure comprising a block arranging unit for determining a location in the FPGA characterized.

A computer program according to another aspect of the present invention for solving the above-described problems may be stored in a computer-readable recording medium in combination with a computer to execute the FPGA design method for the above-described deep learning algorithm.

Other specific details of the invention are included in the detailed description and drawings.

According to the present invention as described above, it is possible to increase the efficiency, optimization and flexibility of FPGA design for a deep learning algorithm (in particular, the Rezne algorithm).

In addition, according to the present invention, by modularizing the architecture for performing the deep learning operation, it is possible to appropriately arrange the modular architecture according to the number of resources of the FPGA. Through this, an architecture that is adaptively optimized according to the size of the FPGA can be implemented quickly and flexibly.

Effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a diagram briefly illustrating the basic concept of an artificial neural network.
2 is a diagram schematically illustrating a basic residual connection structure of Reznet.
3 is a flowchart of an FPGA design method for a deep learning algorithm according to an example of the present invention.
4 is a diagram briefly illustrating a module architecture according to an example of the present invention.
5 is a diagram showing examples of activation functions applicable to the present invention.
6 is a diagram schematically illustrating an architecture structure according to an example of the present invention.
7A to 7C are diagrams briefly illustrating FPGA design steps applicable to the present invention.
8 is a diagram showing the configuration of an FPGA design system according to an example of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains. It is provided to fully understand the scope of the present invention to those skilled in the art, and the present invention is only defined by the scope of the claims.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. As used herein, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and/or “comprising” does not exclude the presence or addition of one or more other components in addition to the stated components. Like reference numerals refer to like elements throughout, and "and/or" includes each and every combination of one or more of the recited elements. Although "first", "second", etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein will have the meaning commonly understood by those of ordinary skill in the art to which this invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless specifically defined explicitly.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention discloses a method and system for designing a field programmable gate array (FPGA) for a deep learning algorithm. In other words, the present invention discloses a method for designing on an FPGA having limited resources capable of implementing the deep learning algorithm and a system therefor.

Before the description, the meaning of the terms used herein will be briefly described. However, it should be noted that the description of terms is for the purpose of helping the understanding of the present specification, and is not used in the meaning of limiting the technical idea of the present invention unless explicitly described as limiting the present invention.

First, a deep learning algorithm is one of the machine learning algorithms and refers to a modeling technique developed from an artificial neural network that mimics a human neural network. The artificial neural network may be configured in a multi-layered hierarchical structure as shown in FIG. 1 .

1 is a diagram briefly illustrating the basic concept of an artificial neural network.

1 , an artificial neural network (ANN) is a layer including an input layer, an output layer, and at least one intermediate layer (or a hidden layer) between the input layer and the output layer. can be structured. The deep learning algorithm can derive reliable results as a result through learning that optimizes the weight of the activation function between layers based on such a multi-layer structure.

The deep learning algorithm applicable to the present invention may include a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), and the like.

DNN is basically characterized by increasing the middle layer (or hidden layer) in the existing ANN model to improve the learning result. As an example, the DNN is characterized in that it performs a learning process using two or more intermediate layers. Accordingly, the computer can derive the optimal output value by repeating the process of creating a classification label by itself, distorting the space, and classifying the data.

Unlike the conventional technique in which a learning process is performed by extracting knowledge from data, CNN is characterized in that it has a structure for identifying patterns of features by extracting features of data. The CNN may be performed through a convolution process and a pooling process. In other words, the CNN may include an algorithm in which a convolutional layer and a pooling layer are combined. Here, in the convolutional layer, a process of extracting features of data (so-called convolution process) is performed. The convolution process is a process of examining adjacent components of each component in the data to determine the characteristics and deriving the identified characteristics into a single sheet. As a single compression process, the number of parameters can be effectively reduced. In the pooling layer, a process of reducing the size of the convolutional layer (so-called pooling process) is performed. The pooling process may reduce the size of data, cancel noise, and provide consistent features in minute details. For example, the CNN may be used in various fields such as information extraction, sentence classification, and face recognition.

RNN is a type of artificial neural network specialized for iterative and sequential data learning, and is characterized by having a cyclic structure inside. The RNN uses the cyclic structure to apply weights to past learning contents and reflect them in current learning, thereby enabling a connection between current learning and past learning and being time dependent. The RNN is an algorithm that solves the limitations of the existing continuous, iterative, and sequential data learning, and can be used to identify a speech waveform or identify the front and back components of a text.

In particular, the FPGA design method according to the present invention based on ResNet, which is one of CNNs, will be described in detail below. However, the technical configuration disclosed in the present invention is not limited to simply being applied to Resnet, and may also be applied to various deep learning algorithms similar to Resnet.

2 is a diagram schematically illustrating a basic residual connection structure of Reznet.

As shown in Fig. 2, according to the residual connection applied to Resnet, an input value of x passes through a certain number of weight layers (eg, two weight layers) and passes through the ReLU function, which is a non-linear activation function. do. When the ReLU function is f(x), according to the residual linkage structure, f(x)+x, which is the activation value f(x) plus x, the input value itself (identity), is applied as the input value of the next activation function. That is, the residual connection structure allows the gradient of x, which is the original input value, to flow directly through the network, and adds the input value itself (identity) to the output value that has passed the nonlinear function to obtain the original gradient. make sure not to lose

Resnet to which such a residual connection structure is applied may continuously include a structure having a certain operation regularity. Considering these characteristics, the operator can be configured by modularizing the basic architecture of Reznet. In this case, the basic architecture considers the number of resources (or the amount of resources, in this case, the resources may include a digital signal processing (DSP), a look up table (LUT), etc.) of the FPGA, and one or a plurality of them are applied to the FPGA. can The modular basic architecture can be applied to FPGAs of various sizes by modifying/supplementing the control architecture that controls them according to the number. Accordingly, the structure of the algorithm itself is very simple, so that placement and wiring errors can be minimized when inserting the FPGA.

Accordingly, in the present invention, a detailed description will be given of an FPGA design method and system in consideration of the characteristics of such a deep learning algorithm (particularly, Reznet algorithm).

FPGAs are semiconductor devices that contain designable logic elements and programmable internal circuitry. The FPGA has the characteristic of being able to flexibly change the internal operator arrangement and storage use/connection structure according to the user's setting. However, the design of the operator architecture is very complicated and the design has to be different depending on the resources (eg DSP, LUT, etc.) secured by the FPGA.

However, as described above, if a deep learning algorithm in which a consistent structure is continuous is configured as a basic module architecture, the basic module architecture can be easily added/applied according to the resource size of the FPGA. In other words, when using a modularized basic module architecture, deep learning computation performance can be easily improved as the number of basic module architectures increases. In addition, when using the modularized basic module architecture, the control architecture that controls it can be implemented through simple modification according to the number of the basic module architectures. In other words, the control architecture can be applied to FPGAs for each size through simple modification according to the number of the basic module architectures. In addition, since the structure of the basic module architecture itself can be implemented very simply, it is possible to minimize placement and wiring errors when inserting it into the FPGA.

Based on these characteristics, the following describes in detail an FPGA design method and system for a deep learning algorithm.

3 is a flowchart of an FPGA design method for a deep learning algorithm according to an example of the present invention.

As shown in FIG. 3 , the FPGA design method for a deep learning algorithm (eg, Reznet, etc.) according to the present invention includes a module architecture design step (S310), a control architecture design step (S320) and an FPGA design step (S330). ) may be included. In the present invention, the FPGA design method may be implemented by a computer program stored in a computer-readable recording medium to execute the FPGA design system or the FPGA design method. Accordingly, the FPGA design method may receive input/setting information from a user, and provide/display an optimal FPGA design method for a corresponding deep learning algorithm to the user.

In one embodiment applicable to the present invention, in step S310, the FPGA design system may design the configuration of the operator for each layer according to the layer structure of the ResNet algorithm. More specifically, the FPGA design system performs at least one of a convolution operation, an add operation, a pooling operation, and an activation operation for each layer according to the hierarchical structure of the Reznet algorithm in step S310. You can configure the module architecture including In this case, the operation structure (or hierarchical structure) of the Reznet algorithm or the deep learning algorithm may be obtained from data input from a user or set data.

As an example applicable to the present invention, the convolution operation may be set to be performed in one cycle, and the addition operation may be set to add up input data before the two layers whenever input data passes through two layers. have. More specifically, the multiplication-accumulation architecture may be configured such that repeatedly used convolution operations (eg, 3*3 convolution operations, etc.) are performed in one cycle, and the addition operation is performed when input data passes through two layers. The pattern may be configured to be merged with input data before the two layers each time. In addition, the pooling operation and the activation operation may be set to be placed in a specific layer (eg, a layer identified in an initial layer search step, etc.) to perform an operation operation.

4 is a diagram briefly illustrating a module architecture according to an example of the present invention.

As shown in FIG. 4 , the module architecture according to an embodiment of the present invention may include a 3*3 multiplication operator, an accumulator, a pooling operation, and a ReLU operation. In other words, the module architecture may be configured to include an operator that performs a total of nine operations (3*3) at once, and an architecture that accumulates and sums them. For example, the convolution operation performs a 3*3 multiplication operation, the addition operation performs summing the result values of the convolution operation, and the pooling operation extracts the largest value among the summed values, The activation operation may be set to add a non-linear characteristic to the extracted value. In this case, the module architecture may additionally include a data selector for outputting a predetermined data value from data output from an accumulator, a pooling operation, and a ReLU operation. As an additional embodiment, when one such module architecture is added, the added module architecture may be connected in parallel to a loop operated by the existing module architecture. Through this, the entire module architecture may be configured to simultaneously process two Reznet operations.

5 is a diagram showing examples of activation functions applicable to the present invention.

As shown in FIG. 5 , an activation operation in the module architecture may apply an activation function to add a non-linear characteristic to input data (eg, a value extracted from a pooling operation). In this case, as the activation function, one of various activation functions shown in FIG. 5 may be applied. As an example, the present invention discloses an example in which the ReLU function is applied as an activation function, but according to an embodiment, a Sigmoid, Leaky ReLU, ELU function, etc. may be applied instead of the ReLU function.

In an embodiment applicable to the present invention, in step S320, the FPGA design system connects input data and weight data to one or more module architectures in parallel, and sets a data path according to an operation in the one or more module architectures. can More specifically, in step S320, the FPGA design system may bind one or more module architectures designed as described above into one, and set an appropriate data flow for the one or more module architectures.

More specifically, the FPGA design system may connect input data and weight data for one module architecture, and set a data path according to an operation within the one module architecture. Then, when one or more (data) module architectures are added, the FPGA design system connects the input data and weight data stored in the existing storage to the one or more module architectures to be added in parallel, and the one or more modules to be added It is possible to detect a module architecture that does not perform each operation among the architectures (eg, a convolution operation, an addition operation, a pooling operation, an activation operation, etc.). Next, the FPGA design system may set the control architecture to be merged after the operation is performed by providing the operation intermediate sequence to the module architecture in which the operation is not being performed. In other words, in step S320, the FPGA design system detects a module architecture in which no operation is performed within one or more module architectures, and provides an intermediate sequence of operations to the detected module architecture so that the corresponding operation is performed and merged. You can set the data path.

6 is a diagram schematically illustrating an architecture structure according to an example of the present invention.

After the module architecture design step and the control architecture design step described above, as shown in FIG. 6 , the entire architecture structure including one or more module architectures and a control architecture for the one or more module architectures can be designed.

For example, as shown in FIG. 6 , the module architecture may include one or more computational architectures and a data merging architecture that merges output values from the one or more computational architectures. Then, the control architecture may be configured to implement a specific deep learning algorithm (eg, Reznet algorithm, etc.) by providing input input data and weight data to each computational architecture and data merging architecture. Then, the data merging architecture may output result data according to the specific deep learning algorithm.

In an embodiment applicable to the present invention, in step S330, the FPGA design system, based on the resource size of the FPGA, the entire architecture including one or more module architectures and a control architecture for one or more module architectures is located in the FPGA can be decided

More specifically, in step S330, the FPGA design system can be set to be implemented by properly inserting the module architecture for the deep learning algorithm (eg, Resnet algorithm) designed according to the above-described method and the control architecture to control it into the actual FPGA. have.

In general, in order to insert a specific architecture into an FPGA, a computer system automatically provides a function of arranging and connecting an operator, but this method requires a lot of time and is inefficient because it takes a lot of time and the confirmation of failure is very slow. In addition, when the size of the FPGA is changed, there is a disadvantage that such arrangement and wiring work must be performed again.

On the other hand, when using a modular architecture (eg, a module architecture) as in the present invention, an FPGA area (eg, a block area) required by the modular architecture may be set as a P-block. In this case, the P-block may mean a plan view or a basic unit on the FPGA. Accordingly, by checking whether the P-block can be placed in a specific position in the FPGA, the probability of failure or error for the same P-block is reduced, and as a result, placement and wiring in the FPGA can be successfully performed. When the verified module architecture is placed and inserted in the entire area of the FPGA, the time required for inserting the REZNET operation architecture optimized for each size FPGA can be significantly reduced, enabling rational optimization design.

7A to 7C are diagrams briefly illustrating FPGA design steps applicable to the present invention.

For the above operation, step S330 (FPGA design step), the resource size calculation step (FIG. 7a) of calculating the total resource size of the FPGA (eg, DSP, LUT resource, etc.) and the resource size for each block (FIG. 7a), the calculation Based on the determined resource size, the module block determination step of determining the block type and the number of blocks for one module architecture (FIG. 7b), based on the determined block type and the number of blocks for the one module architecture, the FPGA and a block placement step (FIG. 7C) of determining where the overall architecture, including the one or more module architectures and a control architecture for the one or more module architectures, is placed in the FPGA in the overall architecture.

Here, the block arrangement step may include, based on the determined block type and the number of blocks for one module architecture, determining a location where the entire architecture is placed in the FPGA so that the maximum number of module architectures in the FPGA is placed. . In other words, the FPGA design system provides the user with the result of placement in the FPGA of the entire architecture including the maximum number of module architectures and the control architecture for the maximum number of module architectures so that the maximum number of module architectures can be placed in the FPGA. can provide

As another example, in the FPGA design system, based on the block type and the number of blocks for one module architecture determined in the block arrangement step, the entire architecture is placed in the FPGA to minimize the probability of failure and/or error in the FPGA. may include determining In other words, the FPGA design system is a configuration in the FPGA of the entire architecture including the one or more module architectures and the control architecture for the one or more module architectures, such that the probability of implementation failure/error of the one or more module architectures in the FPGA can be minimized. Results can be provided to the user.

In the present invention, the above process can be performed through the same algorithm driving in FPGAs of various sizes by using a script for driving a series of algorithms. Through this, the FPGA design system according to the present invention can search for and arrange a block in an optimized form for a module architecture.

8 is a diagram showing the configuration of an FPGA design system for a deep learning algorithm according to an example of the present invention.

As shown in FIG. 8 , the FPGA design system may include a module architecture design unit 810 , a control architecture design unit 820 , an FPGA design unit 830 , and an input unit 840 .

In the present invention, the module architecture design unit 810 may perform an operation related to the above-described module architecture design. Also, the control architecture design unit 820 may perform an operation related to the aforementioned control architecture design. Also, the FPGA design unit 830 may perform an operation related to the above-described FPGA design. In particular, for the above-described FPGA design step, the FPGA design unit 830, a resource size calculation unit for calculating the total resource size of the FPGA and the resource size for each block, based on the calculated resource size, one module architecture A module block determining unit that determines the block shape and the number of blocks for, and the one or more module architectures and the one or more module architectures in the overall structure of the FPGA based on the determined block shape and the number of blocks for one module architecture The entire architecture including the control architecture for may include a block arrangement unit that determines a location in the FPGA.

Additionally, the input unit 840 obtains the user's input/settings for the FPGA design system, and converts it into appropriate data (eg, hierarchical structure of deep learning algorithm, input data, weight data, etc.) to the FPGA design system. can provide Through this, the FPGA design system can provide the user with an optimal FPGA design method for the deep learning algorithm set by the user.

The steps of a method or algorithm described in relation to an embodiment of the present invention may be implemented directly in hardware, as a software module executed by hardware, or by a combination thereof. A software module may contain random access memory (RAM), read only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, hard disk, removable disk, CD-ROM, or It may reside in any type of computer-readable recording medium well known in the art to which the present invention pertains.

As mentioned above, although embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can realize that the present invention can be embodied in other specific forms without changing its technical spirit or essential features. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

800: FPGA design system
810: module architecture design unit
820: control architecture design unit
830: FPGA Design Department
840: input unit

Claims (10)

A method performed by a computer, comprising:
One or more module architectures including operators for performing convolution operation, addition operation, pooling operation, and activation operation for each layer according to the layer structure of the ResNet neural network. designing;
designing a control architecture by setting a path for the flow of computation data to be performed by the operators in the designed one or more module architectures; and
Based on the resource size of a field programmable gate array (FPGA), designing the overall architecture by determining a location in which the entire architecture including the designed one or more module architectures and the designed control architecture will be placed in the FPGA; including; and
The module architecture design step is,
When the same module architecture as the one or more module architectures is added, the added module architecture is connected in parallel to a loop in which the one or more module architectures operate,
The control architecture design step is,
Detecting a module architecture in which an operation is not performed among the designed one or more module architectures,
providing an intermediate sequence of operations to the sensed module architecture to set the path to be merged into the designed one or more module architectures after a corresponding operation is performed,
FPGA Design Methods for Deep Learning Algorithms. The method of claim 1,
The module architecture design step is,
Set the convolution operation to be performed in one cycle,
Each time the input data input to the one or more module architectures passes through two layers, the addition operation is set to be summed with input data before the two layers,
FPGA Design Methods for Deep Learning Algorithms. The method of claim 1,
The convolution operation is a 3 * 3 multiplication operation,
The addition operation is the sum of the result values of the 3 * 3 multiplication operation,
The pooling operation is an operation for extracting the largest value among the summed result values,
The activation operation is characterized in that it is an operation that adds a non-linear characteristic to the extracted value,
FPGA Design Methods for Deep Learning Algorithms. delete The method of claim 1,
The overall architecture design step is,
calculating the total resource size of the FPGA and the resource size for each block;
determining a block type and the number of blocks for the designed one module architecture based on the calculated resource size; and
Based on the determined block type and the number of blocks, designing the overall architecture by determining a location where the entire architecture including the designed one or more module architectures and the designed control architecture in the overall structure of the FPGA is placed in the FPGA ; characterized in that it comprises
FPGA Design Methods for Deep Learning Algorithms. 6. The method of claim 5,
The overall architecture design step is,
Based on the determined block type and the number of blocks, it is characterized in that to determine a position where the entire architecture is placed in the FPGA so that the maximum number of module architectures in the FPGA are placed
FPGA Design Methods for Deep Learning Algorithms. One or more module architectures including operators for performing convolution operation, addition operation, pooling operation, and activation operation for each layer according to the layer structure of the ResNet neural network. a module architecture design unit that designs;
a control architecture design unit for designing a control architecture by setting a path for the flow of operation data to be performed by the operators in the designed one or more module architectures; and
Based on the resource size of a field programmable gate array (FPGA), the entire architecture including the designed one or more module architectures and the designed control architecture is placed in the FPGA to determine a location in the FPGA to design the entire architecture. and
The module architecture design unit, when the same module architecture as the one or more module architectures is added, connects the added module architecture in parallel to a loop in which the one or more module architectures operate,
The control architecture design unit detects a module architecture in which an operation is not performed among the designed one or more module architectures, provides an intermediate sequence of operations to the detected module architecture, and after a corresponding operation is performed, to the designed one or more module architectures characterized in that the path is set to be merged,
FPGA design system for deep learning algorithms. 8. The method of claim 7,
The convolution operation is a 3 * 3 multiplication operation,
The addition operation is the sum of the result values of the 3 * 3 multiplication operation,
The pooling operation is an operation for extracting the largest value among the summed result values,
The activation operation is characterized in that it is an operation that adds a non-linear characteristic to the extracted value,
FPGA design system for deep learning algorithms. 8. The method of claim 7,
The FPGA design unit,
a resource size calculator for calculating the total resource size of the FPGA and the resource size for each block;
a module block determining unit for determining a block type and the number of blocks for the designed one module architecture, based on the calculated resource size; and
Based on the determined block type and the number of blocks, the overall structure of the FPGA includes a block arrangement unit that determines a location in which the entire architecture including the designed one or more module architectures and the designed control architecture is placed in the FPGA. to do,
FPGA design system for deep learning algorithms. A recording medium in which a program for executing the method of any one of claims 1 to 6 is stored in combination with a computer which is hardware.

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