KR102268017B1 - A method of cabac decoding based on an application specific processor and an apparatus therefor - Google Patents

Abstract

The present invention relates to a CABAC decoding method and apparatus based on an application specific instruction processor. According to an embodiment of the present invention, there is provided a method for performing CABAC decoding using an application-specific instruction processor, the method comprising: receiving an image signal; receiving type information of the video signal; and outputting at least one of a context index value and a decoding bit updated based on at least one of a context index value and the video signal according to the type information.

Description

A METHOD OF CABAC DECODING BASED ON AN APPLICATION SPECIFIC PROCESSOR AND AN APPARATUS THEREFOR

The present invention relates to a CABAC decoding method and an apparatus thereof, and more particularly, to a CABAC decoding method based on an application-specific instruction processor and an apparatus thereof.

Due to the proliferation of various multimedia devices, video standards for multimedia devices adopt various video compression algorithms to increase video compression rates. The various image compression algorithms can provide images with a small capacity and high quality. However, recent entropy coding such as CAVLC and CABAC cannot perform parallel processing because the current symbol is determined by the previous symbol. Therefore, various studies have been conducted in which entropy coding processing can be improved on the same platform on which other computational processing is performed.

Among various research methods, the application-specific instruction processor execution method is used to perform entropy coding by adding hardware for performing a specific operation or processing and instructions related thereto. The application-specific instruction processor execution method minimizes additional hardware cost and at the same time exhibits a high processing speed close to that of custom hardware execution. This application-specific instruction processor execution method has the flexibility to be used in various multimedia standards, since these standards are implemented as a program together with newly added instructions. However, in order to recognize the minimum hardware cost without affecting the instructions of the currently existing processor, the operation of the new instructions is performed at an atomic level, and the instructions must be precisely designed and accurate.

A bitstream processor (BSP) is one of the processors that can easily handle variable length coding (VLC) using an application specific instruction processor. The instructions for high-speed processing of the bitstream are based on the look-up table, and by changing the assembly code, adaptive coding and fast processing of various image standards that can be supported are possible. However, CABAC, which is an arithmetic coding used in a recent video standard, is a mixture of arithmetic coding and variable length coding, and thus cannot perform a look-up table, and thus cannot be processed using a currently used bitstream processor.

An object of the present invention is to provide a CABAC decoding method based on an application-specific instruction processor for performing context-adaptive variable-length coding in parallel.

In addition, another technical problem to be achieved by the present invention is to provide a CABAC decoding apparatus based on an application-specific instruction processor capable of providing a fast processing speed while minimizing an additional hardware cost.

According to an embodiment of the present invention, there is provided a method for performing CABAC decoding using an application-specific instruction processor, the method comprising: receiving an image signal; receiving type information of the video signal; The method may include outputting at least one of a context index value and a decoding bit updated based on at least one of a context index value and the video signal according to the type information.

The outputting of at least one of the updated context index value and the decoding bit may be performed simultaneously with receiving the video signal, and the type information includes regular mode information for updating the context index value and the context index value. The update may include bypass mode information that is not performed.

In an embodiment, when the type information is regular mode information, outputting at least one of the updated context index value and the decoding bit includes: checking whether the context index value of the current state is stored in a register ; when the context index value of the current state is stored, calculating a state conversion table and a range table corresponding to the context index value using the stored context index value; performing arithmetic coding using the video signal, the state conversion table, and the range table; outputting the updated context index value calculated during the arithmetic coding and the decoding bit; and adjusting the location information representing the video signal to represent the next video signal.

In addition, when the type information is bypass mode information, outputting at least one of the updated context index value and the decoding bit may include: performing arithmetic coding using the video signal and a fixed probability value; outputting a decoded bit value calculated during the arithmetic coding; and adjusting the location information representing the video signal to represent the next video signal.

According to another embodiment of the present invention, there is provided an apparatus for performing CABAC decoding using an application-specific instruction processor, comprising: a memory for storing the application-specific instruction; and generating at least one of a context index and a decoding bit based on the type information of the video signal in order to context-adaptively perform binary arithmetic coding of the video signal, and using at least one or more of the generated context index and decoding bit It may include a syntax processor for coding the image signal.

In an embodiment, the syntax processor includes: a VLC engine for performing variable length coding on the video signal; a BAC engine for performing binary arithmetic coding on the video signal; an RLC engine that performs run-length coding on the video signal; and a microprocessor core for controlling whether to perform coding of the VLC engine, the BAC engine, and the RLC engine and a command related to the coding.

The BAC engine may include a microprocessor core unit configured to perform a command based on the type information; BAC for receiving the type information and the context index value of the current state from the microprocessor core unit, receiving the updated context index value when the context index value is updated, and outputting a decoding bit value for the video signal control unit; and calculating a state conversion table and a range table corresponding to the context index value using the context index value, performing arithmetic coding using the video signal, the state conversion table, and the range table, and the arithmetic coding It may include a BAC engine core for outputting at least one of the updated context index value calculated at the time and the decoding bit.

When the type information is regular mode information, the BAC control unit outputs the updated context index value and the decoding bit value to the microprocessor core unit, and the BAC engine core unit outputs the updated context index value and the decoding bit value. can be output to the BAC control unit.

In addition, when the type information is bypass mode information, the BAC control unit outputs the decoding bit value to the microprocessor core unit, and the BAC engine core unit determines the decoding bit value using a fixed probability value and the image signal. output to the BAC control unit.

In one embodiment, the memory for storing the state conversion data and the range table data; and a register storing the updated context index value, the decoding bit value, and the video signal.

The BAC engine core may receive the video signal while outputting at least one of an updated context index value and a decoding bit.

According to an embodiment of the present invention, by including a binary arithmetic coding (BAC) engine based on an application-specific instruction processor that generates at least one or more of an updated context index value and a decoding bit according to type information, the context adaptive in parallel It is possible to provide a CABAC decoding method based on an application-specific instruction processor capable of performing variable length coding.

In addition, according to another embodiment of the present invention, by including a binary arithmetic coding engine in an application-specific instruction processor (ASIP) capable of using parallel processing and lookup tables, it is possible to provide fast processing speed while minimizing additional hardware costs. It is possible to provide a CABAC decoding device based on an application-specific instruction processor.

1 is a block diagram illustrating a general CABAC decoding apparatus.
2 is a block diagram illustrating an application specific instruction processor (ASIP) according to an embodiment of the present invention.
3 is a block diagram illustrating a binary arithmetic coding engine unit according to an embodiment of the present invention.
4 is a flowchart illustrating a CABAC decoding method according to an embodiment of the present invention.
5 is a block diagram illustrating a regular mode processing process of a binary arithmetic coding engine unit according to an embodiment of the present invention.
6 is a block diagram illustrating a bypass mode processing process of a binary arithmetic coding engine unit according to an embodiment of the present invention.
7 is an image of an image decoded by a decoding method according to an embodiment of the present invention.
8A and 8B show processing cycles in units of pixels of a decoding apparatus (Example) and general video signal decoding apparatuses (Comparative Examples 1 and 2) according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Examples of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art, and the following examples may be modified in various other forms, and the scope of the present invention is as follows It is not limited to an Example. Rather, these examples are provided so that this disclosure will be more thorough and complete, and will fully convey the spirit of the invention to those skilled in the art.

In the drawings, like reference numerals refer to like elements. Also, as used herein, the term “and/or” includes any one and all combinations of one or more of those listed items.

The terminology used herein is used to describe the embodiments, and is not intended to limit the scope of the present invention. Also, although the singular is used herein, the plural form may be included unless the context clearly indicates the singular. Also, as used herein, the terms "comprise" and/or "comprising" specify the presence of the recited shapes, numbers, steps, actions, members, elements, and/or groups thereof. It does not exclude the presence or addition of other shapes, numbers, movements, members, elements and/or groups.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. When it is determined that a detailed description of a known function or configuration related to the embodiments may unnecessarily obscure the gist of the present invention, a detailed description thereof will be omitted.

The image processing method according to an embodiment may be performed by an image processing apparatus. Like reference numerals in each figure indicate like elements.

Arithmetic coding refers to entropy coding capable of expressing a plurality of symbols as a single real number. A given symbol of the arithmetic coding method and a probability distribution of each symbol can provide a compression rate close to an optimal rate compared to other variable length coding methods. The CABAC algorithm can be used for video standards such as H.264 and HEVC because an initial probability is determined depending on a context to be compressed, and a probability interval is changed based on a new symbol type.

1 is a block diagram showing a general CABAC decoding processing apparatus.

Referring to FIG. 1 , a CABAC decoding processing apparatus according to an embodiment of the present invention includes a context modeling unit 1 , a regular decoding engine 2 , a bypass decoding engine 3 , and an inverse binarization unit 4 . do. CABAC decoding refers to a process of reading a syntax element through inverse binarization of an input bitstream with output of a bin value through a binary arithmetic decoding process. The binary arithmetic decoding process includes two categories, which are regular mode and bypass mode.

In the regular mode, the probability may be determined by the context modeling unit 1 , and a binary output value may be output by the regular decoding engine 2 . In an embodiment, the context modeling unit 1 may be updated for the next probability interval thereafter. The bypass mode may use a preset probability section without using the context modeling unit 1 . If the syntax element has a binary value, the inverse binarization process may be skipped.

Since a general purpose processor does not have appropriate instructions and operations for processing a continuously input CABAC bitstream, a processor is required to operate through various instructions. On the other hand, if all CABAC processes are run in hardware, the process speed will be faster. However, the scalability to other entropy coding techniques will be insufficient, and the hardware cost will increase as the video standard to be supported increases.

In another implementation method, if an existing application specific instruction processor (ASIP) for variable length coding is used as it is, it may be possible to perform fast processing by using functions executed in the past. However, the conventional application specific instruction processor for variable length coding is designed for processing variable length coding instructions with a large number of bits. This represents expressing one variable length coding using one address for the associated operation.

However, since CABAC decoding changes the context model and probability value used in the next bit to 1 bit that is the processing result of the bitstream, the operation can be processed using only 1 bit. Therefore, designing an instruction of variable length coding to process a large number of bits may not be suitable for CABAC decoding that operates one bit at a time.

In one embodiment of the present invention, an application-specific instruction processor suitable for CABAC decoding is designed by extending the conventional application-specific instruction processor for variable length coding. Accordingly, the arithmetic coding (AC) engine for rapid CABAC processing of the present invention can be connected with an application specific instruction processor for conventional variable length coding using hardware. And, the rapid CABAC processing may be possible by adding instructions to efficiently handle the arithmetic coding engine for CABAC.

In CABAC decoding, the instructions may be designed to simultaneously process all various operation processes. In this case, it may be possible to process the same operations as a CABAC decoding apparatus having hardware including an arithmetic coding engine. In addition, this may be possible by using a Reduced Instruction Set Computer (RISC) composed of minimal unit instructions for necessary operations without CABAC instructions. However, multiple instructions for one CABAC process may be required. In addition, due to the intrinsic nature of CABAC bitstream processing, efficient bitstream processing may be possible by linking efficient bitstream-related operations to CABAC instructions using general bitstream processing hardware. The bitstreams needed in this way can be processed by executing additional instructions or a plurality of instructions.

CABAC decoding apparatus according to an embodiment of the present invention can support various compression formats, such as CAVLC and CABAC, by adding CABAC instructions that the conventional application-specific instruction processor platform for variable length coding does not support. Since a conventional processor arithmetic unit cannot simultaneously generate and extract necessary data in the CABAC decoding apparatus, an arithmetic coding (AC) engine and new hardware are added, and a random variable can be updated while moving a bitstream. 1 , while the CABAC arithmetic coding engine processes the normal and bypass decoding engines in the CABAC decoding process, an application-specific instruction processor function for general variable length coding is processed in the context modeling unit 1 and updated and can be binarized.

2 is a block diagram illustrating an application specific instruction processor (ASIP) according to an embodiment of the present invention.

Referring to FIG. 2 , the application specific instruction processor includes a microprocessor core unit 210 , a variable length coding (VLC) engine 220 , a binary arithmetic coding (BAC) engine 230 , and a run length coding (RLC) engine. (240). The binary arithmetic coding engine 230 may be added with a conventional application-specific instruction processor for variable length coding. The binary arithmetic coding engine 230 may operate as a part of the syntax processor 200 using instructions received from the microprocessor core unit 210 .

The run/level values decoded by the syntax processor 200 may be transmitted to a run length coding (RLC) engine 240 . The run length coding engine 240 may generate residual data by combining the delivered run/level values and location information of the run/level values using a zig-zag table stored in the memory 100 . Thereafter, the generated data may be transferred to a system coupled to the application specific instruction processor.

3 is a block diagram illustrating the operation of the binary arithmetic coding engine unit 230 according to an embodiment of the present invention.

Referring to FIG. 3 , the binary arithmetic coding engine unit 230 may be operated according to specific binary arithmetic coding instructions stored in the microprocessor core unit 210 and transmitted to the binary arithmetic coding engine unit 230 . Various table data required for CABAC decoding may be stored in a memory and may be used through assembly code by using memory-related instructions. Therefore, if the table data needs to be changed, the data in the memory 100 area may be changed. These tables can be loaded as a request of the binary arithmetic coding engine 230 .

Also, the bitstream register 300 may be used to hold a bitstream for the binary arithmetic coding engine 230 . In an embodiment, the bitstream register 300 may readjust the stored bitstream to the next bitstream while removing the bit used by the binary arithmetic coding engine 230 .

The new instructions used on the binary arithmetic coding engine 230 may be related to the Decoding Regular (DSR) instruction to operate the regular mode and the Decoding Bypass (DCB) instruction for the Bypass mode. The decoding regular command carries context index values carrying both a maximum probability symbol (MPS) value and a state index, and can operate in regular mode. The decoding bypass command may operate the bypass mode using a fixed probability value.

4 is a flowchart illustrating a CABAC decoding method according to an embodiment of the present invention.

Referring to FIG. 4 , first, the CABAC decoding apparatus may receive an image signal ( S10 ). The video signal may be the entire bitstream in which CABAC decoding is performed, or a portion of the bitstream. In addition, the CABAC decoding apparatus according to an embodiment of the present invention may receive type information of the video signal (S20).

The type information may be information indicating which mode among a regular mode and a bypass mode is performed during the decoding process in order to perform CABAC decoding based on an application-specific command processor on the video signal. The type information may be received by being included in the received video signal or may be received by the CABAC decoding apparatus through a syntax separate from the video signal when the video signal is a part of the entire bitstream.

The regular mode may be a mode in which a context index value is updated using information received from a memory and a decoding bit value to be used is output. Accordingly, the value for the next probability interval may be updated. Meanwhile, the bypass mode may be a mode that uses the context modeling unit to output decoding bits without updating the context index value, and uses a preset probability interval because context modeling is not performed.

Therefore, the CABAC decoding method of the present invention may output at least one of an updated context index value and a decoding bit value according to the type information (S30). In detail, when the type information is in the regular mode, both the updated context index value and the decoding bit value may be output. In addition, when the type information is in the bypass mode, the updated context index value may not be output, and only the decoding bit value may be output.

5 is a block diagram illustrating a regular mode processing process of a binary arithmetic coding engine unit according to an embodiment of the present invention.

Referring to FIG. 5 , when the CABAC decoding apparatus processes an input signal in the regular mode, the microprocessor core unit 210 , the BAC engine 230 , the memory 100 , and the register 300 are activated to activate the input signal. can be processed

In the regular mode, the register 300 may include a destination register (dr) for storing an output bit and a source register (sr) for storing a context index value for transmission. In order to execute the regular mode, the context index value must be stored in the register before the relevant execution has been processed but still executing the regular mode instructions. Once the context index value of the current state is transmitted through the regular mode commands, the BAC engine 230 may calculate state conversion table data and range table data corresponding to the context index value.

Thereafter, the BAC engine 230 may receive the bitstream from the register 300 for an arithmetic coding process. When the processes are completed, the context index value and the decoding bits for the next state may be output. In addition, if the bitstream has been used, the bitstream location information indicating the location of the bitstream may be changed so that it can be used for subsequent processing.

In the BAC engine 230, the updated context index value may be stored in the destination register dr, and the output bit may be stored in the source register sr. As described above, the CABAC decoding apparatus based on the application-specific instruction processor according to an embodiment of the present invention includes the microprocessor core unit 210 that receives and processes the video signal, and the BAC that processes and outputs the updated context index value and the decoding bit. Since all engines 230 are included, it may be possible to perform context-adaptive variable-length coding in parallel.

6 is a block diagram illustrating a bypass mode processing process of a binary arithmetic coding engine unit according to an embodiment of the present invention.

Referring to FIG. 6 , when the CABAC decoding apparatus processes an input signal in the bypass mode, the microprocessor core unit 210 , the BAC engine 230 , and the register 300 are activated to process the input signal. have.

In the bypass mode, the register 300 may include a destination register dr that stores an output bit. When the bypass mode is executed, the BAC engine 230 may execute the process with a fixed probability value. Therefore, table data stored in the memory may not be required. The bitstream is used in the register 300, and after the location of the bitstream is adjusted, location information indicating the location may be transferred back to the bitstream register. The decoding bit may be stored in the destination register dr.

The bit output through the BAC engine 23 may be stored in register 300 or combined with bits already decoded. The stored or combined bits may be decoded into syntax elements through syntax processing as needed. In one embodiment, the decoded values may be aligned with various parameters and blocks to generate data for use after processing of the BSP to complete the residual data.

As described above, the CABAC decoding apparatus based on the application-specific instruction processor according to an embodiment of the present invention includes the microprocessor core unit 210 that receives and processes the video signal, and the BAC that processes and outputs the updated context index value and the decoding bit. Since both the engine 230 is included and both the regular mode and the bypass mode are performed using them, it is possible to provide a fast processing speed while minimizing an additional hardware cost.

In order to verify the effect of the CABAC decoding apparatus according to an embodiment of the present invention, the performances of the existing decoding apparatuses and the CABAC decoding apparatus according to the present invention were compared. CABAC decoding apparatus according to an embodiment of the present invention for testing on an application-specific instruction processor platform performing general variable length coding, the BAC engine 230 of the present invention and a new method capable of performing regular mode and bypass mode commands are loaded. The verilog language was used to ensure easy simulation and cycle clarity, and the BAC engine 230 was loaded as a behavioral model.

Also, during verification, the HEVC CABAC decoding process was simulated to verify the BAC engine and instruction execution. The assembly code for HEVC used for platform operation was described using HM 16.5 version as HEVC reference software, and an input bitstream was generated. The generated bitstream and assembly code are input, and the parameter values and residual data decoded in the ASIP platform are compared with the HM 16.5 version decoded values to confirm the modified operation.

A direct comparison between the CABAC decoding apparatus of the present invention and other microprocessor platforms using different instruction groups is not easy. Therefore, in order to indirectly compare the processing performance of image pixels, a CPP (Cycles per pixel) value was calculated.

For comparison with the CABAC decoding apparatus (Experimental Example) according to an embodiment of the present invention, Intel's IA32 (Comparative Example 1) and ARMv7 (Comparative Example 2) based processors were used. For the IA32 of Comparative Example 1, Intel i7-6700 processors were used, and for the ARMv7 of Comparative Example 2, a Cortex-A53 MP4 processor was used. The i7-6700 processor includes 4 cores and can support hyper-threading (8 threads). The Cortex-A53 MP4 processor has four cores. Experimental examples and comparative examples were compared by analyzing a simulation cycle based on a clock used for very-large-scale-integration (VLSI) mounting.

In order to compare the same performance of the HM 16.5 software used in the test, the calculation time was measured by specifying a function section mounted on the platform of the experimental example. In addition, in order to minimize the influence of other factors on the platform of the experimental example, an average of 10 cycles per pixel operation unit was calculated. Comparative Examples 1 and 2 were analyzed on a Linux platform to ensure optimal performance and accurate measurement times. The compiler used in the experiments of the Experimental Examples and Comparative Examples was GCC version 4.9, the HM 16.5 software was compiled using the optimized option O3, and tested as an executable release mode. In order to simplify data comparison and reduce the required time, only one image size of 704 x 576 pixel resolution was considered, and the decoding result for the intra frame will also be compared using only the HEVC main profile. This comparison result is shown in FIG. 7 .

7 is an image of an image decoded by a decoding method according to an embodiment of the present invention, and FIGS. 8A and 8B are a decoding apparatus (experimental example) and a general image signal decoding apparatus according to an embodiment of the present invention ( The pixel unit processing cycle of Comparative Examples 1 and 2) is shown.

Referring to FIG. 8 , it can be seen that the CABAC decoding apparatus of the experimental example is 9.91 to 22.74 CPP, and the decoding apparatus of Comparative Examples 1 and 2 is 18.52 to 40.10 CPP and 9.91 to 22.74 CPP. It can be seen that the CPP value of the decoding apparatus of the experimental example is reduced by about 1.76 to 7.69 compared to Comparative Examples 1 and 2.

Therefore, the CABAC decoding apparatus of the present invention includes a binary arithmetic coding engine in an application-specific instruction processor (ASIP) that can use parallel processing and a lookup table, so that it is possible to minimize the added hardware cost and provide a fast processing speed. have.

It is common in the art to which the present invention pertains that the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It will be clear to those who have knowledge.

Claims (12)

A method of performing CABAC decoding using an application-specific instruction processor, the method comprising:
receiving an image signal;
receiving type information of the video signal;
outputting at least one of a context index value and a decoding bit updated based on at least one of a context index value and the video signal according to the type information,
The type information includes regular mode information for updating the context index value and bypass mode information in which the context index value update is not performed. CABAC decoding method based on an application-specific instruction processor. A method of performing CABAC decoding using an application-specific instruction processor, the method comprising:
receiving an image signal;
receiving type information of the video signal;
outputting at least one of a context index value and a decoding bit updated based on at least one of a context index value and the video signal according to the type information,
The step of outputting at least one of the updated context index value and the decoding bit is performed simultaneously with receiving the video signal. CABAC decoding method based on an application-specific command processor. delete The method of claim 1,
When the type information is regular mode information,
Outputting at least one of the updated context index value and the decoding bit comprises:
checking whether the context index value of the current state is stored in the register;
when the context index value of the current state is stored, calculating a state conversion table and a range table corresponding to the context index value using the stored context index value;
performing arithmetic coding using the video signal, the state conversion table, and the range table;
outputting the updated context index value calculated during the arithmetic coding and the decoding bit; and
The location information representing the video signal is adjusted to represent the next video signal CABAC decoding method based on an application specific instruction processor. The method of claim 1,
When the type information is bypass mode information,
Outputting at least one of the updated context index value and the decoding bit comprises:
performing arithmetic coding using the video signal and a fixed probability value;
outputting a decoded bit value calculated during the arithmetic coding; and
The location information representing the video signal is adjusted to represent the next video signal CABAC decoding method based on an application specific instruction processor. An apparatus for performing CABAC decoding using an application specific instruction processor, comprising:
a memory for storing the application-specific instructions; and
At least one of a context index and a decoding bit is generated based on the type information of the video signal in order to context-adaptively perform binary arithmetic coding of the video signal, and at least one of the generated context index and decoding bit is used to generate the A syntax processor for coding the video signal,
The type information includes regular mode information for updating the context index value and bypass mode information in which the context index value update is not performed. An apparatus for performing CABAC decoding using an application specific instruction processor, comprising:
a memory for storing the application-specific instructions; and
At least one of a context index and a decoding bit is generated based on the type information of the video signal in order to context-adaptively perform binary arithmetic coding of the video signal, and at least one of the generated context index and decoding bit is used to generate the A syntax processor for coding the video signal,
The syntax processor,
a VLC engine that performs variable length coding on the video signal;
a BAC engine for performing binary arithmetic coding on the video signal;
an RLC engine that performs run-length coding on the video signal; and
CABAC decoding apparatus based on an application-specific instruction processor comprising a microprocessor core for controlling whether the VLC engine, the BAC engine, and the RLC engine perform coding and a command related to the coding. 8. The method of claim 7,
The BAC engine is
a microprocessor core unit that executes an instruction based on the type information;
BAC for receiving the type information and the context index value of the current state from the microprocessor core unit, receiving the updated context index value when the context index value is updated, and outputting a decoding bit value for the video signal control unit; and
A state conversion table and a range table corresponding to the context index value are calculated using the context index value, and arithmetic coding is performed using the video signal, the state conversion table, and the range table, and when the arithmetic coding is performed CABAC decoding apparatus based on an application-specific instruction processor including a BAC engine core for outputting at least one of the calculated updated context index value and the decoding bit. 9. The method of claim 8,
When the type information is regular mode information,
The BAC control unit outputs the updated context index value and the decoding bit value to the microprocessor core unit,
The BAC engine core unit outputs both the updated context index value and the decoding bit value to the BAC control unit, an application-specific command processor-based CABAC decoding apparatus. 9. The method of claim 8,
When the type information is bypass mode information,
The BAC control unit outputs the decoding bit value to the microprocessor core unit,
CABAC decoding apparatus based on an application-specific command processor for outputting the decoded bit value to the BAC control unit using a fixed probability value and the image signal using the BAC engine core unit. An apparatus for performing CABAC decoding using an application specific instruction processor, comprising:
At least one of a context index and a decoding bit is generated based on the type information of the video signal in order to context-adaptively perform binary arithmetic coding of the video signal, and at least one of the generated context index and decoding bit is used to generate the a syntax processor for coding an image signal;
a memory for storing the application-specific instruction, state conversion table data, and range table data corresponding to the generated context index; and
CABAC decoding apparatus based on an application-specific instruction processor including a register for storing the generated context index, the decoding bit, and the video signal. 12. The method of claim 11,
CABAC decoding apparatus based on an application-specific command processor further comprising a BAC engine core for outputting at least one of the generated context index and the decoding bit and simultaneously receiving the video signal.

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