KR102266156B1 - Pulse transformer circuit with adjustable negative voltage potential - Google Patents

Abstract

Disclosed is a pulse transformer circuit capable of adjusting negative voltage potential. The pulse transformer circuit comprises a transformer, a transistor connected to the secondary side of the transformer, a second resistor connected to the secondary side of the transformer and connected to a base or gate of the transistor, and a third resistor connected to the other end of the transformer include Here, a voltage corresponding to the transistor and the third resistor is a voltage of an output terminal, a voltage of the output terminal is a negative voltage, and the negative voltage varies according to a value of the second resistor.

Description

Pulse transformer circuit with negative voltage potential control {PULSE TRANSFORMER CIRCUIT WITH ADJUSTABLE NEGATIVE VOLTAGE POTENTIAL}

The present invention relates to a pulse transformer circuit capable of controlling a negative voltage potential.

Pulse Transformers are one of a variety of transformer families designed to transmit digital control signals from a control circuit to a load.

Recently, there are cases where a negative voltage is required for a device, for example, a negative voltage needs to be applied to the gate of a silicon carbide (SiC) FET, but there is no suitable pulse transformer circuit. In particular, there is no pulse transformer circuit with adjustable negative voltage.

US 10-1879721 B

An object of the present invention is to provide a pulse transformer circuit capable of controlling a negative voltage potential.

In order to achieve the above object, a pulse transformer circuit according to an embodiment of the present invention includes a transformer; a transistor connected to the secondary side of the transformer; a second resistor coupled to the secondary side of the transformer and coupled to a base or gate of the transistor; and a third resistor connected to the other end of the transformer. Here, a voltage corresponding to the transistor and the third resistor is a voltage of an output terminal, a voltage of the output terminal is a negative voltage, and the negative voltage varies according to a value of the second resistor.

A gate driver circuit for supplying a negative voltage to a device according to an embodiment of the present invention includes: a transformer; and a transistor connected to the secondary side of the transformer. Here, the gate driver circuit generates a negative voltage, and the magnitude of the negative voltage input to the gate of the device is changed by adjusting the voltage applied to the base or gate of the transistor.

In the pulse transformer circuit according to the present invention, a transistor is connected to the secondary side of the transformer, and the magnitude of the negative voltage output through the output terminal can be adjusted by adjusting the value of the resistance connected to the base of the transistor. Therefore, it is possible to apply a negative voltage to a device requiring a negative voltage to supply a bidirectional voltage instead of a unidirectional voltage, and the pulse transformer circuit can be applied to various devices.

1 is a diagram illustrating a pulse transformer circuit according to an embodiment of the present invention.
2 is a view showing an equivalent circuit for viewing the current flow of the pulse transformer circuit excluding the transformer.
3 and 4 are diagrams illustrating current flow in an equivalent circuit according to an embodiment of the present invention.
5 is a diagram illustrating an equivalent circuit implemented by PSIM.
6 is a diagram illustrating a PSIM result waveform.
7 is a diagram illustrating an approximate waveform _{of V X .}
8 is a diagram illustrating a V _{gs waveform.}

As used herein, the singular expression includes the plural expression unless the context clearly dictates otherwise. In this specification, terms such as “consisting of” or “comprising” should not be construed as necessarily including all of the various components or various steps described in the specification, some of which components or some steps are It should be construed that it may not include, or may further include additional components or steps. In addition, terms such as "...unit" and "module" described in the specification mean a unit that processes at least one function or operation, which may be implemented as hardware or software, or a combination of hardware and software. .

The present invention relates to a pulse transformer circuit, which can generate a negative voltage and adjust the negative voltage potential itself.

According to an embodiment, the pulse transformer circuit is, for example, a circuit capable of supplying a negative voltage to the gate of a silicon carbide (SiC) FET, and may be referred to as a gate driver circuit in terms of supplying a voltage to the gate.

For example, the pulse transformer circuit may generate a negative voltage of 0V to -15V, and optimally may generate a negative voltage of -4V or -5V.

In addition, the pulse transformer circuit may generate a pulse voltage of, for example, a minimum of -15V, a maximum of 15V, a positive voltage may be maintained at 15V, and a negative voltage may be adjusted in the range of 0V to 15V.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a pulse transformer circuit according to an embodiment of the present invention.

Referring to Figure 1, the pulse transformer circuit of this embodiment is a transformer, located in the front end (primary side) of the transformer and a power supply (V ₁ ), a capacitor (C ₄ ) and a front-end circuit having a _{resistor (R 4 ), the} Located at the rear end (secondary side), a first diode (D ₁ ), a first resistor (R ₁ ), a second resistor (R ₂ ), a transistor, a second diode (D ₂ ), a third resistor (R ₃ ) and It may include a back-end circuit having a capacitor (C _{3 ).}

The capacitor (C ₄ ) and the resistor (R ₄ ) are connected in series to the power supply (V _{1 ), and one end of the resistor (R 4} ) may be connected to the primary side of the transformer.

A first diode (D ₁ ) is connected to the secondary side of the transformer.

One end of the first resistor R ₁ may be connected in series to the first diode D ₁ , and the other end may be connected to one end of the output side.

The second resistor R ₂ may have one end _{connected in parallel to the first diode D 1} , and the other end connected to the base of the transistor. That is, the second resistor R ₂ has one end connected _{in parallel to the first diode D 1} and the first resistor R ₁ connected in series, and the other end connected to the base of the transistor.

The transistor may be a BJT transistor, the emitter may be _{connected to the first resistor (R 1} ), and the collector may be connected to _{the third resistor (R 3 ).} Of course, the transistor may be a MOS transistor.

One end of the third resistor R ₃ may be connected to the collector of the transistor, and the other end may be connected to the other end of the output side, for example, the ground.

The anode of the second diode D ₂ may be connected between the collector of the transistor and the third resistor R ₃ , and the cathode of the second diode D 2 may be connected between the second resistor R ₂ and the base of the transistor. That is, the second diode D ₂ may control the current direction so that the current flows in a specific direction.

When the base and the collector of the transistor are connected without the second diode D ₂ , the current on the secondary side of the transformer may flow to the third resistor R _{3 through the second resistor R 2 . Accordingly, the second diode D 2} is formed between the base and the collector of the transistor to prevent such current flow from occurring.

The capacitor C ₃ may be connected in parallel with _{the third resistor R 3 while} being connected to the anode of the second diode D _{2 .} The capacitor C ₃ serves to apply an average voltage to the third resistor R _{3 .} Without the capacitor (C ₃ ), a square wave voltage is applied to the third resistor (R _{3 ).}

Hereinafter, a process of adjusting the negative voltage in such a pulse transformer circuit will be described.

2 is a view showing an equivalent circuit for viewing the current flow of the pulse transformer circuit excluding the transformer, FIGS. 3 and 4 are views showing the current flow in the equivalent circuit according to an embodiment of the present invention. 5 is a diagram illustrating an equivalent circuit implemented by PSIM, and FIG. 6 is a diagram illustrating a PSIM result waveform. 7 is _{a diagram illustrating an approximate waveform of V X} , and FIG. 8 is a diagram illustrating a V _gs waveform.

V ₁ is a square wave alternating through a pulse transformer, (V ₁ =±V _a ), and C _gs is the Gate-Source Capacitor of the Power Switch, which does not actually exist.

In order to examine the operation in the equivalent circuit, 1) the transformer secondary output is _{a square wave with positive/negative voltage of (V 1} =±V a ), 2) the switching period of the square wave is T _s , 3) V ₁ When =-V _a , the time ratio is τ, and 4) it is assumed _{that the capacitor (C 3 ) is neglected for convenient analysis.} Also, it is assumed that _{V X} is a voltage applied to the third resistor R _{3 .} Assuming this, the equivalent circuit of FIG. 2 can be obtained.

In the first mode for the equivalent circuit, a high level (V ₁ =+V _a ) may be applied to the equivalent circuit. In this case, a current flow as shown in FIG. 3 is formed.

In the first mode, the first diode D ₁ is activated, the second diode D ₂ is deactivated, and the transistor is also in an Off state. As a result, the voltage (V _{gs ) charged in the capacitor (C gs} ) corresponding to the output is expressed by Equation (1) below.

Here, V _D1,on is a threshold voltage when the first diode D ₁ is turned on. A first resistor (R ₁₎ there is a very short time only by the voltage takes the voltage across the first resistor (R ₁₎ and is ignored, V _X = 0.

In the second mode, a Low Level (V ₁ =-V _a ) may be applied to the equivalent circuit. In this case, a current flow as shown in FIG. 4 is formed.

In the second mode, the first diode D ₁ is deactivated, the second diode D ₂ is activated, and the transistor is on. As a result, the voltage (V _gs) charged in the capacitor (C _gs) is shown in Equation (2).

이 On되었을 때의 문턱 전압이다. where V _D2,on is

It is the threshold voltage when is On.

A waveform is viewed using PSIM to analyze the above two modes, as shown in FIG. 6 . The waveforms are V ₁ , V _gs , V _X , V _{EC in} that order.

이다. The maximum value of _{V gs} in the first mode _{is (V gs} =V _a -V _D1,on ), and the maximum value of _{V gs in the second mode is}

to be.

의 값을 구할 수 있다. 이 때 중요한 점은 V_X 파형에서 제 1 모드가 끝난 직후의 V_X의 최대값부터 제 2 모드가 끝나기 전까지 나타나는 곡선 파형이다. The most important thing in MODE analysis is the average voltage, so assuming that the capacitor (C _VX ) is connected in parallel to _{the third resistor (R 3} ) in the equivalent circuit, the average voltage of _{V X}

value can be obtained. At this time point is a curved waveform that appears before the end of the second mode, since the maximum value of _X V immediately after the end of the first mode in the waveform V _X.

Since it is difficult to interpret such a curved waveform, it can be interpreted as shown in FIG. 7 when approximated.

일 때, 하기 수학식 3을 만족한다. Here, using the voltage-time product equilibrium condition,

When , the following Equation 3 is satisfied.

의 수식을

구간 동안 나타내면 하기 수학식 4와 같다. approximated

the formula of

When expressed during the section, it is expressed as Equation 4 below.

Looking at the equivalent circuit, the factor that determines the magnitude of the negative voltage is R ₂ . When R ₂ increases, V ₁ is ideally a fixed value in the second mode, so the voltage across _{R 2} increases and the voltage across _{R 3 decreases.} That is, I _C decreases. When I _C decreases, V _EC is a characteristic voltage of the transistor and is therefore a fixed value, so the magnitude of the absolute value of _{V gs is finally decreased.} That is, when looking at the waveform, it can be seen that the negative voltage approaches 0 as _{R 2 increases.} When this is confirmed by PSIM, it is shown in FIG. V _gs1 is when R ₂ =50Ω, and V _gs2 is when R ₂ =100Ω.

In summary, the pulse transformer circuit of the present invention connects a transistor to the rear end of the transformer, connects a second resistor (R ₂ ) to the gate of the transistor, and connects a third resistor (R ₃ ) to the collector of the transistor to realize a negative voltage However, the value of the negative voltage may be adjusted to a desired value by adjusting the second resistor R _{2 .}

On the other hand, the components of the above-described embodiment can be easily grasped from a process point of view. That is, each component may be identified as a respective process. In addition, the process of the above-described embodiment can be easily understood from the point of view of the components of the apparatus.

The above-described embodiments of the present invention have been disclosed for the purpose of illustration, and various modifications, changes, and additions will be possible within the spirit and scope of the present invention by those skilled in the art having ordinary knowledge of the present invention, and such modifications, changes and additions should be regarded as belonging to the following claims.

Claims (7)

In the pulse transformer circuit,
Transformers;
a transistor connected to one end of the secondary side of the transformer;
a first diode connected to one end of the secondary side of the transformer;
a first resistor connected in series with the first diode and having one end connected to an emitter of the transistor;
a second resistor connected to one end of the secondary side of the transformer and connected to a base or a gate of the transistor;
a second diode coupled between the collector and the base of the transistor; and
and a third resistor connected to the other end of the secondary side of the transformer and having one end connected to the collector of the transistor,
The second resistor is connected in parallel to the first diode and the first resistor, the anode of the second diode is connected between the collector of the transistor and the third resistor, and the cathode of the second diode is connected to the second resistor. connected between the second resistor and the base of the transistor, wherein a voltage between the emitter of the transistor and the other end of the third resistor is a voltage of an output terminal, the voltage of the output terminal is a negative voltage, and the negative voltage is the second terminal A pulse transformer circuit, characterized in that it varies depending on the value of the resistance. According to claim 1,
and a capacitor connected to the second diode and connected in parallel to the third resistor. 3. The method of claim 2,
In the first mode, the first diode is activated and the transistor and the second diode are deactivated so that the current on the secondary side of the transformer flows to the output terminal through the first diode and the first resistor,
In a second mode, the first diode is deactivated and the transistor and the second diode are activated so that a current flows from the output terminal to the ground through the transistor and the third resistor. 4. The pulse transformer circuit according to claim 3, wherein when the value of the second resistor increases, the voltage applied to the third resistor decreases, so that the negative voltage of the output terminal decreases. A gate driver circuit for supplying a negative voltage to a device, comprising:
Transformers;
a transistor connected to the secondary side of the transformer;
a first resistor coupled between the secondary side of the transformer and the emitter of the transistor;
a second resistor coupled to the base of the transistor; and
a third resistor coupled to the collector of the transistor;
The first resistor and the second resistor are connected in parallel, the gate driver circuit generates a negative voltage, and the negative voltage input to the gate of the device by adjusting the voltage applied to the base or the gate of the transistor A gate driver circuit characterized in that it varies in size. delete 6. The gate driver circuit of claim 5, wherein the device comprises a silicon carbide (SiC) FET that receives the negative voltage to a gate.

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