KR102260819B1 - Multiprocessor interrupt signal processing device - Google Patents

Abstract

According to an embodiment of the present invention, in an interrupt signal processing apparatus including a plurality of peripheral devices and a plurality of processors, the peripheral device generates a packet when an interrupt request signal (IRQ, Interrupt Request) is generated and sends the packet through an on-chip network. transmits to the processor, the processor receives the packet and executes an operation corresponding to the interrupt request signal, and the peripheral device generates the packet using the designated processor ID and transmits it to the designated processor interface or global interrupt handling controller An interrupt signal processing device is provided.

Description

Multiprocessor interrupt signal processing device

One embodiment of the present invention relates to a multi-processor interrupt signal processing apparatus.

The existing processor-based system is not efficient because communication between the processor and the peripheral device is unidirectional, and in particular, when multiple processors exist, various problems are presented. A processor has the characteristic of operating only as a master by its characteristics. Therefore, communication with the peripheral device, which is a slave, is possible using polling or interrupt. However, most of these days, when the amount of work of the processor is high, the interrupt method is used.

The interrupt method requires a separate interrupt connection line, and when there are a large number of peripheral devices that are slaves, the interrupt controller goes through one more step for signal processing. The processor that has received the interrupt signal must access the peripheral device through the interrupt controller to identify the cause of the interrupt and start responding to it. Therefore, the overhead for the operation of the interrupt is quite large.

Another problem is that for systems with multiple processors, passing interrupt signals is more complex and has more constraints. When there are multiple processors, a problem arises as to where to send the interrupt signal of the peripheral device slave that has received the work request. In addition, in the case of a high-performance interface protocol such as AXI, since the slave receives and stores multiple requests and can process them simultaneously or sequentially, the interrupt processing process becomes more complicated.

An object of the present invention is to provide a multiprocessor interrupt signal processing apparatus capable of simplifying complex interrupt signal processing for multiple processors and increasing efficiency by using the symmetric interface protocol of the present invention.

According to an embodiment of the present invention, in an interrupt signal processing apparatus including a plurality of peripheral devices and a plurality of processors, the peripheral device generates a packet using a designated processor ID when an interrupt request signal (IRQ, Interrupt Request) is generated. and transmits the packet to the processor through the on-chip network, the processor receives the packet and executes an operation corresponding to the interrupt request signal, and the interrupt signal processing device determines that the interrupt request signal is a non-designated interrupt request signal to a peripheral device. It provides an interrupt signal processing device for designating a processor for processing the unspecified interrupt request signal in at least one of an interrupt signal processing device designation method, a global interrupt controller method, a non-designated dedicated interrupt signal processing device method, and a daisy chain method. .

In the method for specifying interrupt signal processing of the peripheral device, the peripheral device may randomly designate a processor connected to the on-chip network, and generate and transmit the packet using the designated processor ID.

The peripheral device may randomly designate one of a large number of processors as the frequency of occurrence of the interrupt request signal increases, and generate and transmit the packet to the designated processor.

When the interrupt request signal is a non-designated interrupt request signal, the processor may designate a processor for processing the non-designated interrupt request signal in consideration of a periodically measured processor load.

The apparatus may further include a global interrupt controller configured to receive the packet from the peripheral device through the on-chip network and designate a processor connected to a plurality of processors to process the interrupt request signal.

In the global interrupt controller method, the global interrupt controller may receive a preparation signal from the plurality of processors, designate a processor for processing the interrupt request signal according to the preparation signal, and transmit an interrupt request packet to the corresponding processor. .

The global interrupt controller and the processor are connected to an on-chip network or an interrupt packet bus, so that the global interrupt controller can transmit the packet to a designated processor through the on-chip network or the interrupt packet bus.

The non-designated dedicated interrupt signal processing apparatus method may transmit the packet by designating in advance a dedicated processor for processing the non-designated interrupt request signal among the plurality of processors.

A plurality of dedicated processors may be designated according to priorities, and when the unspecified interrupt request signals are accumulated, they may be allocated according to priorities.

In the daisy chain method, interrupt packets are transmitted to all processor interfaces, and each processor interface may sequentially determine whether to process the unspecified interrupt request signal using an enable signal received from a processor interface located at the front end.

The interrupt signal processing apparatus provides an interrupt signal processing apparatus in which a peripheral device designates a processor in common in the non-designated interrupt processing method when the interrupt request signal is a designated interrupt request signal.

By using the multiprocessor asymmetric interface protocol of the present invention, it is possible to simplify complex interrupt signal processing for multiple processors and increase efficiency.

In addition, packet-based interrupt signal transmission may be performed.

In addition, on-chip network-based interrupt signal processing can be performed.

In addition, interrupt signals can be processed without a separate interrupt connection line.

In addition, access to the network can be minimized in processing the interrupt signal.

In addition, it is possible to reduce the overhead due to network access.

It is also compatible with existing processor architectures.

1 is a block diagram of an interrupt signal processing apparatus according to an embodiment of the present invention.
2 is a diagram for explaining an operation of an interrupt signal processing apparatus according to an embodiment of the present invention.
3 is a diagram for explaining the configuration and operation of a processor interface according to an embodiment of the present invention.
4 to 8 are diagrams for explaining the operation of an interrupt signal processing apparatus according to an embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical spirit of the present invention is not limited to some embodiments described, but may be implemented in various different forms, and within the scope of the technical spirit of the present invention, one or more of the components may be selected between the embodiments. It can be combined and substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be generally understood by those of ordinary skill in the art to which the present invention belongs, unless specifically defined and described explicitly. It may be interpreted as a meaning, and generally used terms such as terms defined in advance may be interpreted in consideration of the contextual meaning of the related art.

In addition, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In the present specification, the singular form may also include the plural form unless otherwise specified in the phrase, and when it is described as "at least one (or more than one) of A and (and) B, C", it is combined with A, B, C It may include one or more of all possible combinations.

In addition, in describing the components of the embodiment of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

These terms are only used to distinguish the component from other components, and are not limited to the essence, order, or order of the component by the term.

And, when it is described that a component is 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected, coupled or connected to the other component, but also with the component It may also include a case of 'connected', 'coupled' or 'connected' due to another element between the other elements.

In addition, when it is described as being formed or disposed on "above (above) or below (below)" of each component, the top (above) or bottom (below) is one as well as when two components are in direct contact with each other. Also includes a case in which another component as described above is formed or disposed between two components. In addition, when expressed as "upper (upper) or lower (lower)", the meaning of not only an upper direction but also a lower direction based on one component may be included.

Hereinafter, the embodiment will be described in detail with reference to the accompanying drawings, but regardless of the reference numerals, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted.

1 is a block diagram of an interrupt signal processing apparatus according to an embodiment of the present invention.

Referring to FIG. 1 , an interrupt signal processing apparatus 10 according to an embodiment of the present invention may include a plurality of peripheral devices 11 and a plurality of processors 13 . Each processor 13 may be configured to include a processor interface 12 including an input interface 20 and an output interface 30 .

In an embodiment, the processor 13 is operatively connected to the on-chip network through the processor interface 12 , and the processor 13 and the processor interface 12 are configured to send and receive data by internal logic. The peripheral device 11 and the processor interface 12 may perform data communication through an on-chip network.

In an embodiment, the processor interface 12 and the peripheral device 11 may simultaneously perform master and slave functions, respectively. That is, each of the processor interface 12 and the peripheral device 11 may independently initiate communication through the on-chip network. The processor interface 12 and the peripheral device 11 have interfaces that operate independently in the input direction and the output direction are connected to the on-chip network, so that they can simultaneously serve as a master and a slave, respectively.

Through such a symmetric interface protocol, the processor 13 makes a job request to the peripheral device 11 that is a slave and receives the result, or the peripheral device 11 communicates with the processor 13 by an external input. In the same way as a processor, it can initiate communication forwarding packets. An interrupt controller 22 coupled to the input channel of the processor interface 12 processes the input packets. Through this, an unnecessary process for interrupt processing can be eliminated, and an interrupt operation can be completed with a minimum number of operations.

The peripheral device 11 may generate a packet when an interrupt request signal (IRQ, Interrupt Request) is generated and transmit it to the processor interface 12 through the on-chip network.

When the interrupt request signal is a designated interrupt request signal, the peripheral device 11 may generate and transmit a packet using the designated processor ID.

In an embodiment, the packet may include interrupt status information and data.

The interrupt status information may include peripheral device ID (DID), priority (PR), task ID (TID), and number of attached data (NAD).

Table 1 shows interrupt status information according to the embodiment. The peripheral device ID (DID) may include a unique number of the peripheral device that generated the packet. The priority (PR) indicates the priority of interrupt processing, and a system designer can define and use a specific usage method as needed. Task ID (TID) defines the contents of an interrupt request, and when two or more different tasks are performed simultaneously or sequentially, it can be used to select an interrupt service routine (ISR) for the task. When the interrupt controller 22 recognizes the DID and the TID, when the processor 13 executes the interrupt service routine, only the DID is recognized or the DID and the TID are recognized together to supply the interrupt service routine instruction. Alternatively, the interrupt controller 22 may not recognize the DID and TID, and after executing the interrupt service routine in the processor 13 , a necessary operation may be performed after checking the DID and TID. In this case, the processor 13 may execute a single interrupt service routine or an interrupt service routine by DID. The number of attached data (NAD) indicates how many data are included in the packet, and may be stored in the shared data memory 21 of the input interface 20 . When the processor 13 accesses the peripheral device 11 and requests a read of the attached data, the data controller 23 anticipates this and checks the address, and then the shared data memory 21 that has already been stored without access to the peripheral device 11 data may be supplied to the processor 13 . In an embodiment of the present invention, the shared data memory and the buffer may be used interchangeably.

Also, the peripheral device 11 may access the memory 14 according to the size of the packet and store the packet. This will be described later.

The processor interface 12 receives and decodes the packet to transmit an interrupt request signal to the processor 13 , and receives an interrupt vector generated from the processor 13 and transmits an instruction corresponding to the activated interrupt signal to the processor 13 . can Here, the interrupt vector refers to the address where the code of the interrupt service routine is stored.

The processor interface 12 may include an input interface 20 and an output interface 30 .

The input interface 20 includes a buffer 21 for storing packets, a signal with the interrupt controller 22 and the processor 13 for receiving and decoding the packets, and generating instructions using the interrupt vector table and information contained in the packets. It may include a data controller 23 that performs the transfer.

The output interface 30 may receive the interrupt vector and transmit it to the input interface 20 , and may transmit a request packet to the peripheral device 11 .

Processor interface 12 may also access memory 14 to decode packets.

The input interface 20 may receive the packet and decode it through the interrupt controller 22 . In addition, the ID and data of the peripheral device 11 that sent the packet are stored in the buffer and an interrupt request signal is transmitted to the processor 13 . At this time, if there is an interrupt job waiting, the waiting order may be changed according to the priority policy.

The output interface 30 processes an access request to the memory and the peripheral device 11 of the processor 13. In the case of an operation related to interrupt processing, the output interface 30 detects the address for the request and sends a packet to the network. Instead of sending out the data or commands, directly required data or commands are transmitted to the processor 13 through communication with the input interface 20 .

The processor 13 may receive the packet and execute an operation corresponding to the interrupt request signal.

The processor 13 may output an interrupt vector in response to the interrupt request signal and execute a corresponding interrupt service routine (ISR) according to the instruction.

The processor 13 receives the interrupt request signal from the input interface 20 and outputs an interrupt vector. Thereafter, the processor 13 may execute a task related to the interrupt request signal according to the instruction received from the data controller 23 or may modify a process state variable to execute a task related to the interrupt request signal later. After that, if there are more interrupt request signals not retrieved by the processor 13 in the interrupt queue, the processor 13 continues to receive the interrupt request signal from the input interface 20 . In response to receiving the interrupt signal, the processor 13 continues to retrieve the interrupt request signal from the interrupt queue and executes tasks related to these interrupt request signals until the queue in the interrupt queue is cleared.

FIG. 2 is a diagram for explaining a processor interface and an operation of a processor according to an embodiment of the present invention, and FIG. 3 is a diagram for explaining a configuration and operation of a processor interface according to an embodiment of the present invention.

2 and 3, when the processor 13 generates an interrupt vector in response to the interrupt request signal, the output interface 30 intercepts it, and the input interface 20 corresponds to the currently activated interrupt signal. An instruction is sent to the processor 13 that can start an interrupt service routine. At this time, different interrupt service routines may exist depending on the peripheral device and the type of operation, and the input interface 20 has the peripheral device 11 and the interrupt vector table 24 according to the operation, and the peripheral device 11 Knowing the information passed, we can send a command to start the appropriate interrupt service routine. Accordingly, the processor 13 can immediately start a necessary interrupt service routine without knowing the operation corresponding to the interrupt.

When the interrupt service routine is executed, the data sent by the peripheral device 11 is stored in the buffer 21 , so the output interface 30 recognizes it and transmits the request to the input interface 20 to send the data directly to the processor 13 . can This is possible because, unlike the existing system, the input interface 20 performs a slave role and an address can be assigned to the input interface 20 . When an address is assigned to the buffer 21 , the peripheral device 11 may store the corresponding data in the buffer 21 of the input interface 20 . Through this, data transmission of a small capacity can be completed between the processor 13 and the interface 12 without access to the network. However, when the data capacity is large or a write operation is performed, the processor 13 may directly access the peripheral device 11 or perform the operation through the memory 14 . In the case of having a symmetric interface, since all devices can initiate communication, the peripheral device 11 directly accesses the memory 14 by the instruction of the processor 13 to store related information and data, and the processor 13 stores the memory (14) can be accessed and dealt with. Upon completion of the interrupt service routine, the processor 13 may return to a previous state. An arrow indicated by a dotted line in FIG. 2 indicates a case in which an operation is performed through the memory 14 and occurs only when necessary, such as when the data capacity is large or a write operation is performed, and the frequency thereof is low.

In the processor interface 12 having a symmetric interface protocol according to an embodiment, incoming and outgoing channels exist at the same time, and they may operate independently of each other.

A response packet according to the request of the processor 13 may be transmitted to the processor 13 through the data controller 23 . Since all packets transmitted from the outside to the processor 13 are interrupt request signals, the interrupt controller 22 can process them.

The interrupt controller 22 may analyze the packet to determine which peripheral device 11 is requesting from the peripheral device ID, and determine the interrupt service routine to be executed by analyzing the interrupt status information. The interrupt status information includes information necessary for interrupt processing and may include peripheral device ID (DID), priority (PR), task ID (TID), and number of attached data (NAD) as shown in Table 1.

Interrupt queue ID (IRQ ID) and priority (PR) are stored in the interrupt queue (IRQ) 25 according to the status information analysis result. If the queue is not empty, the priority of the already stored interrupt request signal (PR) can be compared, and the storage location can be determined according to the priority (PR). Through this, the input interrupt request signal is executed according to the priority (PR). That is, the higher the priority of the interrupt request signal, the higher the position of the interrupt queue 25 .

At the same time, the interrupt status (IRQ Status) register 26 stores an interrupt queue ID (IRQ ID), a peripheral device ID (DID), an operation ID (TID), the number of attached data (NAD), or an interrupt vector corresponding to an interrupt service routine. It can store the address of the table (IRQ vector table). Using this, when the processor 13 requests an interrupt service routine in the interrupt mode, a corresponding instruction is read from the interrupt vector table 24 and transmitted through the data controller 23 . The first instruction or address of each interrupt service routine is designated in the interrupt vector table 24, and thereafter, the memory 14 may be accessed to execute the interrupt service routine. Therefore, the storage space for the interrupt vector table 24 is not large. Tables can also be shared when multiple processors exist. Thereafter, data may be stored in the shared data memory 21 according to the value of the number of attached data NAD, and a corresponding start address may be stored in the interrupt status register 26 .

The size of the interrupt queue 25 determines the number of interrupt request signals that can be simultaneously processed, and the data storage capacity of the shared data memory 21 determines the maximum size of data that can be sent to the processor 13 when an interrupt is requested from a peripheral device. can decide This data allows the processor 13 to quickly read the necessary data without accessing the peripheral device 11 . When multiple processors exist, the size may be reduced if each processor 13 shares the data storage space in order to increase the efficiency of the storage space.

The interrupt vector table 24 of the input interface 20 may include the address of the memory 14 in which the interrupt service routine is stored along with the first instruction of the interrupt service routine. Therefore, it is possible to send a signal to the cache controller (not shown) to read the corresponding interrupt service routine code into the instruction cache in advance. In this case, the waiting time can be reduced by the number of cycles from sending an interrupt request signal to executing the first instruction.

4 is a diagram for explaining an operation of an interrupt signal processing apparatus according to an embodiment of the present invention. Referring to FIG. 4 , when the interrupt request signal is a designated interrupt request signal, the peripheral device 11 may generate and transmit a packet using the designated processor ID.

When a specific interrupt request signal generation situation occurs, the peripheral device 11 may generate a packet based on the ID of the corresponding processor in the interface logic, and may transmit the generated packet to the processor interface 12 through the on-chip network.

In a system having a symmetric interface, when the peripheral device 11 completes one task and generates an interrupt, a packet may be generated and delivered to the input interface address of the corresponding processor using the stored processor ID. This is possible because the peripheral device 11 and the processor 13 can perform 1:1 communication in both directions.

Therefore, when a designated interrupt request signal is generated, the processor 13 designates the processor 13 for processing the designated interrupt request signal or generates and transmits a packet to the processor 13 designated in advance in the peripheral device 11 will do When a specific processor 13 is designated, the existing commercial system operates under limited conditions, but in the embodiment of the present invention, the interrupt request signal can be processed without any limitation.

In the embodiment, when an interrupt request signal is generated, a packet can be generated according to the stored processor ID and directly transmitted to the corresponding processor 13 , so that an interrupt request can be made regardless of the number of processors 13 . Also, even if the number of processors 13 increases, interrupt requests can be processed in the same manner as in the case of one processor 13 without adding circuits or connecting lines.

In an embodiment, the designated interrupt request signal may mean an interrupt request signal generated in a state in which the processor 13 for processing a corresponding interrupt is designated. In addition, the non-designated interrupt request signal may mean an interrupt request signal generated in a state in which the processor 13 for processing the corresponding interrupt is not designated. In the case of a non-designated interrupt request signal, the processor 13 for processing the corresponding interrupt may be designated according to an embodiment described below.

Hereinafter, in an embodiment of the present invention, when the interrupt request signal is a non-designated interrupt request signal, the interrupt signal processing device includes at least one of a peripheral device interrupt signal processing designation scheme, a global interrupt controller scheme, a non-designated dedicated interrupt signal processing device scheme, and a daisy chain scheme You can designate the processor to handle the unspecified interrupt request signal in the manner of

In one embodiment, when the interrupt request signal is a non-specified interrupt request signal, the peripheral device 11 arbitrarily designates the processor 13 connected to the on-chip network according to the interrupt signal processing designation method of the peripheral device, and uses the designated processor ID to create a packet and forward it.

At this time, the peripheral device 11 may arbitrarily designate one of a large number of processors 13 as the frequency of occurrence of the interrupt request signal increases, and generate and transmit a packet to the designated processor 13 .

When the peripheral device 11 designates the processor 13 for processing the unspecified interrupt request signal by itself, a combination of the peripheral device 11 and the processor 13 is configured, and a dedicated processor 13 for each peripheral device 11 or may designate the processor 13 according to a predetermined algorithm. When there is a large difference in the frequency of interrupts for each peripheral device 11 , the method of designating the dedicated processor 13 for each peripheral device 11 may increase the load of a specific processor and when the workload of the specific processor 13 is large Interrupt processing of the connected peripheral device 11 may be delayed. Therefore, the method of designating the dedicated processor 13 for each peripheral device 11 is effective when the amount of interrupt generation in the peripheral device 11 is similar.

When the peripheral device 11 designates the processor 13 by itself, since it is determined without knowing the load amount of the processor 13 , a difference occurs in interrupt processing efficiency according to the load condition of the processor 13 . Also, when several peripheral devices 11 operate in the same manner, an interrupt request may be rushed to a specific processor 13 at any moment. In this case, the goal is to prevent the interrupt processing load from being concentrated on a specific processor 13 by distributing the interrupt request of the peripheral device 11 to several processors 13 , but it is decided without knowing the load situation of the processor 13 . Therefore, there is a problem in that it is always difficult to evenly distribute the load to the processors 13 .

Therefore, when there is a large deviation in the amount of interrupts generated by the peripheral devices 11, the peripheral device 11 with a high frequency of interruption requests to distribute interrupts to several processors 13, and the peripheral device 11 with a low frequency of occurrence of the interrupt requests a specific processor. It is effective to make an interrupt request by designating (13) or a smaller number of processors (13).

In another embodiment, when the interrupt request signal is a non-designated interrupt request signal, the processor 13 may designate the processor 13 for processing the non-designated interrupt request signal in consideration of the periodically measured load amount of the processor 13. have. This method of considering the load amount of the processor 13 may be applied to a method of designating a processor to process all non-designated interrupt request signals according to an embodiment of the present invention. That is, the processor can be designated by additionally considering the method of considering the load of the processor in the interrupt signal processing designation method of the peripheral device, the global interrupt controller method, the non-designated dedicated interrupt signal processing device method and the daisy chain method.

When the processor 13 sets the peripheral device 11 , it is possible to designate the connected processor 13 for each peripheral device 11 according to the operating state of the processor 13 in software, so that dynamic allocation is possible. This method has the advantage of being able to designate the processor 13 for interrupt processing in a simple manner and efficiently utilize the resources of the processor 13 .

In another embodiment, the global interrupt controller 40 receives packets from the peripheral device 11 through the on-chip network, and is connected to the plurality of processors 13 to determine the processor 13 for processing the interrupt request signal. may further include.

5 and 6 are diagrams for explaining an operation of an interrupt signal processing apparatus according to an embodiment of the present invention.

Referring to FIG. 5 , when the interrupt request signal is a non-designated interrupt request signal, the global interrupt controller 40 receives the preparation signals from the plurality of processors 13 according to the global interrupt controller method, and receives the interrupt request signal according to the preparation signal. By designating the processor 13 for processing , the interrupt request packet may be delivered to the corresponding processor.

The peripheral device 11 transmits an unspecified interrupt request signal to the global interrupt controller 40 using a symmetric interface. The global interrupt controller 40 checks the ready signal IRQ_RDY sent from the interrupt controller 22 of each processor 13 and designates one of the processors 13 capable of processing the interrupt request signal. The global interrupt controller 40 forwards the packet back to the designated processor 13 through the network.

That is, the interrupt controller 22 of each processor receives status information such as resource availability status and load status of the processor 13 from the processor 13 and transmits it to the global interrupt controller 40 . The global interrupt controller 40 receives the packet, designates the processor 13 to process it according to the ready signal, and delivers the packet to the input interface of the designated processor 13 .

Referring to FIG. 6 , the global interrupt controller 40 and the processor 13 are connected to the on-chip network or the interrupt packet bus 50 , and the global interrupt controller 40 is connected to the on-chip network or the interrupt packet bus 50 through the on-chip network or the interrupt packet bus 50 . The packet may be forwarded to the designated processor 13 . In the case of accessing the network to transfer a packet from the global interrupt controller 40 to the input interface 20 of the processor 13, when the latency is large, the interrupt controller 22 of each processor 13 and the global interrupt An interrupt packet bus (IPB) 50 is generated between the routers (not shown) of the controller 40, and the processor 13 is designated at the same time that a packet is inputted through the interrupt packet bus 50 to the designated processor 13 can be passed to

The global interrupt controller 40 routes the packet to the input interface 20 of the designated processor 13 according to the ready signal every cycle to immediately deliver the packet through the interrupt packet bus, so there is no latency period.

In addition, QoS transmission or priority transfer may be supported. Since QoS transmission is prioritized in the on-chip network, packets can be delivered to the destination the fastest, which is more effective than generating the interrupt packet bus 50 . Interrupt packets require rapid processing, but are suitable for QoS transmission because the packet size is small and the frequency of occurrence is relatively low. An interrupt packet sent from the peripheral device 11 and a packet for the processor 13 to set the global interrupt controller 40 may be transmitted to the global interrupt controller 40 . At this time, the global interrupt controller 40 analyzes the header of the packet to determine whether it is an interrupt packet or a global interrupt controller setting packet, and in the case of the global interrupt setting packet, the global interrupt controller 40 can process it.

7 is a diagram for explaining an operation of an interrupt signal processing apparatus according to an embodiment of the present invention. Referring to FIG. 7 , when the interrupt request signal is a non-designated interrupt request signal, a dedicated processor 13-1 (dotted line) for processing a non-designated interrupt request signal among a plurality of processors 13 according to a non-designated dedicated interrupt signal processing apparatus method You can forward the packet by specifying the box mark in advance. That is, a part of the plurality of processors 13 may be designated in advance as the processor 13-1 dedicated to the non-designated interrupt request signal.

At this time, the input interface of the dedicated processor 13-1 may be configured to include an interrupt status register file, an interrupt queue, and a buffer having a relatively larger capacity compared to the input interface of the unspecified processor 13. .

The peripheral device 11 transmits a packet of a designated interrupt request signal to the corresponding processor 13 according to the processor ID, and transmits a packet of a non-designated interrupt request signal to the designated dedicated processor 13-1. In this way, the proper load balancing policy of the operating system may affect its performance. Since the dedicated processor 13 - 1 has to preferentially process the interrupt request, the operating system may set a relatively small task assignment for the dedicated processor 13 - 1 . In addition, the input interface of the dedicated processor 13-1 may transfer some packets to another dedicated processor 13-2 according to a predetermined policy when interrupt requests are accumulated in the queue of the interrupt queue beyond a certain limit. That is, when the plurality of processors 13-1 and 13-2 are designated exclusively and priorities are set, if unspecified interrupt request signals are accumulated, they can be distributed according to the priorities.

8 is a diagram for explaining an operation of an interrupt signal processing apparatus according to an embodiment of the present invention. Referring to FIG. 8, when the interrupt request signal is a non-designated interrupt request signal, according to the daisy chain method, an interrupt packet is transmitted to all processor interfaces 12, and each processor interface 12 is Whether to process the unspecified interrupt request signal may be sequentially determined using the received enable signal IRQ_EN.

The input interface 20 of each processor interface 12 is not independently connected to the on-chip network, but is connected through one port, so that the packets generated by the peripheral device 11 are input interfaces of all processor interfaces 12 . (20) can be transmitted simultaneously.

The input interface 20 of each processor interface 12 may be connected in a daisy chain manner to transmit the enable signal IRQ_EN. Each enable signal is sequentially transmitted to the input interface 20 of the processor interface 12 located at the relatively rear end.

When a packet of a designated interrupt request signal is input, each input interface 20 reads and processes the packet only when it is designated by checking the header of the packet.

When a packet of a non-designated interrupt request signal is input, it is possible to sequentially determine whether to process an interrupt from the input interface 20 of the first processor interface, and transmit it to the input interface 20 of the processor interface located at the rear end.

The input interface 20 of each processor interface deactivates the enable signal when it processes an interrupt, and activates it when it does not process the interrupt. When the enable signal is activated, the input interface 20 of the processor interface located at the rear end determines whether to process an interrupt and whether to activate its own enable signal.

Therefore, except for the first processor interface, it is possible to determine whether to process the unspecified interrupt request signal according to the state of the processor only when the enable signal is activated. The input interface of the last processor interface located at the end unconditionally processes the unspecified interrupt request signal when the enable signal is activated.

This method has an advantage that the interrupt request signal can be processed by reflecting the state of the processor by adding only one enable signal line between the input interfaces 20 . However, since the plurality of processor input interfaces 20 can receive only one packet at a time, a latency period may occur when a plurality of interrupt request signals are generated at the same time. to be.

All of the non-designated interrupt processing methods shown in FIGS. 5 to 8 are applicable to the designated interrupt processing methods.

The term '~ unit' used in this embodiment means software or a hardware component such as a field-programmable gate array (FPGA) or ASIC, and '~ unit' performs certain roles. However, '-part' is not limited to software or hardware. The '~ unit' may be configured to reside on an addressable storage medium or may be configured to refresh one or more processors. Thus, as an example, '~' refers to components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, and procedures. , subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. The functions provided in the components and '~ units' may be combined into a smaller number of components and '~ units' or further separated into additional components and '~ units'. In addition, components and '~ units' may be implemented to play one or more CPUs in a device or secure multimedia card.

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it can be done.

10: Interrupt signal processing unit
11: Peripherals
12: Processor Interface
13: Processor
14: memory

Claims (10)

An interrupt signal processing apparatus comprising a plurality of peripheral devices, a plurality of processor interfaces, and a plurality of processors, the interrupt signal processing apparatus comprising:
When an interrupt request signal (IRQ, Interrupt Request) is generated, the peripheral device generates a packet including a peripheral device ID and a task ID using a designated processor ID and transmits it to the processor interface through the on-chip network,
The processor interface receives and decodes the packet, transmits the interrupt request signal to the processor, receives the interrupt vector generated from the processor, and transmits instructions and data corresponding to the activated interrupt signal from the IC memory inside the interrupt controller. passed to the processor
The processor receives the packet from the processor interface and executes an operation corresponding to the interrupt request signal,
The processor and the processor interface exchange data by internal logic, and the peripheral device and the processor interface perform data communication through an on-chip network,
When the interrupt request signal is a non-designated interrupt request signal, the interrupt signal processing device uses at least one of a peripheral device interrupt signal processing designation scheme, a global interrupt controller scheme, a non-designated dedicated interrupt signal processing device scheme, and a daisy chain scheme. Specifies the processor to handle the interrupt request signal,
In the global interrupt controller method, the global interrupt controller receives the packet from the peripheral device through the on-chip network, and is connected to a plurality of processors to designate a processor for processing the interrupt request signal, a preparation signal from the plurality of processors. and, according to the preparation signal, designate a processor for processing the interrupt request signal, and transmit the interrupt request packet to a processor interface of the corresponding processor.
According to claim 1,
In the interrupt signal processing designation method of the peripheral device, the peripheral device arbitrarily designates a processor connected to the on-chip network, and generates and transmits the packet using the designated processor ID.
3. The method of claim 2,
The peripheral device arbitrarily designates one of a large number of processors as the frequency of occurrence of the interrupt request signal increases, and generates and transmits the packet to the designated processor.
According to claim 1,
When the interrupt request signal is a non-designated interrupt request signal, the processor designates a processor for processing the non-designated interrupt request signal in consideration of a periodically measured load amount of the processor.
delete delete According to claim 1,
The global interrupt controller and the processor are connected to an on-chip network or an interrupt packet bus, and the global interrupt controller transmits the packet to a designated processor through the on-chip network or the interrupt packet bus.
According to claim 1,
In the non-designated dedicated interrupt signal processing device method, the interrupt signal processing device transmits the packet by designating in advance a dedicated processor for processing the non-designated interrupt request signal from among the plurality of processors.
9. The method of claim 8,
A plurality of the dedicated processor is designated according to a priority, and when the non-designated interrupt request signals are accumulated, the interrupt signal processing apparatus is allocated according to the priority.
According to claim 1,
In the daisy chain method, interrupt packets are delivered to all processor interfaces, and each processor interface sequentially determines whether to process the unspecified interrupt request signal using an enable signal received from a processor interface located at the front end.

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