KR102253971B1 - Recessed composite capacitor - Google Patents

Abstract

Some embodiments relate to an integrated circuit (IC) comprising a semiconductor substrate. The shallow trench isolation region extends downward into the front surface of the semiconductor substrate and is filled with a dielectric material. In the shallow trench isolation region, a first capacitor plate and a second capacitor plate are disposed. The first capacitor plate and the second capacitor plate each have first and second sidewall structures that are substantially parallel to each other and separated from each other by a dielectric material in the shallow trench isolation region.

Description

Recessed Composite Capacitor {RECESSED COMPOSITE CAPACITOR}

This application claims the benefit of U.S. Provisional Application No. 62/855,129, filed May 31, 2019, the contents of which are incorporated herein by reference in their entirety.

A trend in the semiconductor manufacturing industry is to integrate different circuit elements, including logic, passive components such as capacitors and resistors, memories, processors, peripherals, etc. on a common semiconductor substrate. Such integration can lower manufacturing costs and simplify the manufacturing procedure compared to an approach in which circuit elements are made on separate integrated circuits (ICs) and then electrically coupled to each other on a printed circuit board. And, it is possible to increase the operation speed of the resulting circuit.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, according to standard practice in the industry, various features are not drawn to scale. In practice, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.
1 illustrates a cross-sectional perspective view of an integrated circuit including a composite capacitor in accordance with some embodiments.
2 and 3 illustrate cross-sectional perspective views of an integrated circuit showing some examples of how a composite capacitor may be coupled to a logic device in accordance with some embodiments.
4-11 illustrate some examples of how the depth, spacing, and/or length of the composite capacitor can be adjusted to set the capacitance of the composite capacitor according to some embodiments.
12 illustrates a cross-sectional view of an integrated circuit including a composite capacitor in accordance with some embodiments.
13 and 14 illustrate top views of some embodiments of an integrated circuit including a device region laterally surrounded by a shallow trench isolation region, wherein a composite capacitor is disposed in the shallow trench isolation region.
15 and 16 illustrate top views of some embodiments of an integrated circuit including a device region laterally surrounded by a first shallow trench isolation region, wherein the composite capacitor is from the side from the first shallow trench isolation region. The second shallow trench isolation region is spaced apart and does not surround the device region.
17-21 illustrate top views of some embodiments of an integrated circuit including a composite capacitor in accordance with some embodiments.
22 and 23 are cross-sectional perspective views of an integrated circuit including a shallow trench isolation region including a composite capacitor and a device region including a fin field effect transistor (FinFET) device, in accordance with some embodiments. Illustrate.
24 through 29 illustrate a series of cross-sectional views collectively depicting a method of forming an integrated circuit including a composite capacitor in the shallow trench isolation region and a transistor in the logic region of a semiconductor substrate.
30 illustrates, in a flowchart format, a method for forming an integrated circuit consistent with some embodiments of FIGS. 24-29.
31-35 illustrate a series of cross-sectional views collectively depicting a method of forming an integrated circuit including a composite capacitor in a shallow trench isolation region and a FinFET in a logic region of a semiconductor substrate.
36 illustrates, in a flowchart format, a method for forming an integrated circuit consistent with some embodiments of FIGS. 31-35.

This disclosure provides many different embodiments, or examples for implementing different features of the disclosure. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include an embodiment in which the first and second features are formed by direct contact, wherein the first and second features are Embodiments may also be included in which additional features may be formed between the first and second features so that they may not be in direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity, and, as such, does not dictate a relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures, “beneath”, “below”, Spatially relative terms such as “lower”, “above”, “upper” and so forth may be used herein. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. Devices may be oriented differently (rotated 90 degrees or in different directions), and spatially relative descriptors as used herein may likewise be interpreted accordingly.

In integrated circuit (IC) reduction techniques for better gate control and device performance, transistors with high k gate dielectrics and metal gates have been widely used. However, alternative gate or gate last processes face a number of challenges, especially in advanced technologies as voltage bias across transistors increases and channel lengths decrease. In advanced technology (eg, minimum feature size of 28 nm or less), the voltage applied for successive generation of technology due to process limitations is decreasing. However, among other things, power management, regulators, battery savers, direct current (DC) motors, automotive parts, panel display drivers (e.g. Super Twisted Nematic (STN), thin film transistors) High voltage applications have been widely used in film transistors (TFTs), and/or organic light emitting diodes (OLED) panel display drivers), color display drivers, power supply components, and telecommunication circuits. Moving to the advanced technology node, polysilicon-insulator-polysilicon (PIP) capacitors become complex to achieve. The present disclosure provides a recessed composite capacitor that is compatible in terms of integration with high voltage devices.

1 shows a cross-sectional view of some embodiments of an integrated circuit (IC) 100 in accordance with some embodiments. The IC 100 includes a semiconductor substrate 102 having a frontside 102f and a backside 102b. The transistor 108 and/or other semiconductor device is arranged in and/or over the logic region 104 of the semiconductor substrate 102; The composite capacitor 110 is arranged in and/or over the capacitor region 106 of the semiconductor substrate 102.

In some cases, capacitor region 106 corresponds to a shallow trench isolation (STI) region filled with dielectric material 112. The capacitor region 106 is substantially vertical and includes a plurality of capacitor plates disposed in the dielectric material 112 in the STI region. For example, the first capacitor plate 114 and the second capacitor plate 116 are disposed in the dielectric material 112 in the shallow trench isolation region. The first capacitor plate 114 and the second capacitor plate 116 are substantially parallel to each other and separated from each other by a dielectric material 112 in the shallow trench isolation region. Additional capacitor plates such as, for example, the third capacitor plate 118 and the fourth capacitor plate 120 may also be arranged substantially parallel to the first and second capacitor plates 114, 116, and some In an embodiment they are separated from each other by a dielectric material 112 in the shallow trench isolation region. Thus, the first, second, third, and/or fourth capacitor plates 114, 116, 118, 120 may be "recessed" into the substrate 102 and contact and/or semiconductor substrates. (102) It may be operably coupled to each other through an interconnect structure including a horizontal metal line and a vertical via above.

In such a configuration, the first, second, third, and/or fourth capacitor plates 114, 116, 118, 120 are to be measured between the first capacitor terminal 122 and the second capacitor terminal 124. When, in order to establish a composite capacitor 110 whose total capacitance (C _c ) is the sum of the capacitances of the capacitive components (e.g., C _c = C ₁ + C ₂ + C ₃ ), electrically in parallel with each other. It can be coupled together to establish the various capacitive components that are arranged (eg, C ₁ , C ₂ , C _{3 ).} In some embodiments, the first, second, third, and/or fourth capacitor plates 114, 116, 118, 120 have substantially parallel sidewall structures. The sidewalls may be actually parallel or may have a small offset from being parallel (may be really vertical or may have a small offset from being vertical), for example, the sidewalls may be due to the etching process being used. It may have a scallop, or may be tapered, as a result, for example, the upper part of the sidewall is slightly closer than the lower part of the sidewall.

Within the composite capacitor 110, the capacitance of each capacitive component (C _n (n = 1, 2, 3, ...)) is defined by the following equation:

Where c _n is the capacitance of the nth capacitive component in farads, ε ₀ is the dielectric constant of the vacuum, ε _r is the dielectric constant of the dielectric material 112 between the plates, and A _n is the dielectric constant between the adjacent capacitor plates. Is the total area of, and S _n is the spacing between neighboring capacitor plates. _{The advantage in the arrangement of Figure 1 is that the layout of the composite capacitor 110 adjusts the spacing S n} between the first, second, third, and fourth capacitor plates 114, 116, 118, 120, respectively. ; In addition, it can be tuned to each adjust _{the area A n} between neighboring capacitor plates. More specifically, the area A _n between the capacitor plates can be adjusted based on the _{depth d n at which} each capacitor plate extends into the substrate and _{the length l n of each capacitor plate.}

Transistor 108 has first and second source/drain regions 126 and 128 having a first conductivity type (e.g., n-type), and a second conductivity type opposite to the first conductivity type (e.g. , p-type), and a gate electrode 130 disposed between the first and second source/drain regions 126 and 128. The gate electrode 130 extends into the front surface of the semiconductor substrate 102 to the depth of the gate electrode, and the gate dielectric layer 132 is the front surface of the semiconductor substrate 102 to separate the gate electrode 130 from the semiconductor substrate 102. In the gate extends to the dielectric depth. The channel region 134 is disposed along the lower surface and outer sidewalls of the gate dielectric layer 132 in the semiconductor substrate 102 and extends between the first and second source/drain regions 126 and 128. . Thus, the gate electrode 130 is also "recessed" in the substrate 102. In some embodiments, the material composition and depth of the gate dielectric layer 132 may correspond to that of the dielectric material 112 in the STI region; The material composition and depth of the first, second, third, and fourth capacitor plates 114, 116, 118, 120 may correspond to those of the gate electrode 130. For example, the gate dielectric layer 132 and dielectric material 112 in the STI region may or may be a high-k dielectric material or silicon dioxide, and may be from a few nanometers to several micrometers into the semiconductor substrate 102. It can be extended to a depth of up to. In addition, in some embodiments, gate electrode 130 and capacitor plates 114, 116, 118, 120 may be doped polysilicon, or may include them, and from a few nanometers to several micrometers into a semiconductor substrate. It can have a depth that reaches the range of. In other embodiments, the gate electrode 130 and the capacitor plates 114, 116, 118, 120 may be or may include other conductive materials such as, for example, tungsten, aluminum, copper, or nickel. . Further, in still other embodiments, the gate dielectric layer 132 and dielectric material 112 of the STI region may be of different materials and/or different depths from each other; And/or the gate electrode 130 and the first, second, third, and fourth capacitor plates 114, 116, 118, 120 may be of different materials and/or different depths.

Each of the first, second, third, and fourth capacitor plates 114, 116, 118, 120 (they are disposed within the dielectric material 112 in the STI region) and the gate electrode 130 are the front surface 102f of the semiconductor substrate. ), this approach provides a composite capacitor 110 that is more compatible with alternative gate processes and/or is better integrated with high voltage devices. Thus, the various composite capacitor embodiments provided herein can be fabricated in an efficient manner, particularly from a viewpoint of integration with a high voltage transistor as in FIG. 1. In addition, since the first, second, third, and fourth capacitor plates 114, 116, 118, 120 are disposed within the dielectric material 112 of the STI region, this approach is in many respects small footprint and good. Device characteristics can also be provided.

As can be seen from Figures 1-3, composite capacitor 110 and transistor 108 may be operatively coupled in several different configurations. For example, as can be seen in FIG. 2, in some embodiments, the source/drain regions 126 of transistor 108 are directly at the first and/or second capacitor terminals (e.g., 122). Can be coupled. This coupling illustrated in FIG. 2 includes one or more metal lines 138, 140 extending horizontally over capacitor region 106 and logic region 104, and one or more contacts or vias (e.g., 142, 144). ) Can be achieved through the interconnect structure 136 including. The first capacitor terminal 122 of the composite capacitor 110 is connected to the first and third capacitor plates 114 and 118 and a first metal line (e.g., 138) and one or more contacts or vias (e.g. Coupled to the first source/drain region 126 via, for example, 142; Meanwhile, the second capacitor terminal 124 of the composite capacitor 110 is formed of the second and fourth capacitors through a second metal line (for example, 140) and one or more contacts or vias (for example, 144) among the metal lines. It is coupled to the plates 116 and 120. In another embodiment, the gate electrode 130 may be directly coupled to the first or second capacitor terminals 122, 124 of the composite capacitor 110, for example, as can be seen in FIG. 3. have. This coupling illustrated in FIG. 3 includes one or more metal lines 146, 148 extending horizontally over capacitor region 106 and logic region 104, and one or more contacts or vias (e.g., 150, 152). ) Can be achieved through the interconnect structure 136 including. In FIG. 3, the first capacitor terminal 122 of the composite capacitor 110 is a first metal line (eg, 146) among metal lines and at least one contact or via (eg, 150). And coupled to the third capacitor plates 114 and 118 and the gate electrode 130; On the other hand, the second capacitor terminal 124 of the composite capacitor 110 is connected to the second and fourth metal lines through a second metal line (for example, 148) and one or more contacts or vias (for example, 152) among the metal lines. It is coupled to the capacitor plates 116 and 120. In other embodiments, composite capacitor 110 and transistor 108 are not directly coupled to each other.

4-11 illustrate how _{the total capacitance C c} of a composite capacitor according to some embodiments can be tuned by adjusting the depth, spacing, and/or length of the capacitor plate for various capacitive elements. Illustrate some examples to describe. It will be appreciated that these are examples only, and that other variations are also contemplated as falling within the scope of the present disclosure.

4 illustrates an embodiment including first and second composite capacitors 110a and 110b disposed in the first and second STI regions 112a and 112b, respectively, in the semiconductor substrate 102. In this example, each of the first and second composite capacitors 110a, 110b includes a first capacitor plate (114a, 114b, respectively) having a first bottom surface (115a, 115b, respectively); Each includes a second capacitor plate (116a, 116b, respectively). The first bottom surfaces 115a and 115b are disposed at first and second depths d1 and d2, respectively, from the front surface 102f of the semiconductor substrate. The first and second depths d1 and d2 are equal to each other in FIG. 4; It is also equal to the depth of the second bottom surface for the second capacitor plates 116a and 116b. The first and second composite capacitors 110a and 110b also include third capacitor plates 118a and 118b, respectively. The third capacitor plates 118a and 118b have a third bottom surface disposed at a third depth below the front surface of the semiconductor substrate, the first depth, the second depth, and the third depth being the same. For example, in some embodiments, d1 and d2 can range from a few nanometers to a few microns. 4 also shows each composite capacitor including the fourth capacitor plates 120a, 120b at the same depth as the first, second and third plates, but other numbers of capacitor plates are also included within the scope of the present disclosure. It is also considered to be. The spacing between neighboring capacitor plates is the same in the example of FIG. 4.

It is recognized that “first”, “second”, “third”, “fourth”, and the like are merely generic identifiers herein and do not imply or suggest any spatial or temporal relationship between the various elements. Will be. In addition, these identifiers may be interchanged with each other in various embodiments. For example, although 114a is referred to as the “first” capacitor plate with respect to FIG. 1, in some embodiments, 114a is also interpreted and/or interpreted as a second capacitor plate, a third capacitor plate, a fourth capacitor plate, etc. Or may be referred to.

5 illustrates another embodiment including first and second composite capacitors 110a and 110b disposed on a semiconductor substrate 102. In contrast to FIG. 4 (here the bottom surfaces of all capacitor plates are at the same depth from the front surface 102f of the substrate), in the example of FIG. 5, the capacitor plate in the first composite capacitor has a first depth d1' at a first depth d1'. It has a bottom surface, and the capacitor plate in the second composite capacitor has a second bottom surface at a second depth d2'. The first and second depths d1' and d2' are different from each other. For example, in some embodiments d2 can range from 20% to 80% of d1. Therefore, when the length of the capacitor plates 114a-120a is the same as that of 114b-120b and the spacing between the capacitor plates is the same as that of 114b-120b, the second composite capacitor 110b in FIG. 5 has a reduced depth (Therefore, it may have a lower capacitance than that of the first composite capacitor 110a due to the reduced area A between neighboring capacitor plates).

6 illustrates still another embodiment including first and second composite capacitors 110a and 110b disposed on a semiconductor substrate 102. In contrast to FIGS. 4 and 5 (here, each of the composite capacitors 110a and 110b includes a capacitor plate whose bottom surface has the same depth within the composite capacitor), the composite capacitor 110a in FIG. 6 , 110b) have capacitor plates having different depths within each composite capacitor. For example, in some embodiments, the shallowest capacitor plate (e.g., 116b) of the capacitor plates ranges from less than 1% of the thickness of the substrate 102 to up to 75% of the thickness of the substrate 102. On the other hand, the deepest capacitor plate (for example, 120b) among the capacitor plates can range from 1% of the thickness of the substrate 102 to 90% of the thickness of the substrate 102, and is less than the shallowest plate. It can have a depth ranging from 10% greater deep to 10 or 20 times deeper than the shallowest plate. This approach can allow finer tuning of the capacitance than other approaches.

7 shows that the first and second composite capacitors 110a and 110b have capacitor plates having the same depth, but the first and second composite capacitors have sidewall structures spaced apart by _{a first interval s 1.} A second, third, and fourth capacitor plates; Still another embodiment is illustrated in which the second composite capacitor includes first, second, third, and fourth capacitor plates having sidewall structures spaced apart by _{a second spacing s 2.} The second interval s2 is larger than the first interval s1. Therefore, in FIG. 7, if the length and depth of the capacitor plates 114a-120a are the same as those of 114b-120b, the second composite capacitor 110b in FIG. 5, due to the increased spacing between the capacitor plates, It may have a lower capacitance than that of the first composite capacitor 110a.

In contrast to FIG. 7 (here, each of the composite capacitors 110a and 110b includes a capacitor plate spaced equally apart from neighboring capacitor plates in the composite capacitor), the composite capacitors 110a and 110b in FIG. 8 ) Has capacitor plates with different spacing within each composite capacitor. For example, in the first composite capacitor, the first and second capacitor plates are separated by a first interval (sa1), and the second and third capacitor plates are separated by a second interval (sa2 <sa1); The third and fourth capacitor plates are separated by a third interval sa3 <sa2. For example, in the second composite capacitor, the first and second capacitor plates are separated by a first interval (sb1) (for example, sa1> sb1> sa2), while the second and third capacitor plates are Separated by 2 intervals (sb2 <sb1); The third and fourth capacitor plates are separated by a third interval sb3 <sb2. This approach of FIG. 8 may allow finer tuning of the capacitance than other approaches, and different spacings are advantageous in that they typically do not utilize any additional photolithography steps than the approach of FIG. 7.

9 illustrates still another embodiment including first and second composite capacitors 110a and 110b disposed on a semiconductor substrate 102. The composite capacitors 110a and 110b in FIG. 9 have capacitor plates having different depths and different spacings for neighboring capacitor plates in each composite capacitor. 9 also illustrates that composite capacitors can have different numbers of capacitor plates to provide finer tuning of capacitance than other approaches. For example, the first composite capacitor 110a includes three capacitor plates 114a, 116a and 118a; Meanwhile, the second composite capacitor 110b includes six capacitor plates 114b, 116b, 118b, 120b, 121 and 123b.

As shown in FIG. 10, the first and second composite capacitors 110a and 110b may also have different lengths. For example, in the first composite capacitor 110a, each of the first, second, third, and fourth capacitor plates has a first length l1, while in the second composite capacitor 110b, Each of the first, second, third, and fourth capacitor plates 110b has a second length l2. As shown in FIG. 11, the first and second composite capacitors 110a and 110b may also have different lengths, different spacings, and different depths from each other.

12 shows another embodiment of an integrated circuit comprising a composite capacitor 110 and a transistor 108. The composite capacitor 110 is again illustrated as having first, second, third, and fourth capacitor plates 114, 116, 118, 120 (they are disposed within the dielectric material 112 of the STI region); Transistor 108 is again illustrated as having a gate electrode 130 and a gate dielectric layer 132 extending downwardly into the front surface 102f of the semiconductor substrate. An etch stop layer 160, such as a silicon nitride layer, is disposed over the front surface 102f of the substrate. For example, a silicide layer 162, such as nickel silicide, extends at least partially through the etch stop layer 160 so that the first, second, third, and fourth capacitor plates 114, 116, 118, 120 Make ohmic contact with the upper surface of the gate electrode 130, make ohmic contact with the upper surface of the gate electrode 130, and make ohmic contact with the upper surfaces of the first and second source/drain regions 126 and 128. For example, contacts 164 and/or vias, which may be made of tungsten or other metal, couple silicide to a line of metal layer 166 (e.g., metal 1 layer) of the interconnect structure on the substrate. do.

13 and 14 show a device region (which may include the transistor region 104 and/or other active and/or passive devices of FIG. 1) laterally surrounded by a shallow trench isolation region. 1 illustrates a top view of some embodiments of an integrated circuit, such as the integrated circuit.

In FIG. 13, the device region is a gate dielectric separating the gate electrode 130 from the first and second source/drain regions 126 and 128, the gate electrode 130, and the underlying semiconductor substrate 102. Corresponds to the transistor comprising layer 132. The shallow trench isolation region laterally surrounds the device region and is filled with dielectric material 112. The shallow trench isolation region includes a plurality of capacitor plates that collectively establish a composite capacitor in the shallow trench isolation region. More specifically, in Fig. 13, the capacitor plates are concentric rings, each of which continuously and laterally surrounds the device area. Accordingly, the composite capacitor is again illustrated as having first, second, third, and fourth capacitor plates 114, 116, 118, 120, wherein the first and third capacitor plates are the first capacitor terminals ( 122), and the second and fourth capacitor plates are coupled to the second capacitor terminal to establish a composite capacitor.

In FIG. 14, the plurality of capacitor plates includes: a first set 1402 of capacitor plates for a first side of the device area, a second set 1404 of capacitor plates for a second side of the device area, and a second set of capacitor plates 1404 for the second side of the device area. A third set 1406 of capacitor plates for the third side, and a fourth set 1408 of capacitor plates for the fourth side of the device area. The first and third sets of capacitor plates 1402 and 1406 extend parallel to each other in a first direction, and the second and fourth sets of capacitor plates 1404 and 1408 are in a second direction perpendicular to the first direction. Extend parallel to each other at As shown, one or more capacitor plates in each of the first, second, third, and fourth sets may be coupled to the first capacitor terminal 122, and the first, second, third, And one or more other capacitor plates in each of the fourth set may be coupled to the second capacitor terminal 124, thereby establishing a composite capacitor.

15 and 16 illustrate top views of some embodiments of an integrated circuit including a device region laterally surrounded by a first shallow trench isolation region 113 filled with a dielectric material. The integrated circuit also includes a second shallow trench isolation region 115 that is separated from the first shallow trench isolation region 113. The second shallow trench isolation region 115 is also filled with a dielectric material, but does not completely surround the device region. In Fig. 15, the capacitor plate is a concentric ring disposed within the second shallow trench isolation region to establish a composite capacitor. In Fig. 16, the capacitor plates are linear segments arranged in parallel in the first direction, and are coupled to the first capacitor terminal 122 and the second capacitor terminal 124 to establish a composite capacitor.

In FIG. 17, the composite capacitor includes a first capacitor plate 1702, a second capacitor plate 1704, a third capacitor plate 1706, and a fourth capacitor plate 1708 disposed in the shallow trench isolation region. The second capacitor plate 1704 is arranged between the first capacitor plate 1702 and the third capacitor plate 1706; In addition, the third capacitor plate 1706 is arranged between the second capacitor plate 1704 and the fourth capacitor plate 1708. The first capacitor plate 1702, the second capacitor plate 1704, the third capacitor plate 1706, and the fourth capacitor plate 1708 extend parallel to each other in the first direction and have the same length in the first direction. , Each has end portions that are aligned with each other in a second direction perpendicular to the first direction. The fifth, sixth and seventh capacitor plates 1710, 1712, and 1714 extend parallel to each other in the second direction, have the same length in the second direction, and have respective ends aligned with each other in the first direction. The first metal line 1716 couples the first, second, third, and fourth capacitor plates to each other, and the second metal line 1718 couples the first, sixth, and seventh capacitor plates to each other. Ring.

Fig. 18 illustrates another example in which the capacitor plates are arranged parallel to each other, but with respective ends that are offset or "staggered" from each other in a second direction perpendicular to the first direction.

19 illustrates still another example according to some embodiments. In FIG. 19, the first capacitor plate includes a first trunk 1902 extending in a first direction, and a first plurality of fingers extending outward from the first trunk 1902 in a second direction perpendicular to the first direction ( 1904, 1906, 1908, 1910). The second capacitor plate includes a second trunk 1912 extending in a first direction but spaced apart from the first trunk 1902, and a second plurality of fingers extending outward from the second trunk 12912 in a second direction. (1914, 1916, 1918, 1920). The first plurality of fingers are inter-digitated with the second plurality of fingers and are separated from each other by a dielectric material 112 in the shallow trench isolation region. This embodiment is advantageous because it provides a good match for the capacitor and provides a relatively small footprint on the chip.

20 and 21 still illustrate another example according to some embodiments. In these figures, the first capacitor plate and the second capacitor plate are concentric rings of conductive material separated from each other by a dielectric material 112 in the shallow trench isolation region.

22 and 23 illustrate some additional embodiments in which the transistor is implemented as a FinFET 2200 on the same substrate as the composite capacitor 2202. 23 illustrates a structure in which an inter-layer dielectric (ILD) layer 2300, contacts 2302, and metal layer 2304 are in place, while these layers better shape the underlying structure. Removed from Figure 22 to illustrate. The FinFET 2200 includes a plurality of fins 2204 made of a semiconductor material extending upward from the base substrate 2206 and extending through a shallow trench isolation layer 2208 made of a dielectric material such as a high-k dielectric or silicon dioxide. Includes. The gate dielectric layer 2210 extends over the upper surface and upper sidewall regions of the fins 2204, and the conductive gate electrode 2212 extends over the gate dielectric layer 2210. The conductive gate electrode 2212 may be made of, for example, polysilicon or metal. Composite capacitor 2202 includes first and second capacitor plates 2214 and 2216 disposed in shallow trench isolation layer 2208. In some examples, gate dielectric layer 2210 separates first and second capacitor plates 2214 and 2216 from shallow trench isolation layer 2208.

24-29 illustrate some embodiments of forming an integrated circuit including a high voltage transistor and a composite capacitor. Although the disclosed method (e.g., a method described by a flowchart, cross-sectional view, and/or other method disclosed herein) may be illustrated and described herein as a series of actions or events, illustrated It will be appreciated that the order should not be construed in a limiting sense. For example, some actions may occur in a different order and/or concurrently with other actions or events separate from those illustrated and/or described herein. In addition, not all illustrated actions may be required to implement one or more aspects or embodiments of the description herein, and one or more of the actions depicted herein are performed in one or more separate actions and/or steps. It could be.

In Fig. 24, a semiconductor substrate 102 is provided. The substrate 102 includes a logic region 104 and a capacitor region 106. In some embodiments, the semiconductor substrate 102 may be a single crystal silicon substrate or a semiconductor-on-insulator (SOI) substrate (eg, a silicon on insulator substrate). The semiconductor substrate 102 may also be, for example, a binary semiconductor substrate (eg, GaAs), a tertiary semiconductor substrate (eg, AlGaAs), or a higher order semiconductor substrate. The substrate 102 is a doped region formed on the substrate, an epitaxial layer formed on the substrate, one or more insulating layers formed in or on the substrate, and/or conductive formed in or on the substrate. May include layers. In many cases, the semiconductor substrate 102 appears as a semiconductor wafer during the manufacturing process, for example; 1 inch (25 mm); 2 inches (51 mm); 3 inches (76 mm); 4 inches (100 mm); 5 inches (130 mm) or 125 mm (4.9 inches); 150 mm (5.9 inches, commonly referred to as "6 inches"); 200 mm (7.9 inches, commonly referred to as "8 inches"); 300 mm (11.8 inches, commonly referred to as "12 inches"); It may have a diameter of 450 mm (17.7 inches, commonly referred to as “18 inches”). After processing is complete, e.g., after transistors, capacitor elements, and logic elements are formed, such wafers can, optionally, be stacked with other wafers or dies, and then individual dies corresponding to individual ICs. Is singulated. A first mask (not shown) is patterned over the front surface 102f of the semiconductor substrate 102, and a first recess is formed. Then, a dielectric material 112, such as a high k dielectric material or silicon dioxide, is used to fill the first recess to establish a trench isolation region. Then, the first mask is removed, and a second mask is formed. With the second mask in place, ions of the first conductivity type are implanted into the substrate to establish the well region 129. The first mask and/or the second mask may be, for example, a hardmask layer such as nitride, and/or may be a photoresist layer.

In Fig. 25, the second mask is removed, and the third mask is patterned over the entire surface of the semiconductor substrate. With the third mask in place, etching is performed to form a gate electrode recess 2500 in the well region and a set of capacitor plate recesses 2502 in the shallow trench isolation region. The third mask may be, for example, a hardmask layer such as nitride, and/or may be a photoresist layer.

In FIG. 26, a dielectric material 2600, such as a high k dielectric material or silicon dioxide, is then formed on the surface of the set of recesses. Dielectric material 2600 may have a thickness of, for example, 200 Angstroms to 1000 Angstroms, and may establish a gate dielectric for the transistor.

In Figure 27, polysilicon 2700 is deposited over the dielectric material. For example, polysilicon can be formed by chemical vapor deposition (CVD), plasma vapor deposition (PVD), or other deposition techniques.

In Fig. 28, a chemical mechanical planarization (CMP) operation is performed to planarize the polysilicon, dielectric material, well region, and the upper surface of the semiconductor substrate. Another ion implantation or epitaxial growth is performed to form the first and second source/drain regions 126 and 128; An interlayer dielectric (ILD) layer 2800, typically made of silicon dioxide or low-k dielectric material, is then formed over the structure. Then, another CMP operation may be performed to planarize the top surface of the ILD layer 2800. Accordingly, the first capacitor plate 114, the second capacitor plate 116, the third capacitor plate 118, the fourth capacitor plate 120; A gate electrode 130; A gate dielectric layer 132 is formed.

In FIG. 29, another ILD layer 2900 is formed and formed such that the contacts 142 and metal lines 140 extend through the ILD layer and operably couple the capacitor plates to each other and/or to the transistor.

30 illustrates a flowchart 3000 in accordance with some embodiments that may be consistent with some examples of FIGS. 24-29. In block 3002, an STI region made of a dielectric material is formed in a capacitor region of the semiconductor substrate. Some embodiments of 3002 may correspond to some embodiments of FIG. 24, for example. In block 3004, etching is performed to form a recess in the dielectric material of the STI region and to simultaneously form a recess in the logic region of the semiconductor substrate. Some embodiments of block 3004 may correspond to some embodiments of FIG. 25, for example. In block 3006, a gate dielectric is formed in a recess in a logic region of the semiconductor substrate. In some embodiments, the gate dielectric is formed by CVD or PVD and is also formed over the recess in the STI region, while in other embodiments, the gate dielectric is formed by thermal oxidation, and thus the exposed area of the semiconductor substrate. It is formed only on the top and thus not on the dielectric material of the STI region, but on the recess in the logic region. Some embodiments of block 3006 may correspond to some embodiments of FIG. 26, for example. In block 3008, a conductive layer, such as a polysilicon layer, is formed over the gate dielectric. Some embodiments of 3008 may correspond to some embodiments of FIG. 27, for example. In block 3010, a CMP operation is performed on the conductive layer to remove the top portion of the conductive layer, whereby a first portion of the conductive layer in the logic region corresponding to the gate electrode, and in the STI region corresponding to the capacitor plate. It leaves another part of the conductive layer. In block 3012, an ILD layer is formed over the gate electrode and capacitor plate, and CMP is performed on the ILD. Some embodiments of blocks 3010-3012 may correspond to some embodiments of FIG. 28, for example. In block 3014, a contact is formed through the ILD layer, and a layer of metal is formed over the contact. Some embodiments of block 3014 may correspond to some embodiments of FIG. 29, for example. In block 3016, additional ILD layers, vias, and additional metal layers are formed to establish a back-end-of-line (BEOL) interconnect structure operatively coupling the capacitor plate and gate electrode.

31-35 illustrate another manufacturing flow as a series of perspective views in accordance with some embodiments.

In Fig. 31, a semiconductor substrate 2206 is provided.

In FIG. 32, a plurality of fins 2204 are formed over a substrate, in or through a dielectric layer 3202, such as a high k dielectric layer. In some embodiments, fins 2204 may be formed by etching the recesses into the upper surface of the substrate, and then forming dielectric material 3202 in the recesses between the fins. In another embodiment, the dielectric material 3202 may be formed as a continuous sheet over the semiconductor substrate 2206, and then a recess may be formed in the dielectric material to expose the upper surface area of the substrate, and the fins It can be formed by epitaxially growing a semiconductor material within the recess.

In FIG. 33, after fins 2204 are formed, a first mask (not shown) is formed over the substrate and fins, and etching is performed to form recesses 3300 in the dielectric layer.

In FIG. 34, a gate dielectric layer 2210, such as a high k gate dielectric layer, is formed over the bottom surface and sidewalls of the recess and over the dielectric layer 3202. Then, a conductive layer, such as a doped polysilicon layer, is formed over the gate dielectric layer 2210. Then, a second mask (not shown) is formed over the conductive layer over the fin, and in place to remove the conductive layer from the STI region, optionally, to remove a portion of the conductive layer from the STI region. Etching is performed using the second mask, thereby establishing the gate electrode 2212 and the first and second capacitor plates 2214 and 2216 illustrated in FIG. 34.

In FIG. 35, the first interlayer dielectric (ILD) layer 2300a is formed on the structure, and the CMP operation is performed until the first ILD layer 2300a has an upper surface that is flush with the upper surface of the gate electrode 2212. Performed. Then, a second ILD layer 2300b is formed on the first ILD layer 2300a and the gate electrode 2212. Then, a contact opening is formed through the first and second ILD layers, and a metal contact 2302 made of, for example, tungsten or aluminum is formed, for example, in the contact opening. Then, a first layer of metal line 2304 (eg, metal 1 line) is formed over the contact.

36 illustrates a flowchart 3600 in accordance with some embodiments that may be consistent with some examples of FIGS. 31-35. In block 3602, fins extending through the dielectric layer are formed over the semiconductor substrate. Some embodiments of block 3602 may correspond to some embodiments of FIG. 32, for example. At block 3604, an etching is performed to form a recess in a portion of the dielectric layer. Some embodiments of block 3604 may correspond to some embodiments of FIG. 33, for example. At block 3606, a gate dielectric is formed over the structure and a sacrificial and/or conductive layer is formed over the structure. In some embodiments, block 3606 may correspond to some embodiments of FIG. 34, for example. In block 3608, an ILD layer is formed over the gate electrode and capacitor plate, and CMP is performed on the ILD. Some embodiments of block 3608 may correspond to some embodiments of FIG. 34, for example. In optional block 3610, the gate electrode and/or, optionally, the conductive and/or sacrificial material of the capacitor plate is removed and replaced with a metal. At block 3612, a contact is formed through the ILD layer, and a layer of metal 1 is formed over the contact. Some embodiments of block 3612 may correspond to some embodiments of FIG. 35, for example. In block 3614, additional ILD layers, vias, and additional metal layers are formed to establish a line backend (BEOL) interconnect structure operatively coupling the capacitor plate and gate electrode.

Identifiers such as “first” and “second” do not imply any type of order, arrangement, or temporal relationship with respect to other elements; Rather, it will be appreciated that “first” and “second” and other similar identifiers are merely generic identifiers and these elements may be interchanged in other implementations. For example, the “first dielectric layer” described in connection with the first drawing may not necessarily correspond to the “first dielectric layer” described in connection with other drawings or non-illustrated embodiments.

In some embodiments, an integrated circuit (IC) includes a semiconductor substrate having a front surface and a rear surface; A shallow trench isolation region extending into the front surface of the semiconductor substrate and filled with a dielectric material; A first capacitor plate and a second capacitor plate extending from the front surface of the semiconductor substrate into the shallow trench isolation region; The first capacitor plate and the second capacitor plate each have first and second sidewall structures that are substantially parallel to each other and separated from each other by a dielectric material in the shallow trench isolation region. In some embodiments, the first and second capacitor plates have first and second bottom surfaces, the first and second bottom surfaces being disposed at first and second depths, respectively, from the front surface of the semiconductor substrate; The first depth and the second depth are the same as each other. In some embodiments, the IC includes a third capacitor plate disposed in the shallow trench isolation region, the third capacitor plate having a third bottom surface disposed at a third depth below the front surface of the semiconductor substrate, the first depth, the first The second depth and the third depth are the same as each other, or the third depth is different from the first depth and the second depth. In some embodiments, the first and second capacitor plates have first and second bottom surfaces, and the first and second bottom surfaces are disposed at first and second depths, respectively, from the front surface of the semiconductor substrate, The first and second depths are different from each other. In some embodiments, the IC includes a third capacitor plate disposed in the shallow trench isolation region, the third capacitor plate having a third bottom surface disposed at a third depth below the front surface of the semiconductor substrate, the first depth, the first Each of the 2 depth and the 3rd depth is different from each other. In some embodiments, the IC includes a third capacitor plate disposed in the shallow trench isolation region, wherein the first and second capacitor plates are spaced apart from each other by a first distance, and the second and third capacitor plates include a first They are spaced apart by a second distance equal to the distance. In some embodiments, the IC includes a third capacitor plate disposed in the shallow trench isolation region, wherein the first and second capacitor plates are spaced apart from each other by a first distance, and the second and third capacitor plates include a first It is spaced apart by a second distance different from the distance. In some embodiments, the IC includes a third capacitor plate disposed in the shallow trench isolation region; And a metal line extending horizontally over at least two of the first, second and third capacitor plates and directly coupling at least two of the first, second and third capacitor plates to each other. In some embodiments, the IC comprises: a third capacitor plate disposed in the shallow trench isolation region, the second capacitor plate being arranged between the first capacitor plate and the third capacitor plate; And a fourth capacitor plate disposed in the shallow trench isolation region, the third capacitor plate being arranged between the second capacitor plate and the fourth capacitor plate; The first capacitor plate, the second capacitor plate, the third capacitor plate, and the fourth capacitor plate extend parallel to each other in the first direction, have the same length in the first direction, and have the same length in the first direction. Each end has an aligned end. In some embodiments, the IC comprises: a third capacitor plate disposed in the shallow trench isolation region, the second capacitor plate being arranged between the first capacitor plate and the third capacitor plate; And a fourth capacitor plate disposed in the shallow trench isolation region, the third capacitor plate being arranged between the second capacitor plate and the fourth capacitor plate; The first capacitor plate, the second capacitor plate, the third capacitor plate, and the fourth capacitor plate extend parallel to each other in the first direction, have the same length in the first direction, and have the same length in the first direction. Each end is offset from. In some embodiments, the first capacitor plate includes a first trunk extending in a first direction, and a first plurality of fingers extending outwardly from the first trunk in a second direction perpendicular to the first direction. In some embodiments, the second capacitor plate includes a second trunk extending in a first direction but spaced apart from the first trunk, and a second plurality of fingers extending outwardly from the second trunk in a second direction, The first plurality of fingers engage with each other and are separated from each other by a dielectric material in the shallow trench isolation region. In some embodiments, the first capacitor plate and the second capacitor plate are concentric rings of conductive material separated from each other by a dielectric material in the shallow trench isolation region. In some embodiments, the IC includes a transistor laterally surrounded by a shallow trench isolation region, the transistor comprising: first and second source/drain regions disposed over the front surface of the semiconductor substrate; A gate electrode extending into the front surface of the semiconductor substrate to a first non-zero depth and disposed between the first and second source/drain regions; And a gate dielectric layer extending into the front surface of the semiconductor substrate to separate the gate electrode from the semiconductor substrate, wherein the channel region in the semiconductor substrate along the lower surface and outer sidewalls of the gate dielectric layer extends between the first and second source/drain regions. Includes. In some embodiments, the first non-zero depth is equal to the first depth corresponding to the bottom surface of the first capacitor plate. In some embodiments, the IC includes a transistor on the side of the shallow trench isolation region, the transistor comprising: first and second source/drain regions disposed on the front surface of the semiconductor substrate; A gate electrode extending to a first non-zero depth into the entire surface of the semiconductor substrate and disposed between the first and second source/drain regions; And a gate dielectric layer extending into the front surface of the semiconductor substrate to separate the gate electrode from the semiconductor substrate, the channel region in the semiconductor substrate along the lower surface and outer sidewalls of the gate dielectric layer extending between the first and second source/drain regions Including; The shallow trench isolation region is separate from the outer perimeter of the first and second source/drain regions, spaced apart from them, and disposed on one side of the gate electrode without laterally surrounding the gate electrode. Have a perimeter

In some embodiments, an integrated circuit (IC) includes: a semiconductor substrate having a front side and a back side; First and second source/drain regions extending into the front surface of the semiconductor substrate, the first and second source/drain regions separated from each other by a channel region in the semiconductor substrate; A gate electrode extending into the entire surface of the semiconductor substrate and disposed over the channel region; A gate dielectric layer extending into the front surface of the semiconductor substrate to separate the bottom surface and outer sidewalls of the gate electrode from the channel region; A shallow trench isolation region extending into the front surface of the semiconductor substrate and arranged along an outer edge of the first source/drain region or the second source/drain region-the shallow trench isolation region is filled with a dielectric material; And a composite capacitor comprising a first capacitor terminal and a second capacitor terminal-the total capacitance of the composite capacitor is defined between the first capacitor terminal and the second capacitor terminal, wherein the composite capacitor extends into the shallow trench isolation region and the shallow trench isolation region A plurality of substantially vertical capacitor plates separated from each other by a dielectric material of, wherein a first capacitor plate of the plurality of substantially vertical capacitor plates corresponds to a first capacitor terminal of the composite capacitor and a plurality of substantially vertical capacitor plates Arranged between the second capacitor plate and the third capacitor plate of the capacitor plate, the second and third capacitor plates being on opposite sides of the first capacitor plate and corresponding to the second capacitor terminal of the composite capacitor.

In some embodiments, the method includes: receiving a semiconductor substrate including a logic region and a capacitor region; Performing a first etch to form a shallow trench isolation recess in the capacitor region; Forming a dielectric material in the shallow trench isolation recess to form a shallow trench isolation region; Performing a second etching to form a gate electrode recess in the logic region and a plurality of capacitor plate recesses in the shallow trench isolation region; Forming a high k dielectric material in the gate electrode recess and in the plurality of capacitor plate recesses; And simultaneously forming a conductive layer in the gate electrode recess and in the plurality of capacitor plate recesses to establish a gate electrode in the logic region and a plurality of capacitor plates in the capacitor region. In some embodiments, the method includes: performing a chemical mechanical planarization (CMP) process to remove the top portion of the conductive layer, thereby dividing the gate electrode and the plurality of capacitor plates to separate the structures from each other. In some embodiments, the method includes: forming a dielectric structure over the planarized upper surface of the gate electrode and over the planarized upper surface of the plurality of capacitor plates; And a metal interconnect structure in or on the dielectric structure.- The metal interconnect structure establishes a first capacitor terminal by coupling a first group of a plurality of capacitor plates together, and a second group of a plurality of capacitor plates is coupled together to obtain a second. 2 establishes the capacitor terminal-to form.

1) An integrated circuit (IC) according to an embodiment of the present disclosure includes: a semiconductor substrate having a frontside and a backside; A shallow trench isolation region extending into the front surface of the semiconductor substrate and filled with a dielectric material; And a first capacitor plate and a second capacitor plate extending from the front surface of the semiconductor substrate into the shallow trench isolation region.- The first capacitor plate and the second capacitor plate are substantially parallel to each other and are formed in the shallow trench isolation region. And each having first and second sidewall structures separated from each other by the dielectric material.

2) In the integrated circuit (IC) according to the embodiment of the present disclosure, the first and second capacitor plates have first and second bottom surfaces, and the first and second bottom surfaces are the From the front surface of the semiconductor substrate, they are disposed at first and second depths, respectively, and the first and second depths are the same.

3) An integrated circuit (IC) according to an embodiment of the present disclosure further includes a third capacitor plate disposed in the shallow trench isolation region, wherein the third capacitor plate is at a third depth below the front surface of the semiconductor substrate. It has a third bottom surface disposed, and the first depth, the second depth, and the third depth are equal to each other, or the third depth is different from the first depth and the second depth.

4) In the integrated circuit (IC) according to the embodiment of the present disclosure, the first and second capacitor plates have first and second bottom surfaces, and the first and second bottom surfaces are the From the front side, are disposed at first and second depths, respectively, wherein the first and second depths are different from each other.

5) An integrated circuit (IC) according to an embodiment of the present disclosure further includes a third capacitor plate disposed in the shallow trench isolation region, wherein the third capacitor plate is at a third depth below the front surface of the semiconductor substrate. It has a third bottom surface disposed, and each of the first depth, the second depth, and the third depth is different from each other.

6) An integrated circuit (IC) according to an embodiment of the present disclosure further includes a third capacitor plate disposed in the shallow trench isolation region, wherein the first and second capacitor plates are spaced apart from each other by a first distance, , The second and third capacitor plates are spaced apart by a second distance equal to the first distance.

7) An integrated circuit (IC) according to an embodiment of the present disclosure further includes a third capacitor plate disposed in the shallow trench isolation region, wherein the first and second capacitor plates are spaced apart from each other by a first distance, , The second and third capacitor plates are spaced apart by a second distance different from the first distance.

8) An integrated circuit (IC) according to an embodiment of the present disclosure includes: a third capacitor plate disposed in the shallow trench isolation region; And a metal line extending horizontally over at least two of the first, second and third capacitor plates and directly coupling at least two of the first, second and third capacitor plates to each other.

9) In an integrated circuit (IC) according to an embodiment of the present disclosure, a third capacitor plate disposed in the shallow trench isolation region-The second capacitor plate is arranged between the first capacitor plate and the third capacitor plate. -; And a fourth capacitor plate disposed in the shallow trench isolation region, wherein the third capacitor plate is arranged between the second capacitor plate and the fourth capacitor plate; The first capacitor plate, the second capacitor plate, the third capacitor plate, and the fourth capacitor plate extend parallel to each other in a first direction and have the same length in the first direction, and are perpendicular to the first direction. It has respective ends that are aligned with each other in the phosphorus second direction.

10) An integrated circuit (IC) according to an embodiment of the present disclosure includes a third capacitor plate disposed in the shallow trench isolation region-The second capacitor plate is arranged between the first capacitor plate and the third capacitor plate. -; And a fourth capacitor plate disposed in the shallow trench isolation region, wherein the third capacitor plate is arranged between the second capacitor plate and the fourth capacitor plate; The first capacitor plate, the second capacitor plate, the third capacitor plate, and the fourth capacitor plate extend parallel to each other in a first direction, have the same length in the first direction, and are perpendicular to the first direction. With respective ends that are offset from each other in a second direction.

11) In the integrated circuit (IC) according to the embodiment of the present disclosure, the first capacitor plate is a first trunk extending in a first direction, and from the first trunk in a second direction perpendicular to the first direction. It includes a first plurality of fingers extending outward.

12) In the integrated circuit (IC) according to the embodiment of the present disclosure, the second capacitor plate extends in the first direction, but is spaced apart from the first trunk, and the second trunk in the second direction. A second plurality of fingers extending outwardly from a second trunk, wherein the first plurality of fingers are inter-digitated with the second plurality of fingers and by the dielectric material of the shallow trench isolation region. Separate from each other

13) In the integrated circuit (IC) according to the embodiment of the present disclosure, the first capacitor plate and the second capacitor plate are concentric rings of conductive material separated from each other by the dielectric material in the shallow trench isolation region ( concentric ring).

14) An integrated circuit (IC) according to an embodiment of the present disclosure further includes a transistor laterally surrounded by the shallow trench isolation region, wherein the transistor includes first and second transistors disposed on the front surface of the semiconductor substrate. 2 source/drain regions; A gate electrode extending into the front surface of the semiconductor substrate to a first non-zero depth and disposed between the first and second source/drain regions; And a gate dielectric layer extending into the front surface of the semiconductor substrate to separate the gate electrode from the semiconductor substrate.-A channel region in the semiconductor substrate along an outer sidewall and a lower surface of the gate dielectric layer is the first And extending between the second source/drain regions.

15) In the integrated circuit (IC) according to the embodiment of the present disclosure, the first non-zero depth is equal to a first depth corresponding to the bottom surface of the first capacitor plate.

16) An integrated circuit (IC) according to an embodiment of the present disclosure further includes a transistor on a side of the shallow trench isolation region, wherein the transistor includes first and second source/ Drain region; A gate electrode extending into the front surface of the semiconductor substrate to a first non-zero depth and disposed between the first and second source/drain regions; And a gate dielectric layer extending into the front surface of the semiconductor substrate to separate the gate electrode from the semiconductor substrate. The channel regions in the semiconductor substrate along the lower surface and outer sidewalls of the gate dielectric layer are the first and second sources. / Extends between the drain regions-including; The shallow trench isolation region is separate from and spaced apart from the outer perimeter of the first and second source/drain regions, and one side of the gate electrode without laterally surrounding the gate electrode. ) Is provided with an outer periphery disposed on.

17) An integrated circuit (IC) according to another embodiment of the present disclosure includes: a semiconductor substrate having a front surface and a rear surface; First and second source/drain regions extending into the front surface of the semiconductor substrate, wherein the first and second source/drain regions are separated from each other by a channel region in the semiconductor substrate; A gate electrode extending into the front surface of the semiconductor substrate and disposed over the channel region; A gate dielectric layer extending into the front surface of the semiconductor substrate to separate an outer sidewall and a bottom surface of the gate electrode from the channel region; A shallow trench isolation region extending into the front surface of the semiconductor substrate and arranged along an outer edge of the first source/drain region or the second source/drain region, the shallow trench isolation region filled with a dielectric material; And a composite capacitor including a first capacitor terminal and a second capacitor terminal.- The total capacitance of the composite capacitor is defined between the first capacitor terminal and the second capacitor terminal, and the composite capacitor extends into the shallow trench isolation region. And a plurality of substantially vertical capacitor plates separated from each other by the dielectric material in the shallow trench isolation region, wherein a first capacitor plate of the plurality of substantially vertical capacitor plates comprises the first capacitor of the composite capacitor A terminal corresponding to and arranged between a second capacitor plate and a third capacitor plate of the plurality of substantially vertical capacitor plates, the second and third capacitor plates being on opposite sides of the first capacitor plate And-corresponding to the second capacitor terminal of the composite capacitor.

18) A method according to another embodiment of the present disclosure includes: receiving a semiconductor substrate including a logic region and a capacitor region; Performing a first etching to form a shallow trench isolation recess in the capacitor region; Forming a shallow trench isolation region by forming a dielectric material in the shallow trench isolation recess; Performing a second etching to form a gate electrode recess in the logic region and a plurality of capacitor plate recesses in the shallow trench isolation region; Forming a high-k dielectric material in the gate electrode recess and in the plurality of capacitor plate recesses; And simultaneously forming a conductive layer in the gate electrode recess and in the plurality of capacitor plate recesses to establish a gate electrode in the logic region and a plurality of capacitor plates in the capacitor region.

19) A method according to another embodiment of the present disclosure is to perform a chemical mechanical planarization (CMP) process to remove the upper portion of the conductive layer, whereby the gate electrode and the gate electrode and And dividing the plurality of capacitor plates.

20) A method according to another embodiment of the present disclosure includes forming a dielectric structure over the planarized upper surface of the gate electrode and over the planarized upper surface of the plurality of capacitor plates; And a metal interconnect structure in or on the dielectric structure, wherein the metal interconnect structure couples the first group of the plurality of capacitor plates together to establish a first capacitor terminal, and the plurality of capacitor plates. Coupling the second group of s together to form a second capacitor terminal.

The foregoing outlines features of various embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to serve the same purpose and/or to achieve the same advantages of the embodiments introduced herein. You have to be aware. In addition, those skilled in the art also know that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. That, you have to realize.

Claims (10)

As an integrated circuit (IC),
A semiconductor substrate having a front side and a backside;
A shallow trench isolation region extending into the front surface of the semiconductor substrate and filled with a dielectric material; And
A first capacitor plate and a second capacitor plate extending from the front surface of the semiconductor substrate into the shallow trench isolation region-The first capacitor plate and the second capacitor plate are parallel to each other and the dielectric material of the shallow trench isolation region Each of the first and second sidewall structures that are electrically separated from each other by-
Including, an integrated circuit (IC). The method of claim 1,
A third capacitor plate disposed in the shallow trench isolation region; And
A metal line extending horizontally over at least two of the first, second and third capacitor plates and directly coupling at least two of the first, second and third capacitor plates to each other
Further comprising an integrated circuit (IC). The method of claim 1,
A third capacitor plate disposed in the shallow trench isolation region, the second capacitor plate being arranged between the first capacitor plate and the third capacitor plate; And
A fourth capacitor plate disposed in the shallow trench isolation region-The third capacitor plate is arranged between the second capacitor plate and the fourth capacitor plate-
But further includes;
The first capacitor plate, the second capacitor plate, the third capacitor plate, and the fourth capacitor plate extend parallel to each other in a first direction and have the same length in the first direction, and are perpendicular to the first direction. An integrated circuit (IC) having respective ends that are aligned with each other in a second direction. The method of claim 1,
A third capacitor plate disposed in the shallow trench isolation region, the second capacitor plate being arranged between the first capacitor plate and the third capacitor plate; And
A fourth capacitor plate disposed in the shallow trench isolation region-The third capacitor plate is arranged between the second capacitor plate and the fourth capacitor plate-
But further includes;
The first capacitor plate, the second capacitor plate, the third capacitor plate, and the fourth capacitor plate extend parallel to each other in a first direction, have the same length in the first direction, and are perpendicular to the first direction. An integrated circuit (IC) having respective ends offset from each other in a second direction. The method of claim 1,
The first capacitor plate includes a first trunk extending in a first direction, and a first plurality of fingers extending outwardly from the first trunk in a second direction perpendicular to the first direction. (IC). The method of claim 1,
Wherein the first capacitor plate and the second capacitor plate are concentric rings of conductive material separated from each other by the dielectric material in the shallow trench isolation region. The method of claim 1,
Further comprising a transistor laterally surrounded by the shallow trench isolation region, wherein the transistor,
First and second source/drain regions disposed on the front surface of the semiconductor substrate;
A gate electrode extending into the front surface of the semiconductor substrate to a first non-zero depth and disposed between the first and second source/drain regions; And
A gate dielectric layer extending into the front surface of the semiconductor substrate to separate the gate electrode from the semiconductor substrate-a channel region in the semiconductor substrate along an outer sidewall and a lower surface of the gate dielectric layer comprises the first and Extends between the second source/drain regions-
Including, an integrated circuit (IC). The method of claim 1,
Further comprising a transistor on the side of the shallow trench isolation region, the transistor,
First and second source/drain regions disposed on the front surface of the semiconductor substrate;
A gate electrode extending into the front surface of the semiconductor substrate to a first non-zero depth and disposed between the first and second source/drain regions; And
A gate dielectric layer extending into the front surface of the semiconductor substrate to separate the gate electrode from the semiconductor substrate-a channel region in the semiconductor substrate along an outer sidewall and a lower surface of the gate dielectric layer is the first and second source/ Extends between drain regions-
Including;
The shallow trench isolation region is separate from and spaced apart from the outer perimeter of the first and second source/drain regions, and one side of the gate electrode without laterally surrounding the gate electrode. ) Having an outer periphery disposed in the integrated circuit (IC). As an integrated circuit (IC),
A semiconductor substrate having a front surface and a rear surface;
First and second source/drain regions extending into the front surface of the semiconductor substrate, wherein the first and second source/drain regions are separated from each other by a channel region in the semiconductor substrate;
A gate electrode extending into the front surface of the semiconductor substrate and disposed over the channel region;
A gate dielectric layer extending into the front surface of the semiconductor substrate to separate an outer sidewall and a bottom surface of the gate electrode from the channel region;
A shallow trench isolation region extending into the front surface of the semiconductor substrate and arranged along an outer edge of the first source/drain region or the second source/drain region, the shallow trench isolation region filled with a dielectric material; And
A composite capacitor comprising a first capacitor terminal and a second capacitor terminal-the total capacitance of the composite capacitor is defined between the first capacitor terminal and the second capacitor terminal, the composite capacitor extending into the shallow trench isolation region, A plurality of vertical capacitor plates electrically separated from each other by the dielectric material in the shallow trench isolation region, wherein a first capacitor plate of the plurality of vertical capacitor plates corresponds to the first capacitor terminal of the composite capacitor And arranged between a second capacitor plate and a third capacitor plate of the plurality of vertical capacitor plates, wherein the second and third capacitor plates are on opposite sides of the first capacitor plate and the composite capacitor Corresponds to the second capacitor terminal-
Including, an integrated circuit (IC). As a method,
Receiving a semiconductor substrate including a logic region and a capacitor region;
Performing a first etching to form a shallow trench isolation recess in the capacitor region;
Forming a shallow trench isolation region by forming a dielectric material in the shallow trench isolation recess;
Performing a second etching to form a gate electrode recess in the logic region and a plurality of capacitor plate recesses in the shallow trench isolation region;
Forming a high-k dielectric material in the gate electrode recess and in the plurality of capacitor plate recesses; And
Simultaneously forming a conductive layer in the gate electrode recess and in the plurality of capacitor plate recesses to establish a gate electrode in the logic region and a plurality of capacitor plates electrically separated from each other in the capacitor region
Containing, the method.

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