KR102252834B1 - System for transferring all M-PHY signals in capacitive communication - Google Patents

Abstract

A system for carrying all signal levels of M-PHY in capacitive communication is disclosed. The system is a circuit that reproduces signals by placing a signal regeneration circuit between the capacitor and the M-PHY RX in the M-PHY system that is electrically separated by a small capacitor to transmit/receive signals: each differential input signal of the circuit and V _CM is connected using a resistor, the differential input signal of the circuit is amplified using a primary amplifier, the output of the primary amplifier is connected to the input of the squelch detector circuit, and the output of the primary amplifier is It is connected to an amplifier, the output of the secondary amplifier is connected to a level shifter, and the outputs of the squelch detector and the level shifter are input to two AND gates to control the VMD with a digital logic value. The VMD includes a system for transmitting all signal levels of the M-PHY in capacitive communication including a circuit for reproducing the signal level of the M-PHY.

Description

System for transferring all M-PHY signals in capacitive communication}

The present invention relates to a system for conveying all signal levels of an M-PHY in capacitive communication.

In the case of amplifying and transmitting differential signals using a CMOS amplifier, the positive (plus, +) / negative (minus, -) signals amplified while using multiple amplifiers are perfectly balanced in the circuit design. Offset occurs due to failure to match or by changes in CMOS process, temperature, and power voltage. In the worst case, the occurrence of such an offset causes a malfunction of the circuit.

Various methods have been proposed to overcome this, and in general, Auto-Zeroing, Chopping, Ping-Pong, Chopper-CDS (Correlated Double Sampling), Offset-Stabilized, and Continuous-Time Integrator used by analog designers. Various offset cancellation circuits are added to reduce offsets caused by each cause, or large devices are used to solve the problem of device-to-device matching.

However, this solution leads to an increase in design complexity, power consumption, and design area. Moreover, when a more fine process is applied, the change caused by the process becomes a factor that further increases the complexity to a more serious level, thus increasing the design difficulty.

As a related prior art, U.S. Patent No. 6,262,625 (OPERATIONALAMPLIFIER WITH DIGITAL OFFSET CALIBRATION) is a change in thresholds of circuits caused by changes in the physical design and process of an amplifier, mismatching of device sizes, and circuits. Disclosed is a technical idea for removing the offset of an analog amplifier caused by changes in operating conditions and the like. However, the prior art has a problem in that a complex circuit is added to remove an offset, thereby increasing the design complexity and increasing the design area.

In FIG. 1, a general MIPI M-PHY defines a state of a line. The MIPI M-PHY is equipped with a state diagram for overall control, and the control of this state is controlled by an internal logic circuit. Among them, TX and RX of MIPI are controlled by using DIF-P, DIF-N and DIF-Z. Accordingly, in the transmission/reception line separated by a capacitor, the receiving end has a limitation that all the signals presented must be restored as it is.

In this regard, US Patent Publication No. 2013/0064310 (CAPACITIVE COMMUNICATION CIRCUIT AND METHOD THEREFOR) is an invention related to a capacitive communication circuit, in which a small resistance is connected between a _{signal line and V REF to the positive and negative receiving ends, respectively, and a capacitor is attached.} A circuit that generates the passed signal as a pulse signal that follows the RC time constant and restores it to the original signal using a latch is proposed. However, such a circuit has a problem in that it cannot be restored at the receiving end when the transmitting end does not drive like the DIF-Z of the M-PHY.

Another related technology, US Patent No. 8,531,238 (CAPACITIVE ISOLATION CIRCUITRY), is an invention for a multi-stage amplifier. The output is compensated for offset by using Common Mode Feedback, and the input signal is amplified several times and output. It is an invention.

However, in the case of the circuit proposed in this prior art, when TX does not drive in MIPI, the output is always driven even if the differential input signal has the same voltage. This not only increases the area due to the added feedback circuit, but also causes power consumption because the circuit is always in an operating state. In addition, there is a problem in that a certain degree of yield reduction may occur when the process change is severe or the surrounding environment is severely changed.

US Patent No. 6,262,625 (OPERATIONALAMPLIFIER WITH DIGITAL OFFSET CALIBRATION) US Patent Publication No. 2013/0064310 (CAPACITIVE COMMUNICATION CIRCUIT AND METHOD THEREFOR) US Patent No. 8,531,238 (CAPACITIVE ISOLATION CIRCUITRY)

In order to have a low power state as in the M-PHY standard, the present invention has a tri-state that does not drive any and all signal levels of the M-PHY in capacitive communication in which data is transmitted at high speed. It is to provide a system for delivering.

The present invention includes a function of reproducing a signal including a tri-state in which the transmitting end does not drive in a state in which the transmitting end and the receiving end are electrically isolated using a small capacitor, and high-speed data transmission in DC is possible. Capacitive that not only provides possible circuits, but also prevents circuit malfunction due to DC offset of CMOS amplifiers caused by parasitic capacitors and variations occurring in semiconductor processes, etc. It is to provide a system for transmitting all signal levels of M-PHY in communication.

In the present invention, in case the transmitting end does not drive, the voltage at the receiving end is equal to the common mode voltage by placing a resistor between the two signal lines and the common mode voltage of the two signal lines so that the differential input signal at the receiving end has the same voltage level. In capacitive communication, it is possible to reproduce the same signal as the transmission signal even by a simple circuit without the need for an offset compensation circuit of the amplifier by using a combination of analog and digital circuits. It is to provide a system for delivering all signal levels of the PHY.

The present invention prevents an increase in design complexity by applying a circuit with a simple structure, reduces the silicon area, and secures an increase in yield by designing that is not sensitive to process fluctuations. -To provide a system for delivering all signal levels of PHY.

In the present invention, it is easy to construct a waterproof/dustproof system because it is easy to shield the system from the outside, and since the measurement system is electrically separated from the main body, it monitors the patient's biosignals when creating a sensitive system such as an electrocardiogram meter. The purpose is to provide a system for transmitting all signal levels of M-PHY in capacitive communication that can promote patient safety because electric shocks unexpectedly generated from the main body are not transmitted to the patient.

Objects other than the present invention will be easily understood through the following description.

According to an aspect of the present invention, a circuit for regenerating a signal by placing a signal regeneration circuit between the capacitor and the M-PHY RX in an M-PHY system that is electrically separated by a small capacitor to transmit/receive a signal: each of the circuits Connect the differential input signal and V _CM using a resistor, amplify the differential input signal of the circuit using a primary amplifier, connect the output of the primary amplifier to the input of the squelch detector circuit, and The output is connected to a secondary amplifier, the output of the secondary amplifier is connected to a level shifter, and the outputs of the squelch detector and the level shifter are input to two AND gates to provide a digital logic value. The VMD is controlled by the VMD, and the VMD is provided with a system for transmitting all signal levels of the M-PHY in capacitive communication including a circuit for reproducing the signal level of the M-PHY.

The system is a circuit that raises the level of the signal by placing an output voltage control circuit between the M-PHY TX and the capacitor when the received input signal level is low: Connect each differential differential input signal of the circuit and VCM using a resistor. , Connecting the differential input signal to an input of a squelch detector circuit, amplifying the differential input signal of the circuit using a primary amplifier, connecting the output of the primary amplifier to a secondary amplifier, and the secondary amplifier LDO circuit for connecting the output of a level shifter, the squelch detector and the output of the level shift are input to two AND gates to control the VMD with a digital logic value, and to control the voltage of the VMD: and the output of the LDO It may include a circuit including an input signal for controlling the voltage level.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

According to an embodiment of the present invention, in order to have a low power state as in the M-PHY standard, there is an effect of transmitting data at high speed while having a tri-state in which the transmitting end does not drive any.

In addition, a circuit capable of high-speed data transmission in DC, including a signal regeneration function including tri-states in which the transmitting end does not drive at the receiving end, in a state where the transmitting end and the receiving end are electrically isolated using a small capacitor. In addition to providing a parasitic capacitor, there is also an effect of simply and safely preventing a circuit malfunction due to a DC offset of a CMOS amplifier caused by a variation occurring in a parasitic capacitor and a semiconductor process.

In addition, in case the transmitter does not drive, a resistor is placed between the two signal lines and the common mode voltage of the two signal lines so that the differential input signal of the receiver has the same voltage level so that the voltage of the receiver becomes the common mode voltage. Also, by using a combination of analog and digital circuits, there is no need for an offset compensation circuit of the amplifier, and there is an effect that the same signal as the transmission signal can be reproduced even by a simple circuit without a complex automatic voltage gain amplifier.

In addition, by applying a circuit with a simple structure, it is possible to prevent an increase in design complexity, reduce a silicon area, and secure an increase in yield by designing insensitive to process fluctuations.

In addition, shielding to protect the system from the outside is easy, so it is easy to configure a waterproof/dustproof system, and since the measurement system is electrically separated from the main body, in case of making a sensitive system such as an electrocardiogram measuring instrument, the main body is monitored while monitoring the patient's biological signals. There is also an effect that the safety of the patient can be promoted as the electric shock that occurs unexpectedly in the patient is not transmitted to the patient.

In addition, in the M-PHY system, which has a transmitting end and a receiving end separated by a small capacitor, the signal is perfectly reproduced and the analog circuit design is simplified to prevent the design from being complicated and the design area from increasing due to the offset compensation circuit. It minimizes the reduction in yield caused by the analog circuit, provides a robust circuit for process changes, etc., and also has the effect of minimizing power consumption by using internal digital control.

In FIG. 1, a general MIPI M-PHY is a diagram defining a state of a line.
2 is a circuit diagram showing the configuration of a signal transmission system according to an embodiment of the present invention.
3 is a circuit diagram showing the configuration of a signal transmission system according to another embodiment of the present invention.

Since the present invention can apply various transformations and have various embodiments, specific embodiments are illustrated in the drawings and will be described in detail in the detailed description. However, this is not intended to limit the present invention to a specific embodiment, it should be understood to include all conversions, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the present invention, when it is determined that a detailed description of a related known technology may obscure the subject matter of the present invention, a detailed description thereof will be omitted.

Terms such as first and second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another component.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof does not preclude in advance.

2 is a circuit diagram showing the configuration of a signal transmission system according to an embodiment of the present invention.

The signal transmission system according to the present embodiment is a system in which a capacitor is placed between the transmitting end and the receiving end of the MIPI M-PHY to perform communication, and the DIF-P, DIF-N and DIF-Z differential signals of the transmitting end are originally received at the receiving end. In order to reproduce signals as they are, analog and digital circuits are combined. When the line in the state where the transmitter does not drive (for example, HIBERN8 state in M-PHY) is DIF-Z, the signal regeneration circuit of the receiver has a low power state. There is a feature that makes it possible.

Referring to FIG. 1, the signal transmission system 101 functions to restore and transmit a signal transmitted from the M-PHY TX 120 to the M-PHY RX 123 as it is. The capacitive circuit configuration constituted by the capacitor 119 and the parasitic capacitor 122 determines the level of a signal applied to the receiving terminal 102 by the signal transmitted from the TX 120.

When facing a pattern on a PCB or a small metal pattern close together, a capacitor is created between the two patterns according to the principle of electromagnetism. Therefore, the capacitor value has a characteristic that the smaller the pattern size is, the smaller the distance of the metal pattern is.

In addition to the above-described capacitor, a parasitic capacitor exists at the receiving end and is connected in series. According to the size of the two capacitors, the level of a signal transmitted from the transmitting end is received at a reduced signal level at the receiving end. The signal level determined by these two capacitors is input to the receiving end by combining the level of the signal transmitted from the transmitting end. Therefore, in general, an automatic gain control amplifier (AGC Amp.) is used at the receiving end.

Differential input signal lines at the receiving end are connected to _{V CM by resistors 103, respectively.} Therefore, in the DIF-Z state where TX does not drive, all input differential signal lines 102 are fixed to the _{V CM level.}

At this time, the resistor 103 has a large RC time constant by using a sufficiently large value, and when a signal is applied to the input and the level rises or falls, the level gradually decreases as time passes. This is to prevent a circuit malfunction due to a sharp decrease in the received signal level during low-speed data transmission.

The first amplifier 116 is designed using a simple single-stage amplifier and a physically large device, so that offset compensation is not required. The second amplifier 117 receives the amplified signal from the first amplifier 116 and performs secondary amplification so that the level shifter 118 amplifies it as a digital output.

The level shifter 118 receives the secondary amplified differential signal and outputs it as a digital output.

The squelch detector 110 outputs a logic "0" when the difference between the differential input signal is less than a certain voltage, and outputs a logic "1" when the difference between the differential input signal is greater than or equal to a certain voltage.

AND gates 112 and 113 drive a voltage mode driver (VMD) 115 having the same structure as the output terminal of TX 120 by input logic signals.

When all input signals are logic "0", the VMD 115 becomes a tri-state and operates the same as the TX terminal, and outputs the output as the same signal as the TX of the M-PHY depending on whether the input is 1/0 or 0/1. do.

The receiving input is first applied to the first amplifier 116 through the receiving end 102 to perform some amplification. This is because if the received signal level is too low and the input voltage level difference of the squelch detector 110 that detects the voltage level difference of the differential input signal is too small, it is not detected even when a signal is sent from TX 120, and the output is always set to a logic "0". This is to prevent printing as ".

Therefore, when the DIF-Z signal is input, the squelch detector 110 outputs a logic "0" and is applied to the AND gates 112 and 113 to make the outputs of both AND gates a logic "0". As a result, the VMD 115 The two logic “0” signals applied to) become DIF-Z, which does not drive the same as that of TX 120.

In addition, the output of the squelch detector 110 is applied to the first amplifier 116 and the level shifter 118 to turn off the circuit so that power is not consumed in the two circuits in the DIF-Z state.

When DIF-P or DIF-N is applied, the output of the squelch detector 110 becomes a logic "1", and the AND gates 112 and 113 are changed according to the output value of the level shifter 118, which drives the VMD. And make the signal of TX 120 as it is. In addition, the output of the squelch detector 110 causes the second amplifier 117 and the level shifter 118 to be activated.

3 is a circuit diagram showing the configuration of a signal transmission system according to another embodiment of the present invention.

The signal transmission system shown in FIG. 3 shows a configuration in which an output voltage control circuit is disposed between the TX 120 and the capacitor 119 at the transmitting end to adjust the input signal level, unlike the configuration of FIG. 2 described above.

In this case, the signal regeneration circuit used at the receiving end for reuse of the design, i.e., the resistor 203, the first and second amplifiers 216 and 218, the squelch detector 210, the level shifter 218, and the AND gate 212 And 213, VMD 215 can be reused as it is. However, in this case, since the output of TX 120 is electrically connected to the first amplifier 216 as it is, there is no decrease in signal level, so the input of the squelch detector is output from the output of the second amplifier 217 to the output of TX 202. Connect directly to

In FIG. 3, the power line 223 of the VMD 215 is connected to an output of a low-drop out (LDO) 221, and the level of the LDO 221 is determined by the digital control signal 222. Accordingly, an apparatus for adjusting the signal level at the transmitting end in order to adjust the received voltage level determined by the capacitors of FIG. 2 is provided.

Although the above has been described with reference to the embodiments of the present invention, those of ordinary skill in the relevant technical field variously modify the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. And it will be appreciated that it can be changed.

103: resistance 216, 218: amplifier
210: squelch detector 218: level shifter

Claims (2)

In an M-PHY system that is electrically separated by a capacitor and transmits/receives a signal, a circuit to reproduce a signal by placing a signal regeneration circuit between the capacitor and the M-PHY RX: and
Each differential input signal of the circuit and VCM are connected using a resistor, the differential input signal of the circuit is amplified using a primary amplifier, and the output of the primary amplifier is used as an input of a squelch detector circuit. Connect, connect the output of the primary amplifier to the secondary amplifier, connect the output of the secondary amplifier to a level shifter, and the output of the squelch detector and the level shifter are A system for transmitting all signal levels of the M-PHY in capacitive communication including a circuit that is input to the AND gate and controls the VMD with a digital logic value, and the VMD is a circuit for reproducing the signal level of the M-PHY.
The method of claim 1,
A circuit that raises the level of the signal by placing an output voltage control circuit between the M-PHY TX and the capacitor when the received input signal level is low enough that the squelch detector outputs a logic "0": Each differential differential input signal of the circuit And VCM are connected using a resistor, the differential input signal is connected to the input of the squelch detector circuit, the differential input signal of the circuit is amplified using a primary amplifier, and the output of the primary amplifier is It is connected to an amplifier, the output of the secondary amplifier is connected with a level shifter, the squelch detector and the output of the level shift are input to two AND gates to control the VMD with digital logic values, and the voltage of the VMD LDO circuit: and
A system for transmitting all signal levels of the M-PHY in capacitive communication further comprising a circuit having an input signal for controlling the output voltage level of the LDO.

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