KR102248788B1 - Integrated circuit device and method of manufacturing the same - Google Patents

Abstract

The integrated circuit device includes a lower wiring structure including a lower metal film penetrating at least a portion of a first insulating film formed on a substrate, a capping layer covering an upper surface of the lower metal film, a second insulating film covering the capping layer, and the second insulating film. 2 An upper wiring structure that penetrates through the insulating layer and the capping layer and is connected to the lower metal layer, and is disposed between the lower metal layer and the second insulating layer and has a width defined by the capping layer and the upper wiring structure. Includes an air gap.

Description

Integrated circuit device and method of manufacturing the same}

The technical idea of the present invention relates to an integrated circuit device and a method of manufacturing the same, and more particularly, to an integrated circuit device including a multilayer wiring structure and a method of manufacturing the same.

Due to the development of electronic technology, down-scaling of integrated circuit devices is rapidly progressing, and line widths and pitches of metal wiring layers included in integrated circuit devices are also being refined. Accordingly, it is necessary to improve the life and reliability of the integrated circuit device by minimizing physical damage to the multilayer wiring structure including the metal wiring layers while suppressing the increase in resistance and leakage current of the metal wiring layers, and suppressing the electromigration of the metal. have.

The technical problem to be achieved by the technical idea of the present invention is an integrated circuit device capable of improving life and reliability by preventing physical damage to a multilayered wiring structure while suppressing an increase in resistance and leakage current of metal wiring layers, suppressing electron movement of metal, and It is to provide a manufacturing method.

An integrated circuit device according to an aspect of the inventive concept includes a lower wiring structure including a lower metal film penetrating at least a portion of a first insulating film formed on a substrate, a capping layer covering an upper surface of the lower metal film, and A second insulating layer covering the capping layer, an upper wiring structure passing through the second insulating layer and the capping layer and connected to the lower metal layer, and the capping layer disposed between the lower metal layer and the second insulating layer And an air gap having a width defined by the upper wiring structure.

According to another aspect of the inventive concept, an integrated circuit device includes a lower wiring structure including a lower metal line extending in a first direction and penetrating at least a portion of a first insulating layer formed on a substrate, and A capping layer covering an upper surface and an upper surface of the first insulating layer; a second insulating layer covering the capping layer; a contact plug connected to the lower metal line through the second insulating layer and the capping layer; and the lower metal line And an air gap disposed between the lower metal line and the second insulating layer in a corner region defined by an upper surface of and a sidewall of the contact plug.

In a method of manufacturing an integrated circuit device according to an aspect of the inventive concept, a first hole is formed by etching a first insulating layer on a substrate. A lower wiring structure including a lower metal layer is formed in the first hole. A capping layer covering the lower wiring structure and the first insulating layer is formed. A second insulating layer covering the capping layer is formed. A second hole penetrating the second insulating layer and the capping layer in a first direction is formed. A part of the capping layer is removed in a second direction perpendicular to the first direction through the second hole to form a cutout region communicating with the second hole in the capping layer. An upper wiring structure is formed in the second hole to form an air gap defined by the upper wiring structure in the cutout area.

The integrated circuit device according to the technical idea of the present invention includes a capping layer covering the metal film in a multilayer wiring structure, thereby increasing resistance of the metal film and suppressing leakage current, and suppressing the movement of electrons from the metal film to include the metal film. The reliability of the multilayer wiring structure can be improved. In addition, the multilayer wiring structure includes an air gap disposed in a corner region defined by an upper surface of a lower metal film constituting a lower wiring structure and a sidewall of the upper wiring structure. Accordingly, even when peeling or cracking occurs at the lower wiring structure, the upper wiring structure, the insulating films surrounding them, or an interface between each of them, the peeling or crack propagation may be stopped in the air gap. Accordingly, it is possible to improve the reliability of the integrated circuit device by suppressing the operation failure and the decrease in lifespan of the integrated circuit device in the multilayer wiring structure.

1A is a cross-sectional view illustrating main components of an integrated circuit device according to embodiments of the inventive concept. FIG. 1B is a layout diagram showing a planar structure according to an example of some configurations of the integrated circuit device illustrated in FIG. 1A.
1C to 1E are layout diagrams showing a planar structure according to another example of some configurations of the integrated circuit device illustrated in FIG. 1A, respectively.
2 to 7 are cross-sectional views each illustrating an integrated circuit device according to other embodiments according to the technical idea of the present invention.
8A is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept. FIG. 8B is an enlarged and more detailed cross-sectional view of a portion indicated by “X1” in FIG. 8A.
9 and 10 are cross-sectional views showing main configurations of an integrated circuit device according to still other embodiments according to the technical idea of the present invention, and other configurations of a portion corresponding to a portion indicated by “X1” in FIG. 8A Is a cross-sectional view showing.
11 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.
12 to 16 are cross-sectional views for explaining an integrated circuit device according to still another embodiment according to the technical idea of the present invention, respectively, showing another configuration of a portion corresponding to a portion indicated by “X2” in FIG. 11 It is a cross-sectional view.
17 and 18 are cross-sectional views each illustrating an integrated circuit device according to still other embodiments according to the inventive concept.
19A to 19F are cross-sectional views illustrating exemplary methods of manufacturing an integrated circuit device according to embodiments of the inventive concept according to a process sequence.
20 to 24 are cross-sectional views each illustrating an integrated circuit device according to still other embodiments according to the technical idea of the present invention.
FIG. 25A is a layout diagram illustrating a main configuration of an integrated circuit device according to still another exemplary embodiment according to the inventive concept, and FIG. 25B is a cross-sectional view taken along line B-B' of FIG. 25A.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

1A is a cross-sectional view illustrating main components of an integrated circuit device according to embodiments of the inventive concept.

Referring to FIG. 1A, the integrated circuit device 100 includes a lower wiring structure 130 penetrating at least a portion of the first insulating layer 124 formed on the substrate 110. The lower wiring structure 130 may include a conductive line portion extending in one direction, for example, in the X direction.

The substrate 110 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. The substrate 110 may include a conductive region (not shown), for example, circuit elements (not shown) such as a gate structure, an impurity region, and a contact plug.

A first etch stop layer 112 and a lower insulating layer 114 and a lower conductive layer 120 penetrating them may be disposed on the substrate 110. The first etch stop layer 112 may be made of a material having an etching selectivity different from that of the lower insulating layer 114. For example, the first etch stop layer 112 may be formed of a silicon nitride layer, a carbon-doped silicon nitride layer, a carbon-doped silicon oxynitride layer, a metal nitride layer, or a combination thereof. In some embodiments, the lower insulating layer 114 may be made of a silicon oxide-based material. For example, the lower insulating layer 114 is PEOX (plasma enhanced oxide), TEOS (tetraethyl orthosilicate), BTEOS (boro TEOS), PTEOS (phosphorous TEOS), BPTEOS (boro phospho TESO), BSG (boro silicate glass), PSG (phospho silicate glass), BPSG (boro phospho silicate glass), or the like. In some other embodiments, the lower insulating layer 114 may be formed of a low dielectric layer having a low dielectric constant K of about 2.2 to 3.0, for example, a SiOC layer or a SiCOH layer. The lower conductive layer 120 may include a metal layer and a conductive barrier layer surrounding the metal layer. The metal film may be formed of Cu, W, Al, Co, Ru, or a combination thereof. The conductive barrier layer may be formed of Ta, TaN, Ti, TiN, or a combination thereof. The lower conductive layer 120 may be connected to a conductive region formed on the substrate 110, for example, a source/drain region (not shown) or a gate electrode (not shown) of a transistor formed on the substrate 110.

A second etch stop layer 122 and a first insulating layer 124 may be sequentially disposed on the lower insulating layer 114. The lower wiring structure 130 may penetrate the first insulating layer 124 and the second etch stop layer 122 and extend to the lower conductive layer 120. A more specific configuration of the second etch stop layer 122 and the first insulating layer 124 is substantially the same as described for the first etch stop layer 112 and the lower insulating layer 114.

The lower wiring structure 130 may include a lower conductive barrier layer 132 and a lower metal layer 136. The lower conductive barrier layer 132 may surround the bottom surface and sidewalls of the lower metal layer 136. The lower conductive barrier layer 132 may be formed of Ta, TaN, Ti, TiN, or a combination thereof. The lower metal layer 136 may be formed of Cu, W, Co, Ru, Mn, Ti, Ta, or a combination thereof.

The upper surface of the lower metal layer 136 is covered with the capping layer 150. The capping layer 150 may be formed of an insulating capping layer, a conductive capping layer, or a combination thereof. In some embodiments, the capping layer 150 is silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, metal, alloy, Or it may be made of a combination of these. The term "alloy" as used herein refers to a material composed of a combination of different kinds of metals or a material composed of a combination of a metal and an element other than a metal. In one example, the capping layer 150 may include a metal selected from Co, Ni, Ta, Ru, W, Mn, and combinations thereof. In another example, the capping layer 150 may include at least one metal selected from Co, Ni, Ta, Ru, W, and Mn, and a semiconductor element selected from Si and Ge. In some other embodiments, the capping layer 150 may include a nitrogen-containing layer on or inside the capping layer 150. For example, the capping layer 150 may include a nitride of a metal selected from Co, Ni, Ta, Ru, W, Mn, and combinations thereof.

The capping layer 150 is covered with the second insulating layer 156. The upper wiring structure 160 extends through the second insulating layer 156 and the capping layer 150 to be electrically connected to the lower metal layer 136. The upper wiring structure 160 may include an upper conductive barrier layer 162 and an upper metal layer 166. Details of the constituent materials of the upper conductive barrier layer 162 and the upper metal layer 166 are as described for the lower conductive barrier layer 132 and the lower metal layer 136. In some embodiments, the upper wiring structure 160 may constitute a contact plug. The lower wiring structure 130 may include a conductive line portion connected to the upper wiring structure 160 and a contact plug portion protruding from the conductive line portion toward the substrate 110 and connected to the lower conductive layer 120. .

An air gap AG1 is disposed around the upper wiring structure 160 between the lower metal layer 136 and the second insulating layer 156. The width W1 of the air gap AG1 may be limited by the capping layer 150 and the upper wiring structure 160. The width W1 of the air gap AG1 is the horizontal distance between the sidewall of the upper wiring structure 160 exposed into the air gap AG1 and the sidewall of the capping layer 150 exposed inside the air gap AG1. Corresponds. The width W1 of the air gap AG1 may be about 2 to 10 nm, but is not limited thereto. The lower metal layer 136 may provide a lower limit of the air gap AG1, and the second insulating layer 156 may provide an upper limit of the air gap AG1. The height of the air gap AG1 corresponds to the thickness D1 of the capping layer 150, and the height of the air gap AG1 may be limited by the lower metal layer 136 and the second insulating layer 156.

The air gap AG1 may be disposed in a corner region defined by an upper surface of the lower metal layer 136 and a sidewall of the upper wiring structure 160. In some embodiments, the air gap AG1 may extend to surround the upper wiring structure 160 along its circumferential direction at a position perpendicular to the lower metal layer 136. In this specification, "overlap vertically" means overlap with each other along the Z direction.

The capping layer 150 includes a cutout area 150C having a width 150W larger than the width 160W of the bottom surface of the upper wiring structure 160, and the air gap AG1 is a cutout area. It may have a volume excluding a portion occupied by the upper wiring structure 160 of 150C.

In some embodiments, at least one of the first insulating layer 124 and the second insulating layer 156 may be made of a silicon oxide-based material such as PEOX, TEOS, BTEOS, PTEOS, BPTEOS, BSG, PSG, BPSG, and the like. In some other embodiments, at least one of the first insulating film 124 and the second insulating film 156 is a low dielectric film having a low dielectric constant K of about 2.7 to 3.0, for example, a SiOC film or a SiCOH film. Can be made. In still other embodiments, at least one of the first insulating layer 124 and the second insulating layer 156 is an ultra low K (ULK) layer having an ultra low dielectric constant K of about 2.2 to 2.4, For example, it may be made of a SiOC film or a SiCOH film. In still other embodiments, at least one of the first insulating layer 124 and the second insulating layer 156 is each of a fluorine-doped silicon oxide (F-SiO ₂ ), a porous silicon oxide, a spin-on organic polymer, and HSSQ (hydrogen silsesquioxane), MSSQ (methyl silsesquioxane), and the like.

FIG. 1B is a layout diagram showing a planar structure according to an example of some configurations of the integrated circuit device 100 illustrated in FIG. 1A. 1A and 1B, the air gap AG1 may have an annular shape surrounding the upper wiring structure 160 on the upper surface of the lower metal layer 136. The width of the air gap AG1 may be constant along the circumferential direction of the upper wiring structure 160. Among the air gaps AG1, the width W11X along the length direction (X direction) of the lower metal layer 136 and the width W11Y along the width direction (Y direction) of the lower metal layer 136 may be approximately the same. have. The capping layer 150 may not be in contact with the upper wiring structure 160.

1C to 1E are layout diagrams showing a planar structure according to another example of some configurations of the integrated circuit device 100 illustrated in FIG. 1A, respectively.

1A and 1C, the air gap AG1 may have an annular shape surrounding the upper wiring structure 160 on the upper surface of the lower metal layer 136. The width of the air gap AG1 may be variable along the circumferential direction of the upper wiring structure 160. The width W12X of the lower metal layer 136 along the length direction (X direction) of the air gap AG1 may be larger than the width W12Y along the width direction (Y direction) of the lower metal layer 136 . The capping layer 150 may not be in contact with the upper wiring structure 160.

1A and 1D, the air gap AG1 may partially surround the upper wiring structure 160 on the upper surface of the lower metal layer 136. The air gap AG1 may be disposed between the capping layer 150 and the upper wiring structure 160 in the length direction (X direction) of the lower metal layer 136, and may be disposed in the width direction of the lower metal layer 136 ( In the Y direction), there may be a portion where the capping layer 150 (refer to FIG. 1A) and the upper wiring structure 160 contact each other.

1A and 1E, the upper wiring structure 160 is formed at a position shifted from the center in the width direction of the lower metal layer 136 along the width direction, so that a part of the upper wiring structure 160 is formed of the lower metal layer 136. ) May be formed to cover the upper surface of the first insulating layer 124 in the periphery. In FIG. 1E, the position of the first insulating layer 124 covered with the capping layer 150 is indicated by a dotted line. The upper wiring structure 160 may include a portion vertically overlapping the lower metal layer 136 and a portion vertically overlapping the first insulating layer 124. The upper wiring structure 160 may partially surround the air gap AG1 on the upper surface of the lower metal layer 136. The air gap AG1 is not formed around a portion of the upper wiring structure 160 that overlaps in a vertical direction with the first insulating layer 124, but the upper wiring so as to surround only the portion perpendicularly overlapping with the lower metal layer 136. It may extend along the circumferential direction of the structure 160.

Although exemplary planar shapes of the air gap AG1 have been described with reference to FIGS. 1B to 1E, the technical idea of the present invention is not limited thereto. Within the scope of the technical idea of the present invention, the air gap AG1 may have variously deformed and changed planar shapes.

2 is a cross-sectional view illustrating an integrated circuit device according to other embodiments according to the inventive concept.

Referring to FIG. 2, the integrated circuit device 200 has substantially the same configuration as the integrated circuit device 100 illustrated in FIG. 1. However, in the integrated circuit device 200, the upper surface of the lower metal layer 136 is covered with a capping layer 250 made of multiple insulating layers. The capping layer 250 may include a first insulating capping layer 250A containing a metal and a second insulating capping layer 250B not containing a metal. The first insulating capping layer 250A may be made of AlN, AlON, AlO, or AlOC. The second insulating capping layer 250B may be made of silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), or SiOC.

The capping layer 250 is covered with the second insulating layer 156. The upper wiring structure 160 extends through the second insulating layer 156 and the capping layer 250 to be electrically connected to the lower metal layer 136.

An air gap AG2 surrounding the upper wiring structure 160 is disposed between the lower metal layer 136 and the second insulating layer 156. The width W2 of the air gap AG2 may be defined by the first insulating capping layer 250A and the upper wiring structure 160 of the capping layer 250. The width W2 of the air gap AG2 is between the sidewall of the upper wiring structure 160 exposed inside the air gap AG2 and the sidewall of the first insulating capping layer 250A exposed inside the air gap AG2. Corresponds to the horizontal distance. The width W2 of the air gap AG2 may be about 2 to 10 nm. The height of the air gap AG2 may be limited by the lower metal layer 136 and the second insulating capping layer 250B. The height of the air gap AG2 may correspond to the thickness D2 of the first insulating capping layer 250A.

The air gap AG2 may be disposed in a corner region defined by an upper surface of the lower metal layer 136 and a sidewall of the upper wiring structure 160. The air gap AG2 may have any one of the planar shapes of the air gap AG1 illustrated in FIGS. 1B to 1E, or may have a changed and changed planar shape within the scope of the technical idea of the present invention from these. The first insulating capping layer 250A includes a cutout region 250AC having a width (250AW) greater than the width (160W) of the bottom surface of the upper wiring structure 160, and the air gap AG2 is a cutout region. It may have a volume of 250AC excluding a portion occupied by the upper wiring structure 160.

3 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.

Referring to FIG. 3, the integrated circuit device 300 has substantially the same configuration as the integrated circuit device 100 illustrated in FIG. 1. However, the lower wiring structure 130 of the integrated circuit device 300 further includes a lower metal liner 134 interposed between the lower conductive barrier layer 132 and the lower metal layer 136, and the upper wiring structure Reference numeral 160 further includes an upper metal liner 164 interposed between the upper conductive barrier layer 162 and the upper metal layer 166.

The lower and upper metal liners 134 and 164 may include a metal different from the metal included in the lower and upper metal layers 136 and 166, respectively. For example, the lower and upper metal layers 136 and 166 are made of any one first metal selected from Cu, W, Co, Ru, Mn, Ti, and Ta, and the lower and upper metal liners 134, 164) may be selected from Co, Ni, Ta, Ru, W, and Mn, and may be made of a second metal different from the first metal, or may be made of an alloy containing the second metal. In some embodiments, the lower and upper metal liners 134 may each be a Co liner or a Ta liner.

4 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.

Referring to FIG. 4, the integrated circuit device 400 has substantially the same configuration as the integrated circuit device 200 illustrated in FIG. 2. However, in the integrated circuit device 400, the lower wiring structure 130 further includes a lower metal liner 134 interposed between the lower conductive barrier layer 132 and the lower metal layer 136, and the upper wiring structure Reference numeral 160 further includes an upper metal liner 164 interposed between the upper conductive barrier layer 162 and the upper metal layer 166.

5 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.

Referring to FIG. 5, the integrated circuit device 500 has substantially the same configuration as the integrated circuit device 400 illustrated in FIG. 4. However, in the integrated circuit device 500, the upper surface of the lower metal layer 136 is covered with a capping layer 550 formed of a combination of a conductive layer and an insulating layer. The capping layer 550 includes a conductive capping layer 550T, a first insulating capping layer 550A containing a metal, and a second insulating capping layer 250B containing no metal.

The conductive capping layer 550T may include the same metal as the metal constituting the lower metal liner 134. For example, the conductive capping layer 550T may be made of a metal or alloy selected from Co, Ni, Ta, Ru, W, Mn, and combinations thereof. The first insulating capping layer 550A may be made of AlN, AlON, AlO, or AlOC. The capping layer 550 is covered with the second insulating layer 156. The upper wiring structure 160 penetrates the second insulating layer 156 and the capping layer 550 and extends to the lower metal layer 136.

An air gap AG5 is disposed between the lower metal layer 136 and the second insulating layer 156. In particular, the air gap AG5 is disposed between the lower metal layer 136 and the first insulating capping layer 550A, and the air gap AG5 is formed by the conductive capping layer 550T and the upper wiring structure 160. The width W5 of may be limited. The width W5 of the air gap AG5 is the horizontal distance between the sidewall of the conductive capping layer 550T exposed inside the air gap AG5 and the sidewall of the upper wiring structure 160 exposed inside the air gap AG5 Corresponds to. The width W5 of the air gap AG5 may be about 2 to 10 nm. The height of the air gap AG5 may be limited by the lower metal layer 136 and the first insulating capping layer 550A, and may correspond to the thickness D5 of the conductive capping layer 550T.

The air gap AG5 may be disposed in a corner region defined by an upper surface of the lower metal layer 136 and a sidewall of the upper wiring structure 160. The air gap AG5 may have any one of the planar shapes of the air gap AG1 illustrated in FIGS. 1B to 1E, or a planar shape that has been changed and changed within the scope of the technical idea of the present invention from these.

Among the capping layers 550, the first insulating capping layer 550A and the second insulating capping layer 250B may contact sidewalls of the upper wiring structure 160. The conductive capping layer 550T includes a cutout region 550TC having a width (550TW) greater than the width (160W) of the bottom surface of the upper wiring structure 160, and the air gap AG5 is the cutout region 550TC. ) May have a volume excluding a portion occupied by the upper wiring structure 160.

6 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.

Referring to FIG. 6, the integrated circuit device 600 has substantially the same configuration as the integrated circuit device 500 illustrated in FIG. 5. In the integrated circuit device 600, the upper surface of the lower metal layer 136 is covered with a capping layer 650 formed of a combination of a conductive layer and an insulating layer. The capping layer 650 includes a conductive capping layer 550T, a first insulating capping layer 650A containing a metal, and a second insulating capping layer 250B containing no metal. However, in the capping layer 650 of the integrated circuit device 600, the first insulating capping layer 650A is spaced apart from the sidewall of the upper wiring structure 160.

An air gap AG6 is disposed between the lower metal layer 136 and the second insulating layer 156. In particular, the air gap AG6 is disposed between the lower metal layer 136 and the second insulating capping layer 250B. A sidewall of the conductive capping layer 550T facing the upper wiring structure 160 and a sidewall of the first insulating capping layer 650A facing the upper wiring structure 160 are respectively formed at the upper portion with the air gap AG6 interposed therebetween. A portion spaced apart from the wiring structure 160 may be included. Among the conductive capping layers 550T, the lower width W6A of the air gap AG6 is limited by the sidewall facing the upper wiring structure 160 and the upper wiring structure 160, and among the first insulating capping layer 650A The upper width W6B of the air gap AG6 may be limited by the sidewall facing the upper wiring structure 160 and the upper wiring structure 160. The lower width W6A and the upper width W6B of the air gap AG6 have different sizes. 6 illustrates a case where the lower width W6A of the air gap AG6 is larger than the upper width W6B, but the upper width W6B of the air gap AG6 may be larger than the lower width W6A. . The lower width W6A and the upper width W6B of the air gap AG6 may have a size selected within a range of about 2 to 10 nm. The height of the air gap AG6 may be limited by the lower metal layer 136 and the second insulating capping layer 250B. The height of the air gap AG6 may correspond to the sum of the thickness D5 of the conductive capping layer 550T and the thickness D6 of the first insulating capping layer 650A.

The air gap AG6 may be disposed in a corner region defined by an upper surface of the lower metal layer 136 and a sidewall of the upper wiring structure 160. The air gap AG6 may have any one of the planar shapes of the air gap AG1 illustrated in FIGS. 1B to 1E, or may have a changed and changed planar shape within the scope of the technical idea of the present invention from these.

7 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.

Referring to FIG. 7, the integrated circuit device 700 has substantially the same configuration as the integrated circuit device 600 illustrated in FIG. 6. In the integrated circuit device 700, the upper surface of the lower metal layer 136 is covered with the capping layer 750. The capping layer 750 includes a conductive capping layer 550T, a first insulating capping layer 750A containing a metal, and a second insulating capping layer 250B containing no metal. The capping layer 750 is substantially similar to the capping layer 650 illustrated in FIG. 6, but the sidewall of the conductive capping layer 550T facing the upper wiring structure 160 and the upper wiring of the first insulating capping layer 750A It differs from the capping layer 650 illustrated in FIG. 6 in that the sidewalls facing the structure 160 form one substantially flat plane without a step therebetween.

An air gap AG7 is disposed between the lower metal layer 136 and the second insulating capping layer 250B. The air gap AG7 may have approximately the same width W7 between the conductive capping layer 550T and the upper wiring structure 160, and between the first insulating capping layer 750A and the upper wiring structure 160. have. The width W7 of the air gap AG7 may be about 2 to 10 nm. The air gap AG7 may have a height corresponding to the sum of the thickness D5 of the conductive capping layer 550T and the thickness D7 of the first insulating capping layer 750A.

The air gap AG7 may be disposed in a corner region defined by an upper surface of the lower metal layer 136 and a sidewall of the upper wiring structure 160. The air gap AG7 may have any one of the planar shapes of the air gap AG1 illustrated in FIGS. 1B to 1E, or may have a changed and changed planar shape within the scope of the technical idea of the present invention from these.

8A is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept. FIG. 8B is an enlarged and more detailed cross-sectional view of a portion indicated by “X1” in FIG. 8A.

8A and 8B, the integrated circuit device 800A has substantially the same configuration as the integrated circuit device 700 illustrated in FIG. 7. However, in the integrated circuit device 800A, the upper wiring structure 860A includes a protrusion 860P1 protruding toward the air gap AG7. The upper wiring structure 860A includes an upper conductive barrier layer 862A, an upper metal liner 864, and an upper metal layer 866, and at least some of them are from the protrusion 860P1 toward the air gap AG7. It may have a protruding shape. For a more detailed configuration of the upper conductive barrier film 862A, the upper metal liner 864, and the upper metal film 866, referring to FIG. 3, the upper conductive barrier film 162, the upper metal liner 164, and the upper As described for the metal film 166.

The upper conductive barrier layer 862A and the upper metal liner 864 each include local regions 862F and 864F facing the air gap AG7 at the protrusion 860P1. At least a portion of the local regions 862F and 864F may have a thickness smaller than portions of the upper conductive barrier layer 862A and the upper metal liner 864 facing the second insulating layer 156. The local regions 862F and 864F protrude more outward of the upper wiring structure 860A than portions of the upper conductive barrier layer 862A and the upper metal liner 864 facing the second insulating layer 156.

9 and 10 are cross-sectional views showing main configurations of an integrated circuit device according to still other embodiments according to the technical idea of the present invention, and other configurations of a portion corresponding to a portion indicated by “X1” in FIG. 8A Is a cross-sectional view showing.

Referring to FIG. 9, the integrated circuit device 800B has substantially the same configuration as the integrated circuit device 700 illustrated in FIG. 7. The upper wiring structure 860B includes an upper conductive barrier layer 862B, an upper metal liner 864, and an upper metal layer 866. However, in the integrated circuit device 800B, an opening 862H communicating with the air gap AG7 is formed in the upper conductive barrier film 862B of the upper wiring structure 860B. Accordingly, the upper conductive barrier layer 862B may discontinuously extend in a portion adjacent to the air gap AG7. The upper wiring structure 860B may include a protrusion 860P2. The local area 864F of the upper metal liner 864 may protrude toward the air gap AG7 from the protrusion 860P2. The protrusion 860P2 may face the air gap AG7 through the opening 862H of the upper conductive barrier layer 862B. A more detailed configuration of the upper conductive barrier layer 862B is substantially the same as that described for the upper conductive barrier layer 162 with reference to FIG. 3.

Referring to FIG. 10, the integrated circuit device 800C has substantially the same configuration as the integrated circuit device 700 illustrated in FIG. 7. However, in the integrated circuit device 800C, the upper wiring structure 860C includes a protrusion 860P3 protruding toward the air gap AG7. The upper wiring structure 860C includes an upper conductive barrier layer 862C, an upper metal liner 864C, and an upper metal layer 866. At least one of the upper conductive barrier layer 862C, the upper metal liner 864C, and the upper metal layer 866 may have a shape protruding from the protrusion 860P3 toward the air gap AG7. For a more detailed configuration of the upper conductive barrier film 862C, the upper metal liner 864C, and the upper metal film 866, referring to FIG. 3, the upper conductive barrier film 162, the upper metal liner 164, and the upper It is substantially the same as described for the metal film 166. In some embodiments, the upper conductive barrier layer 862C may have an approximately constant thickness depending on the location where the upper conductive barrier layer 862C is formed. For example, the thickness of the upper conductive barrier layer 862C at the protrusion 860P3 facing the air gap AG7 and the thickness at the portion facing the second insulating layer 156 may be substantially the same. Parts of the upper conductive barrier layer 862C and the upper metal liner 864C constituting the protrusion 860P3 may protrude outward of the upper wiring structure 860C than portions facing the second insulating layer 156.

11 is a cross-sectional view illustrating an integrated circuit device according to still other embodiments according to the inventive concept.

Referring to FIG. 11, the integrated circuit device 900 has substantially the same configuration as the integrated circuit device 400 illustrated in FIG. 4. However, in the integrated circuit device 900, the upper surface of the lower metal layer 136 is covered with the capping layer 950. The capping layer 950 has a structure in which a conductive alloy capping layer 950T, a first insulating capping layer 950A including metal, and a second insulating capping layer 250B not including metal are sequentially stacked.

The conductive alloy capping layer 950T may be formed of an alloy of a metal or alloy selected from Co, Ni, Ta, Ru, W, Mn, and combinations thereof, and a semiconductor element selected from Si and Ge. In some embodiments, the conductive alloy capping layer 950T is represented by M _x A _y (where M is a metal, A is Si or Ge, x is an integer from 1 to 6, and y is an integer from 1 to 10). It can be made of a material. For example, the conductive alloy capping layer 950T may be formed of CoSi, CoSi ₂ , Co ₂ Si, Co ₃ Si, CoGe, CoGe ₂ , Co ₅ Ge ₃ , Co ₅ Ge ₇ , Co ₄ Ge, and the like. The first insulating capping layer 950A may be formed of AlN, AlON, AlO, or AlOC. The second insulating capping layer 250B may be made of silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), or SiOC. The capping layer 950 is covered with the second insulating layer 156. The upper wiring structure 160 extends through the second insulating layer 156 and the capping layer 950 to be electrically connected to the lower metal layer 136.

An air gap AG9 is disposed between the lower metal layer 136 and the second insulating layer 156. In particular, the air gap AG9 is disposed between the conductive alloy capping layer 950T and the second insulating capping layer 250B, and the air gap is formed by the first insulating capping layer 950A and the upper wiring structure 160. The width W9 of (AG9) may be limited. The width W9 of the air gap AG9 may be about 2 to 10 nm. The height of the air gap AG9 may be air-limited by the conductive alloy capping layer 950T and the second insulating capping layer 250B. The height of the air gap AG9 may correspond to the thickness D9 of the first insulating capping layer 950A.

The air gap AG9 may be disposed in a corner region defined by an upper surface of the lower metal layer 136 and a sidewall of the upper wiring structure 160. The air gap AG9 may have any one of the planar shapes of the air gap AG1 illustrated in FIGS. 1B to 1E, or may have a modified and changed planar shape within the scope of the technical idea of the present invention from these.

Among the capping layers 950, the conductive alloy capping layer 950T and the second insulating capping layer 250B may contact sidewalls of the upper wiring structure 160. The first insulating capping layer 950A includes a cutout region 950AC having a width 950AW greater than the width 160W of the bottom surface of the upper wiring structure 160, and the air gap AG9 is a cutout region. It may have a volume excluding a portion occupied by the upper wiring structure 160 of the 950AC.

12 to 16 are cross-sectional views for explaining an integrated circuit device according to still another embodiment according to the technical idea of the present invention, respectively, showing another configuration of a portion corresponding to a portion indicated by “X2” in FIG. 11 It is a cross-sectional view.

Referring to FIG. 12, the integrated circuit device 900A has substantially the same configuration as the integrated circuit device 900 illustrated in FIG. 11. However, the upper wiring structure 960A of the integrated circuit device 900A includes an upper conductive barrier film 962A, an upper metal liner 964A, and an upper metal film 966, and the upper conductive barrier film 962A Has a reduced thickness in the localized region 962F facing the air gap AG9. The upper metal liner 964A and the upper metal film 966 include protrusions 964P1 and 966P1 protruding toward the air gap AG9, respectively.

Referring to FIG. 13, the integrated circuit device 900B has substantially the same configuration as the integrated circuit device 900 illustrated in FIG. 11. However, the upper wiring structure 960B of the integrated circuit device 900B includes an upper conductive barrier film 962B, an upper metal liner 964B, and an upper metal film 966, and the upper conductive barrier film 962B and Openings 962H and 964H communicating with the air gap AG9 are formed in the upper metal liner 964B, respectively. The upper metal layer 966 may include a protrusion 966P1 protruding toward the air gap AG9, and the protrusion 966P1 may be exposed into the air gap AG9.

Referring to FIG. 14, the integrated circuit device 900C has substantially the same configuration as the integrated circuit device 900 illustrated in FIG. 11. However, the upper wiring structure 960C of the integrated circuit device 900C includes an upper conductive barrier film 962C, an upper metal liner 964C, and an upper metal film 966, and the upper conductive barrier film 962C An opening 962H communicating with the air gap AG9 is formed. The upper metal liner 964C and the upper metal film 966 include protrusions 964P3 and 966P1 protruding toward the air gap AG9, respectively. The protrusion 964P3 of the upper metal liner 964C may be exposed into the air gap AG9.

Referring to FIG. 15, the integrated circuit device 900D has substantially the same configuration as the integrated circuit device 900 illustrated in FIG. 11. However, the upper wiring structure 960D of the integrated circuit device 900D includes an upper conductive barrier layer 962D, an upper metal liner 964D, and an upper metal layer 966. The upper conductive barrier layer 962D includes a local region 962F facing the air gap AG9, and at least some of the local regions 962F face the second insulating layer 156 of the upper conductive barrier layer 962D. It has a smaller thickness than that of the part. The upper metal liner 964D and the upper metal film 966 include protrusions 964P3 and 966P1 protruding toward the air gap AG9, respectively.

Referring to FIG. 16, the integrated circuit device 900E has substantially the same configuration as the integrated circuit device 900 illustrated in FIG. 11. However, the upper wiring structure 960E of the integrated circuit device 900E includes a protrusion 960P protruding toward the air gap AG9. The upper wiring structure 960E includes an upper conductive barrier film 962E, an upper metal liner 964E, and an upper metal film 966. At least a portion of the upper conductive barrier layer 962E, the upper metal liner 964E, and the upper metal layer 966 has a shape protruding from the protrusion 960P toward the air gap AG9. The upper conductive barrier layer 962E may have substantially the same thickness at the protrusion 960P facing the air gap AG9 and at the portion facing the second insulating layer 156.

12 to 16, the upper conductive barrier films 962A, 962B, 962C, 962D, 962E, upper metal liners 964A, 964B, 964C, 964D, 964E, and the upper metal film 966 are detailed. The configuration is substantially the same as described for the upper conductive barrier layer 162, the upper metal liner 164, and the upper metal layer 166 with reference to FIG. 3.

17 and 18 are cross-sectional views each illustrating an integrated circuit device according to still other embodiments according to the inventive concept.

17 and 18, the integrated circuit devices 1000A and 1000B have substantially the same configuration as the integrated circuit device 900 illustrated in FIG. 11. However, in the integrated circuit device 1000A, the lower metal layer 136 is covered with a capping layer 1050 including a first conductive alloy capping layer T1 and a second conductive alloy capping layer T2. The capping layer 1050 includes a second conductive alloy capping layer T2, a first conductive alloy capping layer T1, a first insulating capping layer 950A, and a second insulating cap sequentially stacked on the lower metal layer 136. It includes a ping layer (250B). The first conductive alloy capping layer T1 has substantially the same configuration as described for the conductive alloy capping layer 950T with reference to FIG. 11. The second conductive alloy capping layer T2 is made of an alloy of a metal different from the metal constituting the first conductive alloy capping layer T1 and a semiconductor element selected from Si and Ge. In some embodiments, the second conductive alloy capping layer T2 may be formed of CuSi, Cu ₃ Si, CuGe, or Cu ₃ Ge. The capping layer 1050 is covered with the second insulating layer 156.

In the integrated circuit device 1000A illustrated in FIG. 17, the upper wiring structure 160 is electrically connected to the lower metal layer 136 through the second conductive alloy capping layer T2. The second conductive alloy capping layer T2 is interposed between the upper wiring structure 160 and the upper wiring structure 160. The upper wiring structure 160 penetrates through the second insulating layer 156, the second insulating capping layer 250B, the first insulating capping layer 950A, and the first conductive alloy capping layer T1 to form a second conductive alloy cap. It extends to the upper surface of the ping layer T2.

In the integrated circuit device 1000B illustrated in FIG. 18, the upper wiring structure 160 is in direct contact with the lower metal layer 136. The upper wiring structure 160 includes a second insulating layer 156, a second insulating capping layer 250B, a first insulating capping layer 950A, a first conductive alloy capping layer T1, and a second conductive alloy capping layer ( It penetrates through T2) and extends to the upper surface of the lower metal layer 136.

In general, when a multilayer wiring structure is formed on a substrate, due to a difference in stress between the multilayer wiring structure side and the substrate side, or relatively weak adhesion between different film qualities adjacent to each other in the multilayer wiring structure, the multilayer of the integrated circuit device Peeling or cracking may occur within the wiring structure. Peeling or cracking generated in the multilayer wiring structure may propagate along the interface between the wiring structures and insulating films for insulating them from each other. If peeling or cracking occurs in the multilayer wiring structure and propagating from the point of occurrence to the periphery, the reliability of the integrated circuit device may deteriorate due to poor operation of the integrated circuit device and a reduction in lifespan.

The integrated circuit devices according to embodiments of the present invention described with reference to FIGS. 1A to 18 are air formed in a corner region defined by the upper surface of the lower metal film constituting the lower wiring structure and the sidewall of the upper wiring structure. A gap is included, and the air gap has a size defined by a capping layer covering an upper surface of the lower metal layer and the upper wiring structure. Therefore, even when peeling or cracking occurs at the lower wiring structure, the upper wiring structure, the insulating films surrounding them, or the interface between each of them, when the peeling or crack reaches the air gap, the peeling or crack propagation is caused by the air. It can be stopped in the gap. Therefore, in the integrated circuit devices according to the embodiments according to the technical idea of the present invention, even if peeling or cracking occurs in the multilayer wiring structure, the propagation of these devices is suppressed, thereby preventing the operation failure and lifespan of the integrated circuit device from occurring. And improve the reliability of the integrated circuit device.

19A to 19F are cross-sectional views illustrating exemplary methods of manufacturing an integrated circuit device according to embodiments of the inventive concept according to a process sequence. An exemplary method of manufacturing the integrated circuit device 500 illustrated in FIG. 5 will be described with reference to FIGS. 19A to 19F. In Figs. 19A to 19F, the same reference numerals as in Figs. 1 to 5 denote the same members, and detailed descriptions thereof are omitted here.

Referring to FIG. 19A, a first etch stop layer 112 and a lower insulating layer 114 are formed on a substrate 110, and the substrate 110 passes through the lower insulating layer 114 and the first etch stop layer 112. ) To form a lower conductive layer 120 that can be electrically connected to the conductive region (not shown).

A second etch stop layer 122 and a first insulating layer 124 are formed on the lower insulating layer 114, and the lower conductive layer 120 passes through the first insulating layer 124 and the second etch stop layer 122. A first hole H1 exposing is formed. The first hole H1 may include a first via hole VH1 and a first line hole LH1 communicating with each other. In order to form the first hole H1, the first insulating layer 124 and the second etch stop layer 122 may be dry etched using a plurality of etch mask patterns having different etch selectivity. In FIG. 19A, an area corresponding to the first line hole LH1 is indicated by a dotted line.

Referring to FIG. 19B, a lower conductive barrier layer 132, a lower metal liner 134, and a lower metal layer 136 are sequentially formed in the first hole H1 (see FIG. 19A) to form a first hole H1. A filling lower wiring structure 130 is formed.

In some embodiments, to form the lower metal layer 136, after forming the lower metal liner 134 on the lower conductive barrier layer 132, a metal seed layer (not shown) on the lower metal liner 134 ) Can be formed and the plating process can be performed. In order to form the lower conductive barrier layer 132, the lower metal liner 134, and the metal seed layer, it is composed of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. Process can be used. In some other embodiments, a PVD, CVD, or ALD process may be used instead of a plating process to form the lower metal layer 136. Thereafter, the lower metal layer 136, the lower metal liner 134, and the lower conductive barrier layer 132 are etched and planarized using a chemical mechanical polishing (CMP) process and/or an etch-back process, thereby forming a first hole. The upper surface of the first insulating layer 124 is exposed around (H1) (see FIG. 11A), and the lower conductive barrier layer 132, the lower metal liner 134, and the lower metal layer ( 136) can be left.

Referring to FIG. 19C, a preliminary capping layer 50 is formed on the lower metal layer 136. To form the preliminary capping layer 50, a first preliminary capping layer 50A, a second preliminary capping layer 50B, and a third preliminary capping layer 50C may be sequentially formed on the lower wiring structure 130. . Although not shown in FIG. 19C, the second preliminary capping layer 50B and the third preliminary capping layer 50C are the first insulating layer 124 surrounding the lower wiring structure 130 as well as the upper surface of the lower wiring structure 130. It may be formed to cover the upper surface of the together.

The first preliminary capping layer 50A may be formed of a conductive layer. The first preliminary capping layer 50A is not formed on the exposed surfaces of the first insulating layer 124 and the lower conductive barrier layer 132, but on the exposed surfaces of the lower metal layer 136 and the lower metal liner 134. Can be formed selectively. A selective CVD process may be used to form the first preliminary capping layer 50A. In some embodiments, in the deposition process for forming the first preliminary capping layer 50A, the metal constituting the first preliminary capping layer 50A constitutes the lower metal layer 136 and the lower metal liner 134 It is deposited in a self-assembled manner only on the exposed surfaces of the lower metal film 136 and the lower metal liner 134 due to the affinity for the metal, and is thus deposited on the exposed surfaces of the lower metal film 136 and the lower metal liner 134, respectively. Only the first preliminary capping layer 50A may be selectively formed. The first preliminary capping layer 50A may be made of a metal or alloy selected from Co, Ni, Ta, Ru, W, Mn, and combinations thereof.

The second preliminary capping layer 50B may be formed of an insulating layer containing a metal. For example, the second preliminary capping layer 50B may be made of AlN, AlON, AlO, or AlOC. A CVD, ALD, or PVD process may be used to form the second preliminary capping layer 50B. In some embodiments, after forming the second preliminary capping layer 50B, a post-treatment annealing process may be performed. In an example for performing the post-treatment annealing process, the resultant product on which the second preliminary capping layer 50B is formed may be annealed _{in an N 2} gas atmosphere and then annealed in an H _{2 gas atmosphere.} In another example for performing the post-treatment annealing process, the resulting product on which the second preliminary capping layer 50B is formed _{may be annealed in an NH 3} and N ₂ mixed gas atmosphere. During the post-treatment annealing process, a plasma atmosphere may be created by applying RF power. The post-treatment annealing process may be performed for about 30 seconds under a temperature of about 360° C. and a pressure of about 2.4 torr. However, these conditions are only examples, and the technical idea of the present invention is not limited to those illustrated above. By performing the post-treatment annealing process as described above with respect to the second preliminary capping layer 50B, the second preliminary capping layer 50B for an etchant or cleaning solution that may contact the second preliminary capping layer 50B in a subsequent process ) Can improve the etch resistance.

The third preliminary capping layer 50C may be formed of an insulating layer that does not contain metal. For example, the third preliminary capping layer 50C may be made of silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), or SiOC. A CVD, ALD, or PVD process may be used to form the third preliminary capping layer 50C.

Referring to FIG. 19D, a second insulating layer 156 is formed on the preliminary capping layer 50. The second insulating layer 156 is formed to cover the upper surface of the lower wiring structure 130 and the upper surface of the second insulating layer 156 around the lower wiring structure 130 with the preliminary capping layer 50 therebetween. I can.

19D and 19E, the second insulating layer 156 is etched using the preliminary capping layer 50 as an etch stop layer, and then a part of the preliminary capping layer 50 is etched to form the lower wiring structure 130. A second hole H2 exposing the lower metal layer 136 of) and an air gap AG5 communicating with the second hole H2 are formed. As a result, a capping layer 550 composed of remaining portions of the preliminary capping layer 50 may be obtained.

The second hole H2 may be formed to penetrate the second insulating layer 156 and the capping layer 550 in a vertical direction (Z direction). In order to form the air gap AG5, a part of the preliminary capping layer 50 exposed through the second hole H2 is removed along the horizontal direction (X direction and/or Y direction) to form the second hole H2. A cut-out area 550TC communicating with may be formed. A part of the cut-out area 550TC may become the air gap AG5.

In an example for forming the second hole H2 and the air gap AG5, the second insulating layer 156 and the third preliminary capping layer 50C are dry-etched using plasma etching or a reactive ion etching (RIE) process. Can be etched. In this case, the etching rate may be reduced by the third preliminary capping layer 50C, and the second preliminary capping layer 50B including a material different from the third preliminary capping layer 50C is used as an etch end point. I can. Thereafter, after wet etching the exposed second preliminary capping layer 50B to expose the first preliminary capping layer 50A, the exposed first preliminary capping layer 50A and the inside of the second hole H2 and A part of the first preliminary capping layer 50A is selectively etched through the second hole H2 by using the difference in the etching selectivity from other films exposed from the outside, and cut into the first preliminary capping layer 50A. The out area 550TC may be formed. A wet etching process may be used to form the cutout area 550TC. In some embodiments, when the second preliminary capping layer 50B is made of an AlN film, the etching process of the second preliminary capping layer 50B for forming the second hole H2 and the formation of the cutout region 550TC are performed. The etching process of the first preliminary capping layer 50A for may be performed using the same etching solution. In this case, the etch selectivity of the first preliminary capping layer 50A may be greater than that of the second preliminary capping layer 50B with respect to the etchant. Accordingly, when etching the second preliminary capping layer 50B and the first preliminary capping layer 50A below the second preliminary capping layer 50A using the same etching solution, the first preliminary capping layer 50A is less than the etching amount of the second preliminary capping layer 50B. ) May be larger. Accordingly, after the second hole H2 is formed, the cutout region 550TC may be formed in the first preliminary capping layer 50A, and the cutout region 550TC may remain as the air gap AG5. . As an etching solution for etching the second preliminary capping layer 50B and the first preliminary capping layer 50A below the second preliminary capping layer 50B, for example, an acid solution such as sulfuric acid or hydrochloric acid may be used. In some other embodiments, when the second preliminary capping layer 50B is formed of an AlON layer, the second preliminary capping layer 50B is dry-etched to form the second hole H2 to form the first preliminary capping layer ( 50A) may be exposed, and then the exposed first preliminary capping layer 50A may be wet-etched using an acid solution such as sulfuric acid or hydrochloric acid to form the second hole H2 and the cut-out region 550TC.

Referring to FIG. 19F, an upper conductive barrier layer 162, an upper metal liner 164, and an upper metal layer 166 are sequentially formed in the second hole H2 (see FIG. 19E) to form a second hole H2. An upper wiring structure 160 filling in is formed. In some embodiments, a plating process may be performed to form the upper metal layer 166.

An exemplary method of manufacturing the integrated circuit device 500 illustrated in FIG. 5 has been described with reference to FIGS. 19A to 19F, but various modifications and changes are made therefrom to FIGS. 1A to 4 and FIGS. 6 to 18. The illustrated integrated circuit devices can be manufactured.

For example, in order to manufacture the integrated circuit devices 100 and 300 illustrated in FIGS. 1A and 3, the capping layer 150 may be formed instead of the preliminary capping layer 50 in the process described with reference to FIG. 19C. . In addition, after forming the second hole H2 as in the method described with reference to FIG. 19E, a portion of the capping layer 150 exposed through the second hole H2 is removed instead of forming the air gap AG5. Thus, the air gap AG1 may be formed by forming the cut-out region 150C. In this case, the air gap AG1 having various planar shapes illustrated in FIGS. 1B to 1E may be formed by controlling various process conditions for creating an etching atmosphere of the capping layer 150 as necessary. After that, the upper wiring structure 160 illustrated in FIGS. 1A and 3 may be formed with reference to what has been described with reference to FIG. 19F.

In order to manufacture the integrated circuit devices 200 and 400 illustrated in FIGS. 2 and 4, the capping layer 250 may be formed instead of the preliminary capping layer 50 in the process described with reference to FIG. 19C. In addition, after forming the second hole H2 as in the method described with reference to FIG. 19E, the first of the capping layers 250 exposed through the second hole H2 instead of forming the air gap AG5 The air gap AG2 may be formed by forming the cutout region 250AC by selectively partially etching the insulating capping layer 250A. After that, the upper wiring structure 160 illustrated in FIGS. 2 and 4 may be formed with reference to what has been described with reference to FIG. 19F.

In order to manufacture the integrated circuit devices 600 and 700 illustrated in FIGS. 6 and 7, processes as described with reference to FIGS. 19A to 19F may be performed. However, in the process described with reference to FIGS. 19D and 19E, the first preliminary capping layer 50A and the second preliminary capping layer 50B among the preliminary capping layers 50 exposed through the second hole H2 are added together. Can be etched. At this time, the air gap AG6 illustrated in FIG. 6 or the air gap AG7 illustrated in FIG. 7 is formed by adjusting the etch selectivity of each of the first preliminary capping layer 50A and the second preliminary capping layer 50B. Can be formed.

In order to manufacture the integrated circuit devices 800A, 800B, and 800C illustrated in FIGS. 8A to 10, processes as described with reference to FIGS. 19A to 19F may be performed. However, in order to form the upper wiring structures 860A, 860B, and 860C, processes similar to those described for the method of forming the upper wiring structure 160 are performed with reference to FIG. 19F, but if necessary, the upper conductive barrier layers 862A and 862B , 862C), the upper metal liners 864 and 864C, and the upper metal layer 866, respectively, by controlling the deposition conditions, the upper wiring structures 860A, 860B, and 860C having a desired shape may be formed.

In order to manufacture the integrated circuit device 900 illustrated in FIG. 11, a capping layer 950 including a conductive alloy capping layer 950T may be formed instead of the preliminary capping layer 50 in the process described with reference to FIG. 19C. have. In order to form the conductive alloy capping layer 950T, after forming the first preliminary capping layer 50A in the same manner as described with reference to FIG. 19C, the first preliminary capping layer 50A is formed in an H ₂ gas atmosphere, or First annealing under a mixed gas atmosphere of H ₂ gas and an inert gas such as Ar, He, Ne, and N ₂ to remove undesirably remaining natural oxide film on the exposed surface of the first preliminary capping layer 50A by reduction And heal surface damage. During the first annealing, a plasma atmosphere may be created by applying RF power. The primary annealing may be performed for about 1 second to about 1 minute under a temperature of about 300 to 400° C. and a pressure of about 1 to 20 torr. Thereafter, the first pre-annealed first preliminary capping layer 50A is subjected to secondary annealing in a gas atmosphere containing a semiconductor element, and the conductive alloy capping layer 950T containing the semiconductor element from the first preliminary capping layer 50A. Can be formed. The process of performing the secondary annealing may be performed in-situ without breaking vacuum after the primary annealing process. The semiconductor element may be at least one of Si and Ge. The gas containing the semiconductor element may include a _{silicon source such as SiH 4} , Si ₂ H ₆ , Si(CH ₃ ) ₄ , SiH ₂ Cl ₂ , and/or a germanium source such as _{GeH 4} and GeCl _4. In some embodiments, the gas atmosphere including the semiconductor element may be a mixed gas atmosphere of _{a gas including the semiconductor element and an inert gas such as Ar, He, Ne, and N 2.} Annealing in a gas atmosphere including the semiconductor element may be performed in a plasma method. The annealing in a gas atmosphere containing the semiconductor element may be performed for about 1 second to about 1 minute under a temperature of about 300 to 400° C. and a pressure of about 1 to 20 torr. In addition, instead of forming the air gap AG5 in the process described with reference to FIG. 19E, the first insulating capping layer 950A of the capping layer 950 is selectively partially removed to form the cut-out area 950AC. A gap AG9 may be formed. Thereafter, the upper wiring structure 160 may be formed with reference to what has been described with reference to FIG. 19F.

In order to manufacture the integrated circuit devices 900A, 900B, 900C, 900D, and 900E illustrated in FIGS. 12 to 16, processes as described with reference to FIGS. 19A to 19F may be performed. However, in order to form the upper wiring structures 960A, 960B, 960C, 960D, 960E, processes similar to those described for the method of forming the upper wiring structure 160 are performed with reference to FIG. 19F, but if necessary, the upper conductive barrier layer (962A, 962B, 962C, 962D, 962E), upper metal liners 964A, 964B, 964C, 964D, 964E, and upper metal film 966 by controlling the deposition conditions of each of the upper wiring structure 960A of a desired shape, 960B, 960C, 960D, 960E) can be formed.

In order to manufacture the integrated circuit device 1000A illustrated in FIG. 17, a method similar to that described above may be used for the manufacturing method of the integrated circuit device 900 illustrated in FIG. 11. However, instead of forming the capping layer 950 including the conductive alloy capping layer 950T, a capping layer 1050 including the first conductive alloy capping layer T1 and the second conductive alloy capping layer T2 is formed. Can be formed. To this end, after forming the first conductive alloy capping layer T1 on the lower metal layer 136 by the same method as the method of forming the conductive alloy capping layer 950T, the first conductive alloy capping layer among the lower metal layers 136 A second conductive alloy capping layer T2 including a semiconductor element may be further formed from a partial thickness portion from the upper surface in contact with (T1). When the lower metal layer 136 is made of Cu and the semiconductor element is Si, the second conductive alloy capping layer T2 may be made of _{an alloy containing Cu and Si, for example, CuSi or Cu 3 Si.} . When the lower metal layer 136 is made of Cu and the semiconductor element is Ge, the second conductive alloy capping layer T2 may be made of _{an alloy containing Cu and Ge, for example, CuGe or Cu 3 Ge.} . In some embodiments, in order to form the first conductive alloy capping layer T1 and the second conductive alloy capping layer T2, a temperature of about 300 to 400° C. and a temperature of about 1 to about 400° C. under a gas atmosphere including the semiconductor element It can be annealed for about 10 seconds to about 2 minutes under a pressure of 20 torr. Annealing can be performed in a plasma method.

In order to manufacture the integrated circuit device 1000B illustrated in FIG. 18, the method described above for the manufacturing method of the integrated circuit device 1000A illustrated in FIG. 17 is used, but the second contact hole ( In forming H2), the lower metal layer 136 may be exposed by etching the second conductive alloy capping layer T2. Thereafter, the upper wiring structure 160 may be formed in contact with the lower metal layer 136 by penetrating the capping layer 1050 in a similar manner as described with reference to FIG. 19F.

According to a method of manufacturing an integrated circuit device according to embodiments of the inventive concept, in a corner region defined by a top surface of a lower metal layer constituting a lower wiring structure and a sidewall of the upper wiring structure, the lower metal layer is When the capping layer covering the upper surface and the air gap whose width is limited by the upper wiring structure are formed, peeling or cracking occurs at the lower wiring structure, the upper wiring structure, the insulating films surrounding them, or the interface between each of them Edo may implement a structure in which peeling or propagation of cracks can be stopped by the air gap. Therefore, according to the method of manufacturing an integrated circuit device according to the technical idea of the present invention, an integrated circuit device capable of suppressing operation failure and a reduction in lifespan of the integrated circuit device due to peeling or propagation of cracks in a multilayer wiring structure I can.

In the above, exemplary structures of an integrated circuit device and methods of manufacturing them according to the technical idea of the present invention have been described with reference to FIGS. 1A to 19F, but the technical idea of the present invention is not limited to the above exemplified, Various modifications and changes are possible from these. For example, in the integrated circuit devices according to embodiments according to the inventive concept described with reference to FIGS. 1A to 18, the upper surface of the lower metal layer 136 is, for example, as illustrated in FIG. 2. , Having a structure covered with a capping layer including a two-layered insulating capping layer composed of a first insulating capping layer 250A and a second insulating capping layer 250B, or a similar two-layered insulating capping layer. Although the integrated circuit devices have been described, the technical idea of the present invention is not limited thereto, and a structure in which the upper surface of the lower metal layer 136 is covered with a capping layer including an insulating capping layer having at least a three-layer structure is described. You can have it.

20 to 24 are diagrams for describing integrated circuit devices according to still other embodiments according to the inventive concept. The integrated circuit devices 1100, 1200, 1300, 1400, and 1500 including an insulating capping layer having a three-layer structure will be described with reference to FIGS. 20 to 24.

Referring to FIG. 20, the integrated circuit device 1100 has substantially the same configuration as the integrated circuit device 500 illustrated in FIG. 5. However, the capping layer 1150 of the integrated circuit device 1100 further includes a third insulating capping layer 1150A covering the second insulating capping layer 250B, unlike the capping layer 550 of the integrated circuit device 500 do. That is, the capping layer 1150 includes a conductive capping layer 550T, a first insulating capping layer 550A, a second insulating capping layer 250B, and a third insulating capping layer sequentially stacked on the conductive capping layer 550T. It includes a triple insulating capping layer structure made of (1150A).

The sidewall of the third insulating capping layer 1150A may contact the upper wiring structure 160.

Similar to the first insulating capping layer 550A, the third insulating capping layer 1150A may be formed of AlN, AlON, AlO, or AlOC. The first insulating capping layer 550A and the third insulating capping layer 1150A may be formed of the same material or different materials selected from AlN, AlON, AlO, and AlOC, respectively.

Referring to FIG. 21, the integrated circuit device 1200 has substantially the same configuration as the integrated circuit device 600 illustrated in FIG. 6. However, the capping layer 1250 of the integrated circuit device 1200 further includes a third insulating capping layer 1250A covering the second insulating capping layer 250B unlike the capping layer 650 of the integrated circuit device 600 do. That is, the capping layer 1250 includes a conductive capping layer 550T, a first insulating capping layer 650A, a second insulating capping layer 250B, and a third insulating capping layer sequentially stacked on the conductive capping layer 550T. It includes a triple insulating capping layer structure made of (1250A).

The sidewall of the third insulating capping layer 1250A is spaced apart from the upper wiring structure 160, and between the sidewall of the third insulating capping layer 1250A facing the upper wiring structure 160 and the upper wiring structure 160 The air gap AG12 may be defined. The air gap AG12 may be spaced apart from the air gap AG6 with the second insulating capping layer 250B interposed therebetween, and thus the air gap AG12 and the air gap AG6 have a structure that does not communicate with each other. I can. The width of the air gap AG12 along the X direction may be equal to or smaller than the upper width W6B of the air gap AG6 (see FIG. 6 ).

Similar to the first insulating capping layer 650A, the third insulating capping layer 1250A may be formed of AlN, AlON, AlO, or AlOC. The first insulating capping layer 650A and the third insulating capping layer 1250A may be formed of the same material or different materials selected from AlN, AlON, AlO, and AlOC, respectively. In some embodiments, the first insulating capping layer 650A may be formed of AlN, and the third insulating capping layer 1250A may be formed of any one of AlON, AlO, and AlOC. In this case, the width of the air gap AG12 along the X direction may be smaller than the upper width W6B of the air gap AG6 (see FIG. 6 ). In some other embodiments, when the first insulating capping layer 650A and the third insulating capping layer 1250A are made of the same material, the width of the air gap AG12 along the X direction is It may be approximately the same as the upper width W6B (see Fig. 6).

Referring to FIG. 22, the integrated circuit device 1300 has substantially the same configuration as the integrated circuit device 900 illustrated in FIG. 11. However, the capping layer 1350 of the integrated circuit device 1300 further includes a third insulating capping layer 1250A covering the second insulating capping layer 250B, unlike the capping layer 950 of the integrated circuit device 900 do. That is, the capping layer 1350 includes a conductive alloy capping layer 950T, a first insulating capping layer 950A sequentially stacked on the conductive alloy capping layer 950T, a second insulating capping layer 250B, and a third insulating property. It includes a triple insulating capping layer structure made of the capping layer 1250A.

The sidewall of the third insulating capping layer 1250A is spaced apart from the upper wiring structure 160, and between the sidewall of the third insulating capping layer 1250A facing the upper wiring structure 160 and the upper wiring structure 160 The air gap AG12 may be defined. A more detailed description of the third insulating capping layer 1250A is substantially the same as described with reference to FIG. 21.

The integrated circuit devices 1100, 1200, and 1300 including the capping layers 1150, 1250, and 1350 further including the third insulating capping layers 1150A and 1250A have been described with reference to FIGS. 20 to 22. The technical idea of the invention is not limited to those illustrated in FIGS. 20 to 22, and various modifications and changes are possible. For example, the capping layer 150 illustrated in FIG. 1A, the capping layer 250 illustrated in FIG. 2, the capping layer 250 illustrated in FIG. 4, the capping layer 750 illustrated in FIG. 7, and FIG. The capping layer 1050 illustrated in FIG. 17 is a third insulating capping layer 1150A, a third insulating capping layer 1250A, or a third insulating cap of various structures modified from these within the scope of the technical idea of the present invention. It may further include a ping layer.

Referring to FIG. 23, the integrated circuit device 1400 has substantially the same configuration as the integrated circuit device 600 illustrated in FIG. 6. However, the capping layer 1450 of the integrated circuit device 1400 further includes a third insulating capping layer 1450A covering the second insulating capping layer 250B, unlike the capping layer 650 of the integrated circuit device 600 And does not include the conductive capping layer 550T. That is, the capping layer 1450 is a triple insulating consisting of a first insulating capping layer 650A, a second insulating capping layer 250B, and a third insulating capping layer 1450A sequentially stacked on the lower metal layer 136. It includes a capping layer structure. The lower metal layer 136 and the first insulating capping layer 650A may be in direct contact, and in this case, the lower metal layer 136 may be formed of Co.

Among the first insulating capping layers 650A, an air gap AG14 is disposed between the sidewall facing the upper wiring structure 160 and the upper wiring structure 160, and the height of the air gap AG14 in the Z direction is a lower metal layer. It may be defined by an upper surface of 136 and a lower surface of the second insulating capping layer 250B.

The sidewall of the third insulating capping layer 1450A may contact the upper wiring structure 160.

A more detailed configuration of the third insulating capping layer 1450A is substantially the same as described for the third insulating capping layer 1150A with reference to FIG. 20.

Referring to FIG. 24, the integrated circuit device 1500 has substantially the same configuration as the integrated circuit device 900 illustrated in FIG. 11. However, the capping layer 1550 of the integrated circuit device 1500 further includes a third insulating capping layer 1550A covering the second insulating capping layer 250B, unlike the capping layer 950 of the integrated circuit device 900 And does not include the conductive alloy capping layer 950T. That is, the capping layer 1550 is a triple insulating consisting of a first insulating capping layer 950A, a second insulating capping layer 250B, and a third insulating capping layer 1550A sequentially stacked on the lower metal layer 136. It includes a capping layer structure. The lower metal layer 136 and the first insulating capping layer 950A may be in direct contact, and in this case, the lower metal layer 136 may be formed of Co.

Among the first insulating capping layers 950A, an air gap AG9 is disposed between the sidewall facing the upper wiring structure 160 and the upper wiring structure 160, and the height of the air gap AG9 in the Z direction is a lower metal layer. It may be defined by an upper surface of 136 and a lower surface of the second insulating capping layer 250B.

The sidewall of the third insulating capping layer 1550A is spaced apart from the upper wiring structure 160, and between the sidewall of the third insulating capping layer 1550A facing the upper wiring structure 160 and the upper wiring structure 160 The air gap AG15 may be defined. The height of the air gap AG15 in the Z direction may be limited by the top surface of the second insulating capping layer 250B and the bottom surface of the second insulating layer 156. A more detailed configuration of the third insulating capping layer 1550A is substantially the same as described for the third insulating capping layer 1150A with reference to FIG. 20.

With reference to FIGS. 23 and 24, the integrated circuit devices 1400 and 1500 including the capping layers 1450 and 1550 including the insulating capping layer having a three-layer structure without including the conductive capping layer have been described. The technical idea of the invention is not limited to those illustrated in FIGS. 23 and 24, and various modifications and changes are possible. For example, the capping layer 150 illustrated in FIG. 1A, the capping layer 250 illustrated in FIG. 2, the capping layer 250 illustrated in FIG. 4, the capping layer 550 illustrated in FIG. 5, and FIG. 7 The capping layer 750 illustrated in and the capping layer 1050 illustrated in FIG. 17 are respectively a third insulating capping layer 1450A, a third insulating capping layer 1550A, or the scope of the technical idea of the present invention from these. A third insulating capping layer having various structures modified within may be further included.

The integrated circuit devices 1100, 1200, 1300, 1400, and 1500 described with reference to FIGS. 20 to 24 are each of the upper surface of the lower metal layer 136 and the upper wiring structure 160 constituting the lower wiring structure 130. And air gaps AG5, AG9, AG12, AG14, AG15 formed in the corner regions defined by the side walls. Therefore, even when peeling or cracking occurs at the lower wiring structure 130, the upper wiring structure 160, the insulating films surrounding them, or the interface between each of them, the peeling or cracking may cause air gaps (AG5, AG9, AG12). , AG14, AG15), peeling or crack propagation may be stopped in the air gap (AG5, AG9, AG12, AG14, AG15). Accordingly, even if peeling or cracking occurs in the multilayer wiring structure of the integrated circuit devices 1100, 1200, 1300, 1400, 1500 according to the embodiments of the present invention, the operation of the integrated circuit device by suppressing the propagation It is possible to prevent the occurrence of defects and deterioration of life, and improve the reliability of the integrated circuit device.

Those skilled in the art refer to FIGS. 20 to 24 using an exemplary manufacturing method of the integrated circuit device 500 described with reference to FIGS. 19A to 19F and various modified and modified methods within the scope of the technical idea of the present invention. It will be appreciated that the illustrated integrated circuit devices 1100, 1200, 1300, 1400, and 1500 can be manufactured.

25A and 25B are views for explaining an integrated circuit device according to still other embodiments according to the technical idea of the present invention, and FIG. 25A is a layout diagram showing a main configuration of the integrated circuit device 2000, and FIG. 25B is a cross-sectional view taken along line B-B' of FIG. 25A. The integrated circuit device 2000 illustrated in FIGS. 25A and 25B may constitute a logic cell including a fin field effect transistor (FinFET) device.

Referring to FIGS. 25A and 25B, the logic cell region LC of the substrate 110 includes a first device region RX1 and a second device region RX2. A plurality of fin-type active regions AC protruding from the substrate 110 are formed in the first device region RX1 and the second device region RX2. The plurality of fin-type active regions AC may extend parallel to each other in one direction (X direction). A device isolation layer (not shown) is formed between each of the plurality of fin-type active regions AC on the substrate 110, and the plurality of fin-type active regions AC may protrude above the device isolation layer in a fin shape. . A plurality of gate insulating layers 1118 and a plurality of gate lines GL may extend on the substrate 110 in a direction (Y direction) crossing the plurality of fin-type active regions AC. The plurality of gate insulating layers 1118 and the plurality of gate lines GL may extend while covering an upper surface and both sidewalls of each of the plurality of fin-type active regions AC and an upper surface of the device isolation layer. A plurality of MOS transistors may be formed along the plurality of gate lines GL. The plurality of MOS transistors may be MOS transistors having a three-dimensional structure in which channels are formed on top and sidewalls of the plurality of fin-type active regions AC, respectively. The plurality of gate insulating layers 1118 may be formed of a silicon oxide layer, a high dielectric layer, or a combination thereof. The high dielectric layer may be formed of a metal oxide having a higher dielectric constant than that of the silicon oxide layer. Each of the plurality of gate lines GL may include a work function metal-containing layer and a gap-fill metal layer. The work function metal-containing layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The gap-fill metal layer may be formed of a W layer or an Al layer. In some embodiments, each of the plurality of gate lines GL is a stacked structure of TiAlC/TiN/W, a stacked structure of TiN/TaN/TiAlC/TiN/W, or a stacked structure of TiN/TaN/TiN/TiAlC/TiN/W. It may include a laminated structure.

The first level LV1 above the plurality of fin-type active regions AC includes a plurality of first contacts CA connected to the source/drain regions 1116 among the plurality of fin-type active regions AC, and a plurality of gate lines. A plurality of second contacts CB connected to GL are formed. The plurality of first and second contacts CA and CB may be insulated from each other by the first interlayer insulating layer 1132 covering the plurality of fin-type active regions AC and the gate line GL.

A second interlayer insulating layer 1134 and a plurality of lower via contacts V0 penetrating the second interlayer insulating layer 1134 are formed on the first interlayer insulating layer 1132.

A plurality of first wiring layers M1 extending in a horizontal direction at a second level LV2 higher than the first level LV1 may be formed on the second interlayer insulating layer 1134. The plurality of first wiring layers M1 may extend on the second interlayer insulating layer 1134 in parallel with the extending direction of the main surface 110A of the substrate 110. Each of the plurality of first wiring layers M1 is a plurality of first and second contacts through any one of the plurality of lower via contacts V0 formed between the first level LV1 and the second level LV2, respectively. CA, CB) can be connected to any one selected from. Each of the plurality of lower via contacts V0 may pass through the second interlayer insulating layer 1134 and may be connected to any one of the plurality of first and second contacts CA and CB. The plurality of lower via contacts V0 may be insulated from each other by the second interlayer insulating layer 1134.

In the logic cell area LC, the power line VDD is connected to the active area AC in the first device area RX1, and the ground line VSS is connected to the active area AC in the second device area RX2. Can be connected. The power line VDD and the ground line VSS are connected to the active area AC of the first device area RX1 and the active area AC of the second device area RX2 through any one of the plurality of lower via contacts V0. ) Can be connected to each. The plurality of first wiring layers M1, the power line VDD, and the ground line VSS may be insulated from each other by the third interlayer insulating layer 1136.

The plurality of lower via contacts V0, the plurality of first wiring layers M1, the power line VDD, and the ground line VSS may each have a stacked structure of a conductive barrier layer and a metal layer. The conductive barrier layer and the metal layer may have the same configuration as described for the lower conductive barrier layer 132 and the lower metal layer 136 constituting the lower wiring structure 130 with reference to FIG. 1A.

A fourth interlayer insulating layer 1138 covering the third interlayer insulating layer 1136 and the plurality of first wiring layers M1 may be formed. In some embodiments, the first to fourth interlayer insulating layers 1132, 1134, 1136, and 1138 may be made of the same material, or at least some of them may be made of different materials. Details of the constituent materials of the first to fourth interlayer insulating layers 1132, 1134, 1136, and 1138 are as described for the lower insulating layer 114 with reference to FIG. 1A.

A plurality of upper via contacts V1 penetrating the fourth interlayer insulating layer 1138 may be formed on the plurality of first wiring layers M1. A plurality of second wiring layers M2 extending in a direction crossing the plurality of first wiring layers M1 at a third level LV3 higher than the second level LV2 may be formed on the upper via contact V1. . The plurality of second wiring layers M2 are formed between the second level LV2 and the third level LV3, respectively, through one of the plurality of upper via contacts V1. It may be connected to any one of the first wiring layers M1. The plurality of upper via contacts V1 may penetrate through the fourth interlayer insulating layer 1138 and extend to any one first wiring layer M1 among the plurality of first wiring layers M1. The plurality of upper via contacts V1 and the plurality of second wiring layers M2 may each have a stacked structure of a conductive barrier layer and a metal layer. The conductive barrier layer and the metal layer may have the same configuration as described for the upper conductive barrier layer 162 and the upper metal layer 166 constituting the upper wiring structure 160 with reference to FIG. 1A.

A capping layer 150 extending to cover the top surface of the first wiring layer M1 and the top surface of the third interlayer insulating layer 1136 is interposed between the first wiring layer M1 and the fourth interlayer insulating layer 1138 . An air gap AG1 is formed between the first wiring layer M1 and the fourth interlayer insulating layer 1138. The air gap AG1 may be formed in a corner region defined by an upper surface of the first wiring layer M1 and a sidewall of the upper via contact V1. The width of the air gap AG1 may be limited by the capping layer 150 and the upper via contact V1. A more detailed configuration of the capping layer 150 and the air gap AG1 is as described with reference to FIG. 1A. 25B illustrates a case in which the air gap AG1 is formed on the first wiring layer M1 connected to the first contact CA, but also on the first wiring layer M1 connected to the second contact CB is also shown in FIG. 25B. Similar to the illustrated example, the air gap AG1 may be formed.

25A and 25B, in the integrated circuit device 2000, in the corner region defined by the top surface of the first wiring layer M1 constituting the lower wiring structure and the sidewall of the upper via contact V1 constituting the upper wiring structure. An air gap AG1 is formed. Therefore, even when peeling or cracking occurs at a plurality of first wiring layers M1, a plurality of upper via contacts V1, a plurality of second wiring layers M2, insulating films surrounding them, or an interface between each of them. Peeling or propagation of cracks may be stopped by the air gap AG1. Accordingly, reliability can be improved by suppressing operation failure due to the propagation of peeling or cracks in the multilayer wiring structure included in the integrated circuit device 2000 and reduction in lifespan.

The case in which the capping layer 150 and the air gap AG1 illustrated in FIG. 1A are formed in the integrated circuit device 2000 illustrated in FIGS. 25A and 25B is illustrated, but the technical idea of the present invention is not limited thereto, and FIG. Capping layers and air gaps having various configurations described with reference to FIGS. 1A to 18 and FIGS. 20 to 24 may be employed.

Above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those of ordinary skill in the art within the spirit and scope of the present invention This is possible.

130: lower wiring structure, 136: lower metal film, 150, 250, 550, 650, 750, 950, 1050: capping layer, 160, 860A, 860B, 860C, 960A, 960B, 960C, 960D, 960E: upper wiring structure , 1150A, 1250A, 1450A, 1550A: third insulating capping layer, AG1, AG2, AG5, AG6, AG7, AG9, AG12, AG14, AG15: air gap.

Claims (20)

A lower wiring structure including a lower metal film penetrating at least a portion of the first insulating film formed on the substrate,
A capping layer covering an upper surface of the lower metal film,
A second insulating layer covering the capping layer,
An upper wiring structure connected to the lower metal layer through the second insulating layer and the capping layer,
An air gap disposed between the lower metal layer and the second insulating layer and having a width defined by a distance between the capping layer and the upper wiring structure,
The air gap is interposed between the upper wiring structure and the capping layer, and the upper wiring structure does not contact the capping layer. The method of claim 1,
The air gap is disposed in a corner region defined by an upper surface of the lower metal layer and a sidewall of the upper wiring structure. The method of claim 1,
The air gap surrounds at least a portion of the upper wiring structure at a position vertically overlapping the lower metal layer. The method of claim 1,
The capping layer includes a conductive capping layer, a first insulating capping layer containing a metal, and a second insulating capping layer not containing the metal and other metals,
The conductive capping layer, the first insulating capping layer, and the second insulating capping layer are sequentially stacked,
The air gap is interposed between the conductive capping layer and the upper wiring structure. The method of claim 4,
A first sidewall of the conductive capping layer facing the upper wiring structure and a second sidewall of the first insulating capping layer facing the upper wiring structure each include a portion spaced apart from the upper wiring structure,
The air gap is interposed between the first sidewall of the conductive capping layer and the upper wiring structure, and between the second sidewall of the first insulating capping layer and the upper wiring structure. The method of claim 4,
The air gap has a first width in a first direction between the conductive capping layer and the upper wiring structure, and the air gap has a first width in the first direction between the first insulating capping layer and the upper wiring structure. An integrated circuit device having a second width different from the first width. The method of claim 4,
The air gap is an integrated circuit device between the lower metal layer and the second insulating capping layer. The method of claim 1,
The capping layer includes a first conductive alloy capping layer including a first metal and a semiconductor element, a first insulating capping layer including a second metal different from the first metal, and the first metal, the second metal, and Including a second insulating capping layer that does not contain other metals,
The first conductive alloy capping layer, the first insulating capping layer, and the second insulating capping layer are sequentially stacked,
The air gap is an integrated circuit device between the first conductive alloy capping layer and the second insulating capping layer. The method of claim 8,
The capping layer further includes a second conductive alloy capping layer interposed between the lower metal film and the first conductive alloy capping layer,
The second conductive alloy capping layer includes a third metal different from the first metal and the semiconductor element. The method of claim 1,
The capping layer includes a conductive capping layer and an insulating capping layer having a three-layer structure covering the conductive capping layer,
The three-layered insulating capping layer includes a first insulating capping layer containing a metal, a second insulating capping layer not containing the metal and other metals, and a third insulating capping layer containing the metal or other metal. and,
The first insulating capping layer, the second insulating capping layer, and the third insulating capping layer are sequentially stacked. delete delete delete delete delete delete delete delete delete delete

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