KR102244871B1 - The Voltage/Frequency droop parallel operation inverter duplication apparatus, and the method thereof - Google Patents

Abstract

The present invention discloses a voltage/frequency (V/F) droop parallel operation inverter duplication apparatus and a method thereof that can eliminate the deviation between the active power and the reactive power of each inverter by equally adjusting the load sharing ratio between two or more inverters connected in parallel, and suppress the circulating current that is generated due to the power deviation between the inverters. According to a V/F droop parallel operation inverter duplication apparatus and method of the present invention, when at least one (m) of the first inverter to the N^th inverter is not operated, the output voltage frequency of the inverter is lowered to lower the increased active power when the active power of the inverter is increased, such that the remaining inverters except the non-operated inverters (N-m) can operate by evenly distributing power. In addition, when the reactive power of the inverter increases, the output voltage of the inverter is lowered to lower the increased reactive power, such that the load of two or more inverters connected in parallel is equally controlled.

Description

V／F droop parallel operation inverter duplication apparatus and method {The Voltage/Frequency droop parallel operation inverter duplication apparatus, and the method thereof}

The present invention relates to a V/F droop parallel operation inverter redundancy apparatus and method, and more particularly, when at least one of the first to the Nth inverters (m) is not operated, inverters that do not operate. Except (Nm), the remaining inverters distribute power evenly to equally adjust the load sharing ratio between two or more inverters connected in parallel, thereby eliminating the deviation between active power and reactive power of each inverter, and caused by power deviation between inverters. The present invention relates to a V/F droop parallel operation inverter redundancy apparatus and method to suppress possible circulating currents.

As technology advances, electricity generated from various types of energy sources is connected to the grid to supply power. In this case, an inverter that converts DC power supplied from each DC source into AC power and supplies it to the load is used.

Depending on the purpose of use, the inverter may be used in an independent form, or two or more inverters may be connected in parallel and used. In the method of connecting two or more inverters in parallel, the power conversion capacity can be adjusted by adding, changing, or removing inverters as needed, and when an inverter fails, the faulty inverter can be replaced to normalize the power system. .

However, when two or more inverters are connected in parallel, wired signals are exchanged between a plurality of inverters using wired communication, and power of each inverter is compensated.

However, when a wired signal cannot be received due to an error in wired communication, power compensation of each inverter may not be performed and power supply operation may not be maintained.

In addition, when two or more inverters are connected in parallel, there may be variations in the characteristics of the components of the inverter for each inverter, the impedance of the power line affected by the load characteristics, and the difference in the temperature change characteristics of each component. There is a problem in that each inverter cannot equally share the active power and reactive power supplied to the load on a one-to-one basis.

In this case, when a deviation between the active power and the reactive power occurs between the inverters, a circulating current is generated between the inverters, and there is a problem in that an overcurrent may be generated from the inverter due to this circulating current.

V/F (Voltage/Frequency) droop-based inverter parallel operation was developed to minimize the difference between active and reactive power between two or more inverters connected in parallel. This V/F droop-based inverter parallel operation is a method that allows parallel operation without wired communication without power information exchange between parallel connected inverters by compensating for active power and reactive power using only the voltage and current values calculated from the load side.

However, in the conventional V/F droop-based inverter parallel operation, if the voltage value and current value calculated from the load side are used as they are to compensate for the deviation between the active power and the reactive power of each inverter, the active power and the reactive power of each inverter are There is a problem in that the parallel operation state of the inverter is unstable because it takes a long time from the time the deviation occurs until the deviation between the active power and the reactive power is compensated.

As a related prior patent document, there is Korean Patent Publication No. 10-1639825 (registered on July 8, 2016), and a current control device of an inverter is described in the document.

The object of the present invention is to minimize power deviation in a normal state of wired communication by compensating for a power deviation value with a wired signal through V/F droop control and redundant parallel operation in order to minimize the power deviation between each inverter. It is to provide a V/F droop parallel operation inverter redundancy device and method that enables continuous maintenance of parallel operation by V/F droop control in case of an error.

In addition, an object of the present invention is that when at least one (m) of the No. 1 inverter to the No. N inverter is not operated, except for the non-operating inverters (Nm), the remaining inverters uniformly distribute power to parallel V/F, which eliminates the deviation between active power and reactive power of each inverter by equally adjusting the load sharing ratio between two or more inverters connected to each other, and suppresses circulating current that may be caused by power deviation between inverters. It is to provide a droop parallel operation inverter redundancy apparatus and method.

A V/F droop parallel operation inverter redundancy apparatus according to an embodiment of the present invention for achieving the above object is a V/F droop parallel operation inverter redundancy apparatus in which two or more inverters are connected in parallel, and provides an applied DC power supply. It converts to AC power, filters the PWM pulse signal of the AC power, converts it into a sine wave form and supplies it to the load, and applies a three-phase bypass voltage (VBYP), an inverter current (IID), and a three-phase load current from the bypass line. (ILD) and three-phase load voltage (VLD) are converted into DQ synchronous coordinate values, and the three-phase load current (ILD) and the three-phase load voltage (VLD) for the DQ synchronous coordinate values are converted into QD coordinate values, and A first unit inverter for compensating to calculate an active power reference value (Pref) and a reactive power reference value (Qref) to output to the second unit inverter; Using the active power reference value (Pref) and reactive power reference value (Qref) applied from the first unit inverter as a relative active power reference value (Pm) and a relative reactive power reference value (Qm), respectively, the relative active power reference value (Pm) and The effective power droop reference signal (PdrpRef) is a value obtained by proportionally integrating (Kp+Ki/s) the difference between the active power reference value (Pref) and applying the active power droop coefficient (Kpdrp) to the difference between the active power reference value. And the reactive power droop at the difference between the relative reactive power reference value (Qm) and the reactive power reference value (Qm) proportionally integrated (Kp+Ki/s) and the reactive power reference value (Qref). The value to which the coefficient (Kqdrp) is applied is generated as a reactive power droop reference signal (QdrpRef) to control the output voltage frequency, output voltage and output current, and the active power reference value (Pref) and the reactive power reference value (Qref) are as follows. A second unit inverter outputting to the unit unit inverter; And the active power reference value (Pref) and the reactive power reference value (Qref) applied from the N-1th inverter as the relative active power reference value (Pm) and the relative reactive power reference value (Qm), respectively, and the relative active power reference value (Pm). ) And the difference between the active power reference value (Pref) and the active power reference value (Pref) are proportionally integrated (Kp+Ki/s), and the active power droop factor (Kpdrp) is applied to the difference between the active power reference value and the active power droop reference signal ( PdrpRef), and the difference between the relative reactive power reference value (Qm) and its reactive power reference value (Qm) is proportionally integrated (Kp+Ki/s) and the difference between the reactive power reference value (Qref) is invalid. Including, The first to the first inverter to the unit N inverter for controlling the output voltage frequency, output voltage and output current by generating a value to which the power droop coefficient (Kqdrp) is applied as a reactive power droop reference signal (QdrpRef) When at least one of the Nth inverters (m) is not operated, the remaining inverters excluding the non-operated inverters (Nm) may be uniformly distributed and operated.

The first to the Nth inverters may be calculated for power deviation compensation (Perr, Qerr) according to the following equation.

Here, Perr represents the active power deviation compensation value, Pref (Pm) represents the master active power, Pref represents the active power, Qerr represents the reactive power deviation compensation value, and Qref (Qm) represents the master reactive power. , Qref represents reactive power.

At least one inverter of the first to the Nth inverter converts the applied DC power into AC power, filters the PWM pulse signal of the AC power, converts it into a sine wave form, and supplies it to a load, An inverter stage for receiving 3-phase AC power from a bypass line and supplying it to the load when the inverter fails; And a three-phase bypass voltage (VBYP) applied from the bypass line, an inverter current (IID) detected from the inverter stage, a three-phase load current (ILD), and a three-phase load voltage (VLD) as DQ synchronization coordinate values. And converts the three-phase load current (ILD) and the three-phase load voltage (VLD) with respect to the DQ synchronous coordinate value to a QD coordinate value and compensates for the active power reference value (Pref) and the reactive power reference value (Qref). Calculated and proportionally integrated (Kp+Ki/s) the difference between the active power reference value (Pref) and the active power reference value (Pm) of another inverter and the active power droop coefficient (Kpdrp) The applied value is generated as an active power droop reference signal (PdrpRef), and the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of another inverter is proportionally integrated (Kp+Ki/s) and the invalidity Includes an inverter controller that generates a value obtained by applying a reactive power droop coefficient (Kqdrp) to the difference value of the power reference value (Qref) as a reactive power droop reference signal (QdrpRef), and controls the output voltage frequency, output voltage, and current of the inverter. can do.

In addition, the inverter stage may include an IGBT power converter 3 for converting DC power applied to the inverter into AC power and outputting an inverter current according to a PWM pulse signal; An LC filter unit 5 filtering the PWM pulse signal output from the IGBT power conversion unit 3 and converting it into a sine wave form; An inverter switch (1) connected to the output terminal of the LC filter unit (5) to switch the filtered inverter current to flow to a load; And a bypass switch 4 connected to the output terminal of the inverter switch 1 to switch the three-phase AC power input from the bypass line 6 to be supplied to the load side.

In addition, the inverter control unit includes an inverter current (IID) output from the IGBT power conversion unit (3), a three-phase load voltage (VLD) and a three-phase load current (ILD) output from the LC filter unit (5). In addition, the three-phase bypass voltage VBYP applied from the bypass line 6 is applied to the synchronization signal ThetaByp provided from the synchronization signal generator 7 and the drop applied synchronization signal ThetaLd2 provided from the frequency control unit 17. DQ conversion unit 9 for outputting a DQ synchronous coordinate conversion signal (Vlqs, Vlds, Vlqe, Vlde, Ilqs Ilds, Ilqe Ilde, Iiqs Iids, Iiqe Iide, Vbqe) by performing DQ conversion; A synchronization signal generator (7) that generates a DQ synchronization coordinate conversion signal (Vbqe) of the three-phase bypass voltage converted by the DQ conversion unit (9) and a three-phase bypass voltage synchronization signal (ThetaByp, ThetaLd) in phase ; A first Q-axis error calculator that calculates an error between the reactive power droop reference signal (QdrpRef) and the Q-axis voltage reference signal (Vref(q axis)) and outputs a synchronous Q-axis inverter reference voltage (Vref(Viqe)) signal (14);

By receiving the synchronous Q-axis inverter reference voltage (Vref(Viqe)) signal and the synchronous D-axis inverter reference voltage (0 (Vide)) signal, the DQ synchronous coordinate conversion signal (Vlqs, Vlds, Vlqe, Vlde, Ilqs Ilds, An inverter voltage current controller 15 for controlling a load voltage and a load current of the inverter according to Ilqe Ilde) to output a Q-axis voltage control signal Vqref and a D-axis voltage control signal Vdref; The inverter voltage and current control unit 15 receives the Q-axis voltage control signal Vqref and the D-axis voltage control signal Vdref, converts it into a three-phase signal according to the control signal of the frequency control unit 17, A DQ inverse transform unit 13 for outputting a command signal for adjusting an output voltage and a frequency; Converts the command signal output from the DQ inverse conversion unit 13 into a space vector pulse width modulation signal (SV PWM) for switching the IGBT (Insulated Gate Bipolar Transistor) of the IGBT power conversion unit 3 SV PWM conversion unit 19; The phase angle of the three-phase load current input from the DQ converter 9 is compensated by using the current phase angle compensation value provided from the parameter stored in the memory, and the phase angle is compensated for the three-phase load current and the DQ converter ( 9) The new active power reference value (Pref) and the reactive power reference value (Qref) are calculated using the three-phase load voltage input from 9), and the active power reference value (Pref) is used when the active power of the inverter is increased. In order to lower the voltage frequency output from the inverter, the difference between the active power reference value (Pref) and the active power reference value (Pm) of another inverter is proportionally integrated (Kp+Ki/s) and the difference between the active power reference value. In order to generate a value to which the droop coefficient (Kpdrp) is applied as an active power droop reference signal (PdrpRef), and to lower the voltage output from the inverter by using the reactive power reference value when the reactive power of the inverter is increased, the reactive power The difference between the reference value (Qref) and the reactive power reference value (Qm) of other inverters is proportionally integrated (Kp+Ki/s) and the value obtained by applying the droop factor (Kqdrp) to the difference between the reactive power reference value (Qref) and the value is invalid. A voltage/frequency (V/F) parallel droop control unit 11 that generates a power droop reference signal QdrpRef; And the active power droop reference signal (PdrpRef) is subtracted from the three-phase bypass voltage synchronization signal (ThetaLd) in phase with the DQ synchronization coordinate conversion signal (Vbqe) output from the synchronization signal generator (7) to synchronize the droop application. A frequency control unit 17 that outputs the signal ThetaLd2 to the DQ inverse transform unit 13 may be included.

In addition, the V/F parallel droop control unit receives DQ synchronization coordinate conversion signals (Vlqe, Vlde, Ilqe Ilde) for the three-phase load voltage and three-phase load current from the DQ conversion unit 9 and supplies them to the load. A PQ conversion unit 21 that calculates a value of the active power P and the reactive power Q. To create a parallel droop control signal, the phase angle of the three-phase load current input from the DQ converter 9 is compensated using the current phase angle compensation value provided from the parameter stored in the memory, and the phase angle is compensated. A phase error compensating unit 23 for calculating a new active power reference signal Pref and the reactive power reference signal Qref using a three-phase load current and a three-phase load voltage transmitted from the DQ converter 9; And the difference between the active power reference value Pref and the active power reference value Pm of another inverter in order to lower the voltage frequency output from the inverter by using the active power reference value Pref when the active power of the inverter is increased. A value obtained by applying a droop factor (Kpdrp) to the difference between the proportional integral (Kp+Ki/s) of the active power reference value and the active power reference value is generated as an active power droop reference signal (PdrpRef), and the reactive power of the inverter is increased. In order to lower the voltage output from the inverter by using the reactive power reference value, the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of another inverter is proportionally integrated (Kp+Ki/s) A droop signal generator 25 for generating a value obtained by applying a droop coefficient Kqdrp to the difference value of the reactive power reference value Qref as a reactive power droop reference signal QdrpRef.

The droop signal generator 25 may include a second error calculator 31 for calculating an error between the active power reference value Pref and the active power reference value Pm of another inverter; A first-order proportional integrator (32) for first-order proportional integration (Kp+Ki/s) of the value output from the second error calculator (31); A third error calculator (33) calculating an error between the first proportional integral value and the active power reference value (Pref); An active power droop applying unit 34 for generating an active power droop reference signal PdrpRef by applying an active power droop coefficient Kpdrp to the value output from the third error calculator 33; A fourth error calculator 35 for calculating an error between the reactive power reference value Qref and the reactive power reference value Qm of another inverter; A second-order proportional integrator 36 for second-order proportional integration (Kp+Ki/s) of the value output from the fourth error calculator (35); A fifth error calculator (37) calculating an error between the second-order proportional integration value and the reactive power reference value (Qref); And a reactive power droop application unit 38 for generating a reactive power droop reference signal QdrpRef by applying a reactive power droop coefficient Kqdrp to the value output from the fifth error calculator 37.

In addition, the inverter voltage and current control unit 15 converts the synchronous axis coordinates of the synchronous Q-axis inverter reference voltage (Vref(Viqe)) and the synchronous D-axis inverter reference voltage (0(Vide)) into stationary axis coordinates. A first coordinate axis conversion unit 41 outputting the Q-axis load reference voltage Vlqs_ref and the D-axis load reference voltage Vlds_ref; A sixth error calculator 42 for calculating an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs; A Q-axis fundamental wave compensator 43 for compensating a Q-axis fundamental wave by controlling the error signal output from the sixth error calculator 42 by proportional resonance (PR) control; A seventh error calculator 44 for calculating an error between the Q-axis stationary axis inverter voltage Vlqs and a reference level voltage 0; A fifth harmonic compensator 1 (45) for compensating the fifth harmonic by controlling the error signal output from the seventh error calculator 44 by proportional resonance (PR) control; An eighth error calculator (46) calculating an error between the stationary axis inverter voltage (Vlqs) and a reference level voltage (0); A seventh harmonic compensator 1 47 for compensating for a seventh harmonic by controlling the error signal output from the eighth error calculator 46 by proportional resonance (PR) control; A ninth adder (48) for first adding the 5th harmonic-compensated value output from the 5th harmonic compensator 1 (45) and the 7th harmonic compensation value output from the 7th harmonic compensator 1 (47) ; The first-order added value output from the ninth adder 48, the first-order fundamental wave compensated value output from the first-order fundamental wave compensator 43, and the Q-axis load current value (IIqs) are all A tenth adder 49 for secondary addition; An eleventh adder (50) for thirdly adding the second-added value output from the tenth adder (49) and a Q-axis inverter current value (Iiqs); A twelfth error calculator 51 for calculating an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds; A D-axis fundamental wave compensator 52 for compensating the D-axis fundamental wave by controlling the error signal output from the twelfth error calculator 51 by proportional resonance (PR) control; A thirteenth error calculator (53) calculating an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0); A fifth harmonic compensator 2 (54) for compensating the fifth harmonic by controlling the error signal output from the thirteenth error calculator (53) by proportional resonance (PR) control; A 14th error calculator (55) for calculating an error between the D-axis stationary axis inverter voltage (Vlqs) and a reference level voltage (0); A 7th harmonic compensator 2 (56) for compensating the 7th harmonic by controlling the error signal output from the 14th error calculator (55) by proportional resonance (PR) control; A fifteenth adder (57) for adding the fifth harmonic-compensated value output from the fifth harmonic compensator 2 (54) and the seventh harmonic-compensated value output from the seventh harmonic compensator 2 (56) by a fourth order ; The fourth-order added value output from the fifteenth adder 57, the D-axis fundamental wave compensated value output from the D-axis fundamental wave compensator 52, and the D-axis load current value (IIds) are all A sixteenth adder 58 to add the fifth order; A seventeenth adder (59) for adding the fifth-order added value output from the sixteenth adder (58) and the D-axis inverter current value (Iids) by a sixth order; A second coordinate axis transformation for converting stationary axis coordinates of the third-added signal output from the eleventh adder (50) and the sixth-added signal output from the seventeenth adder (59) into synchronous axis coordinates Part 60; A Q-axis current controller 61 for outputting a Q-axis voltage control signal Vqref by controlling the current in a proportional integration (Kp+Ki/s) method of the Q-axis signal output from the second coordinate-axis conversion unit 60; And a D-axis current controller 62 for outputting a D-axis voltage control signal Vdref by controlling the current in a proportional integration (Kp+Ki/s) method of the D-axis signal output from the second coordinate axis converter 60. It may include.

In addition, the inverter voltage and current control unit 15 converts the synchronous axis coordinates of the synchronous Q-axis inverter reference voltage (Vref(Viqe)) and the synchronous D-axis inverter reference voltage (0(Vide)) into stationary axis coordinates. A first coordinate axis conversion unit 41 outputting the Q-axis load reference voltage Vlqs_ref and the D-axis load reference voltage Vlds_ref; A sixth error calculator 42 for calculating an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs; A Q-axis fundamental wave compensator 43 for compensating a Q-axis fundamental wave by controlling the error signal output from the sixth error calculator 42 by proportional resonance (PR) control; A seventh error calculator 44 for calculating an error between the Q-axis stationary axis inverter voltage Vlqs and a reference level voltage 0; A fifth harmonic compensator 1 (45) for compensating the fifth harmonic by controlling the error signal output from the seventh error calculator 44 by proportional resonance (PR) control; An eighth error calculator (46) calculating an error between the stationary axis inverter voltage (Vlqs) and a reference level voltage (0); A seventh harmonic compensator 1 47 for compensating for a seventh harmonic by controlling the error signal output from the eighth error calculator 46 by proportional resonance (PR) control; A ninth adder (48) for first adding the 5th harmonic-compensated value output from the 5th harmonic compensator 1 (45) and the 7th harmonic compensation value output from the 7th harmonic compensator 1 (47) ; The primary added value output from the ninth adder 48, the Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 43, and the Q-axis load current value (IIqs) are all A tenth adder 49 for secondary addition; An eleventh adder (50) for thirdly adding the second-added value output from the tenth adder (49) and a Q-axis inverter current value (Iiqs); A twelfth error calculator 51 for calculating an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds; A second-order fundamental wave compensator 52 for compensating for a second-order fundamental wave by controlling the error signal output from the twelfth error calculator 51 by proportional resonance (PR) control; A thirteenth error calculator (53) calculating an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0); A fifth harmonic compensator 2 (54) for compensating the fifth harmonic by controlling the error signal output from the thirteenth error calculator (53) by proportional resonance (PR) control; A 14th error calculator (55) for calculating an error between the D-axis stationary axis inverter voltage (Vlqs) and a reference level voltage (0); A 7th harmonic compensator 2 (56) for compensating the 7th harmonic by controlling the error signal output from the 14th error calculator (55) by proportional resonance (PR) control; A fifteenth adder (57) for adding the fifth harmonic-compensated value output from the fifth harmonic compensator 2 (54) and the seventh harmonic-compensated value output from the seventh harmonic compensator 2 (56) by a fourth order ; The fourth-order added value output from the fifteenth adder 57, the second-order fundamental wave compensated value output from the second-order fundamental wave compensator 52, and the D-axis load current value (IIds) are all A sixteenth adder 58 to add the fifth order; A seventeenth adder (59) for adding the fifth-order added value output from the sixteenth adder (58) and the D-axis inverter current value (Iids) by a sixth order; A second coordinate axis transformation for converting stationary axis coordinates of the third-added signal output from the eleventh adder (50) and the sixth-added signal output from the seventeenth adder (59) into synchronous axis coordinates Part 60; A Q-axis current controller 61 for controlling a current in a proportional integration (Kp+Ki/s) method of the Q-axis signal output from the second coordinate axis conversion unit 60; A D-axis current controller 62 for controlling a current in a proportional integration (Kp+Ki/s) method of the D-axis signal output from the second coordinate axis conversion unit 60; An eighteenth error calculator (63) calculating an error between the synchronous Q-axis inverter reference voltage (ViqeCmd) and the synchronous Q-axis load voltage (Vlqe) of the DQ synchronous coordinate conversion value; A Q-axis repetition controller 64 for repeatedly controlling the Q-axis error signal output from the eighteenth error calculator 63; A 19th adder (65) for outputting a Q-axis voltage control signal (Vqref) by adding the Q-axis signal output from the Q-axis current controller (61) and the Q-axis error signal output from the Q-axis repeat controller (64). ); A twentieth error calculator (66) for calculating an error between the synchronous D-axis inverter reference voltage (VideCmd) and the synchronous D-axis load voltage (Vlde) of the DQ synchronous coordinate conversion value; A D-axis repetition controller 67 that repeatedly controls the D-axis error signal output from the twentieth error calculator (66); And a 21st adder for outputting a D-axis voltage control signal (Vdref) by adding the D-axis signal output from the D-axis current controller 62 and the D-axis error signal output from the D-axis repeat controller 67 ( 68).

In addition, the frequency control unit 17 includes an active power droop reference signal QdrpRef output from the V/F parallel droop control unit 11 from the bypass voltage synchronization signal ThetaLd output from the synchronization signal generator 7. A frequency subtractor 73 for subtracting) and outputting the droop application synchronization signal ThetaLd2 may be included.

In addition, the synchronization signal generation unit 7 outputs a primary bypass synchronization signal (ThetaByp) synchronized with the Q-axis voltage signal of the three-phase bypass voltage converted by the DQ conversion unit 9 A phase locked loop 87 (PLL); And a second-order phase-locked loop 89 that outputs a second-order bypass synchronization signal (ThetaLd) that is synchronized with the first-order bypass synchronization signal (ThetaByp) output from the first-order phase-locked loop 87. have.

In addition, the DQ conversion unit 9 performs primary DQ conversion (a, b) of the three-phase load voltage supplied to the load from the LC filter unit 5 to convert the first DQ synchronous coordinate values (Vlqs, Vlds). A load voltage primary DQ converter 59 for outputting ); The load voltage primary DQ conversion unit 59 converts the primary DQ stop coordinate conversion values (Vlqs, Vlds) converted to the secondary DQ conversion values (Vlqs, Vlds) to the secondary DQ synchronous coordinate conversion values (Vlqe, Vlde). Load voltage secondary DQ conversion unit 60; A bypass voltage DQ conversion unit 61 for converting the three-phase bypass voltage VBYP bypassed from the bypass line 6 to DQ and outputting a DQ synchronous coordinate conversion value Vbqe; The primary load current that converts (a, b) the three-phase load current (ILD) supplied to the load from the LC filter unit 5 to the primary DQ synchronous coordinate conversion value (Ilqs, Ilds) DQ conversion unit 63; The primary DQ stationary coordinate conversion value (Ilqs, Ilds) converted by the load current primary DQ conversion unit 63 is converted into the secondary DQ conversion value (Ilqe, Ilde) and output as the secondary DQ synchronous coordinate conversion value (Ilqe, Ilde). Load current secondary DQ conversion unit 64; Inverter current primary DQ conversion for outputting primary DQ stop coordinate conversion values (Iiqs, Iids) by primary DQ conversion (a, b) of the 3-phase inverter current (IID) output from the IGBT power conversion unit 3 Part 65; And 2nd DQ conversion of the primary DQ stationary coordinate conversion values (Iiqs, Iids) converted by the inverter current primary DQ conversion unit 65 as secondary DQ synchronous coordinate conversion values (Iiqe, Iide). It may include an inverter current secondary DQ conversion unit 66.

Meanwhile, the V/F droop parallel operation inverter redundancy method according to an embodiment of the present invention for achieving the above object is a V/F droop parallel operation inverter redundancy method in which two or more inverters are connected in parallel, (a) The DC power applied by the No. 1 inverter is converted into AC power, the PWM pulse signal of the AC power is filtered, converted into a sine wave form and supplied to the load, and a three-phase bypass voltage (VBYP) applied from the bypass line, Convert inverter current (IID), three-phase load current (ILD), and three-phase load voltage (VLD) into DQ synchronous coordinate values, and the three-phase load current (ILD) and the three-phase load voltage for the DQ synchronous coordinate value Converting (VLD) into active power (P) and reactive power (Q) values and compensating to calculate an active power reference value (Pref) and a reactive power reference value (Qref), and outputting them to the second unit inverter; (B) Using the active power reference value (Pref) and the reactive power reference value (Qref) applied by the second unit inverter from the first unit inverter as the relative active power reference value (Pm) and the relative reactive power reference value (Qm), respectively, The difference between the relative active power reference value (Pm) and the active power reference value (Pref) is proportionally integrated (Kp+Ki/s) and the difference between the active power reference value and the active power droop factor (Kpdrp) applied. Generated as an active power droop reference signal (PdrpRef) and proportionally integrated (Kp+Ki/s) the difference between the relative reactive power reference value (Qm) and its own reactive power reference value (Qm), and the reactive power reference value (Qref) ) To the difference value of the reactive power droop coefficient (Kqdrp) is applied to the reactive power droop reference signal (QdrpRef) to control the output voltage frequency, the output voltage and the output current, and the active power reference value (Pref) and Outputting the reactive power reference value Qref to the next unit inverter; And (C) the active power reference value (Pref) and the reactive power reference value (Qref) applied from the N-1 inverter by the N-th inverter as the relative active power reference value (Pm) and the relative reactive power reference value (Qm), respectively. , The difference between the relative active power reference value (Pm) and the active power reference value (Pref) is proportionally integrated (Kp+Ki/s), and the active power droop coefficient (Kpdrp) is applied to the difference between the active power reference value. A value obtained by generating a value as an active power droop reference signal (PdrpRef) and proportionally integrating the difference between the relative reactive power reference value (Qm) and the reactive power reference value (Qm) (Kp+Ki/s) and the reactive power reference value Generating a value obtained by applying the reactive power droop coefficient Kqdrp to the difference value of (Qref) as a reactive power droop reference signal QdrpRef, and controlling an output voltage frequency, an output voltage, and an output current; Including, and when at least one (m) of the first to the Nth inverter is not operated, except for the inverters that are not operating (Nm) so that the remaining inverters uniformly distribute power to operate. can do.

In steps (a) to (c), the first to the Nth inverters may be calculated according to the following equation for power deviation compensation (Perr, Qerr).

Here, Perr represents the active power deviation compensation value, Pref (Pm) represents the master active power, Pref represents the active power, Qerr represents the reactive power deviation compensation value, and Qref (Qm) represents the master reactive power. , Qref represents reactive power.

In the steps (a) to (c), at least one inverter among the first to the Nth inverters, (a) the DQ conversion unit 9, from the IGBT power conversion unit 3 The output inverter current (IID), the three-phase load voltage (VLD) and the three-phase load current (ILD) output from the LC filter unit 5, and the three-phase bypass voltage applied from the bypass line (6) DQ conversion of (VBYP) according to the synchronization signal (ThetaByp) provided from the synchronization signal generation unit 7 and the drop application synchronization signal (ThetaLd2) supplied from the frequency control unit 17, and the DQ synchronization coordinate conversion signals (Vlqs, Vlds, Vlqe, Outputting Vlde, Ilqs Ilds, Ilqe Ilde, Iiqs Iids, Iiqe Iide, Vbqe); (b) The phase angle of the three-phase load current input from the DQ converter 9 by the V/F (Voltage/Frequency) parallel droop control unit 11 using the current phase angle compensation value provided from the parameter stored in the memory. Compensates for, and calculates a new active power reference value (Pref) and a reactive power reference value (Qref) using the 3-phase load current compensated for the phase angle and the 3-phase load voltage input from the DQ converter 9, and the In order to lower the voltage frequency output from the inverter by using the active power reference value (Pref) when the active power of the inverter is increased, the difference between the active power reference value (Pref) and the relative active power reference value (Pm) is determined. When a value obtained by applying a droop coefficient (Kpdrp) to the difference between the proportional integral (Kp+Ki/s) value and the active power reference value is generated as an active power droop reference signal (PdrpRef), and the reactive power of the inverter increases In order to lower the voltage output from the inverter by using the reactive power reference value, the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of another inverter is proportionally integrated (Kp+Ki/s), and the Generating a value obtained by applying the droop coefficient Kqdrp to the difference value of the reactive power reference value Qref as a reactive power droop reference signal QdrpRef; (c) The synchronization signal generation unit 7 includes a three-phase bypass voltage synchronization signal (ThetaByp) in phase with the DQ synchronization coordinate conversion signal Vbqe of the three-phase bypass voltage converted by the DQ conversion unit 9. Generating ThetaLd); (d) The first Q-axis error calculator 14 calculates an error between the reactive power droop reference signal QdrpRef and the Q-axis voltage reference signal Vref (q axis) to calculate the synchronous Q-axis inverter reference voltage Vref. (Viqe)) outputting a signal; (e) The inverter voltage and current control unit 15 receives the synchronous Q-axis inverter reference voltage (Vref(Viqe)) signal and a synchronous D-axis inverter reference voltage (0(Vide)) signal, and the DQ synchronous coordinate conversion signal Outputting a Q-axis voltage control signal (Vqref) and a D-axis voltage control signal (Vdref) by controlling the load voltage and load current of the inverter according to (Vlqs, Vlds, Vlqe, Vlde, Ilqs Ilds, Ilqe Ilde); (f) the frequency control unit 17, the active power droop reference signal from the three-phase bypass voltage synchronization signal (ThetaLd) in phase with the DQ synchronization coordinate conversion signal (Vbqe) output from the synchronization signal generator (7) Subtracting (PdrpRef) to output a droop application synchronization signal (ThetaLd2); (g) The DQ inverse conversion unit 13 receives the Q-axis voltage control signal Vqref and the D-axis voltage control signal Vdref from the inverter voltage current control unit 15, and a control signal of the frequency control unit 17 Converting into a three-phase signal according to the step of outputting a command signal for adjusting an output voltage and a frequency of the inverter; And (h) SV PWM conversion unit 19, a spatial vector pulse width modulation for switching the IGBT (Insulated Gate Bipolar Transistor) of the IGBT power conversion unit 3 to the command signal output from the DQ inverse conversion unit 13 A step of converting a signal (SV PWM: Space Vector Pulse Width Modulation) and outputting it to the IGBT power converter 3 may be performed.

In addition, the step (b), (b-1) the PQ conversion unit 21, the DQ synchronous coordinate conversion signal (Vlqe, Vlde) for the three-phase load voltage and the three-phase load current from the DQ conversion unit 9 , Receiving Ilqe Ilde) and calculating active power (P) and reactive power (Q) values supplied to the load; (b-2) The phase error compensation unit 23 receives a three-phase input from the DQ conversion unit 9 using a current phase angle compensation value provided from a parameter stored in the memory to create a parallel droop control signal. A new active power reference signal (Pref) and the reactive power reference signal using the 3-phase load current for which the phase angle of the load current is compensated and the phase angle is compensated and the 3-phase load voltage transmitted from the DQ converter 9 Calculating (Qref); And (b-3) the droop signal generation unit 25 uses the active power reference value Pref when the active power of the inverter is increased, so as to lower the voltage frequency output from the inverter, the active power reference value ( Pref) and the difference between the active power reference value (Pm) of other inverters are proportionally integrated (Kp+Ki/s) and the difference between the active power reference value and the droop factor (Kpdrp) applied to the active power droop reference signal ( PdrpRef), and in order to lower the voltage output from the inverter by using the reactive power reference value when the reactive power of the inverter is increased, the reactive power reference value (Qref) and the reactive power reference value (Qm) of another inverter are Generating a value obtained by applying a droop coefficient (Kqdrp) to the difference value obtained by proportionally integrating the difference (Kp+Ki/s) and the reactive power reference value (Qref) as a reactive power droop reference signal (QdrpRef). have.

In addition, the step (b-3), (b-3-1) the second error calculator 31, calculating an error between the active power reference value (Pref) and the active power reference value (Pm) of another inverter. ; (b-3-2) the first-order proportional integrator 32 performs a first-order proportional integration (Kp+Ki/s) of the value output from the second error calculator 31; (b-3-3) calculating, by a third error calculator (33), an error between the first-order proportional integration value and the active power reference value (Pref); (b-3-4) The active power droop application unit 34 generates an active power droop reference signal (PdrpRef) by applying an active power droop coefficient (Kpdrp) to the value output from the third error calculator (33). The step of doing; (b-3-5) calculating, by the fourth error calculator 35, an error between the reactive power reference value Qref and the reactive power reference value Qm of another inverter; (b-3-6) the second-order proportional integrator 36 performs a second-order proportional integration (Kp+Ki/s) of the value output from the fourth error calculator 35; (b-3-7) calculating, by a fifth error calculator (37), an error between the second-order proportional integration value and the reactive power reference value (Qref); And (b-3-8) the reactive power droop application unit 38 applies a reactive power droop coefficient (Kqdrp) to the value output from the fifth error calculator 37 to obtain a reactive power droop reference signal (QdrpRef). It may include the step of generating.

In addition, the step (e), (e-1) the first coordinate axis conversion unit 41, the synchronous Q-axis inverter reference voltage (Vref (Viqe)) and the synchronous D-axis inverter reference voltage (0 (Vide) Converting the synchronous axis coordinates for) into the stationary axis coordinates and outputting a Q-axis load reference voltage (Vlqs_ref) and a D-axis load reference voltage (Vlds_ref); (e-2) calculating, by the sixth error calculator 42, an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs; (e-3) compensating the first fundamental wave by controlling the error signal output from the sixth error calculator 42 by the first fundamental wave compensator 43 by controlling proportional resonance (PR); (e-4) calculating, by the seventh error calculator (44), an error between the Q-axis stop axis inverter voltage (Vlqs) and a reference level voltage (0); (e-5) performing, by the fifth harmonic compensator 1 (45), performing proportional resonance (PR) control on the error signal output from the seventh error calculator 44 to compensate for the fifth harmonic; (e-6) an eighth error calculator (46) calculating an error between the stationary axis inverter voltage (Vlqs) and a reference level voltage (0); (e-7) performing, by the 7th harmonic compensator 1 (47), performing proportional resonance (PR) control on the error signal output from the eighth error calculator (46) to compensate for the 7th harmonic; (e-8) The ninth adder 48 compensates for the fifth harmonic output from the fifth harmonic compensator 1 (45) and the seventh harmonic compensation output from the seventh harmonic compensator 1 (47). Adding one value first; (e-9) The tenth adder 49 compensates for the first-order added value output from the ninth adder 48 and the first-order fundamental wave output from the first-order fundamental wave compensator 43 Adding the value and the Q-axis load current value (IIqs) by a second order; (e-10) the eleventh adder 50 thirdly adding the second-added value output from the tenth adder 49 and the Q-axis inverter current value Iiqs; (e-11) calculating, by the twelfth error calculator 51, an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds; (e-12) performing, by the second fundamental wave compensator 52, performing proportional resonance (PR) control on the error signal output from the twelfth error calculator 51 to compensate for the second fundamental wave; (e-13) calculating, by the thirteenth error calculator (53), an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0); (e-14) performing, by the fifth harmonic compensator 2 (54), performing proportional resonance (PR) control on the error signal output from the thirteenth error calculator (53) to compensate for the fifth harmonic; (e-15) calculating an error between the D-axis stop axis inverter voltage (Vlqs) and the reference level voltage (0), by the 14th error calculator (55); (e-16) performing, by the 7th harmonic compensator 2 (56), performing proportional resonance (PR) control on the error signal output from the 14th error calculator (55) to compensate for the 7th harmonic; (e-17) The 15th adder 57 compensates for the 5th harmonic output from the 5th harmonic compensator 2 54 and the 7th harmonic compensation output from the 7th harmonic compensator 2 56 Adding one value by the fourth order; (e-18) The sixteenth adder 58 compensates for the fourth-order added value output from the fifteenth adder 57 and the second-order fundamental wave output from the second-order fundamental wave compensator 52 Adding the value and the D-axis load current value (IIds) by a fifth order; (e-19) adding, by a seventeenth adder (59), the fifth-added value output from the sixteenth adder (58) and a D-axis inverter current value (Iids) by a sixth order; (e-20) The second coordinate axis converting unit 60 includes the third-order added signal output from the eleventh adder 50 and the sixth-order added signal output from the seventeenth adder 59. Converting the stationary axis coordinates of the corresponding axis into synchronization axis coordinates; (e-21) The Q-axis current controller 61 controls the Q-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method to control the Q-axis voltage control signal. Outputting (Vqref); And (e-22) the D-axis current controller 62 controls the D-axis signal output from the second coordinate axis converter 60 in a proportional integration (Kp+Ki/s) method to control the D-axis voltage. It may include the step of outputting the signal (Vdref).

And, the step (e), (e-1) the first coordinate axis conversion unit 41, the synchronous Q-axis inverter reference voltage (Vref (Viqe)) and the synchronous D-axis inverter reference voltage (0 (Vide) Converting the synchronous axis coordinates for) into the stationary axis coordinates and outputting a Q-axis load reference voltage (Vlqs_ref) and a D-axis load reference voltage (Vlds_ref); (e-2) calculating, by the sixth error calculator 42, an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs; (e-3) compensating the first fundamental wave by controlling the error signal output from the sixth error calculator 42 by the first fundamental wave compensator 43 by controlling proportional resonance (PR); (e-4) calculating, by the seventh error calculator (44), an error between the Q-axis stop axis inverter voltage (Vlqs) and a reference level voltage (0); (e-5) performing, by the fifth harmonic compensator 1 (45), performing proportional resonance (PR) control on the error signal output from the seventh error calculator 44 to compensate for the fifth harmonic; (e-6) an eighth error calculator (46) calculating an error between the stationary axis inverter voltage (Vlqs) and a reference level voltage (0); (e-7) performing, by the 7th harmonic compensator 1 (47), performing proportional resonance (PR) control on the error signal output from the eighth error calculator (46) to compensate for the 7th harmonic; (e-8) The ninth adder 48 compensates for the fifth harmonic output from the fifth harmonic compensator 1 (45) and the seventh harmonic compensation output from the seventh harmonic compensator 1 (47). Adding one value first; (e-9) The tenth adder 49 compensates for the first-order added value output from the ninth adder 48 and the first-order fundamental wave output from the first-order fundamental wave compensator 43 Adding the value and the Q-axis load current value (IIqs) by a second order; (e-10) the eleventh adder 50 thirdly adding the second-added value output from the tenth adder 49 and the Q-axis inverter current value Iiqs; (e-11) calculating, by the twelfth error calculator 51, an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds; (e-12) performing, by the second fundamental wave compensator 52, performing proportional resonance (PR) control on the error signal output from the twelfth error calculator 51 to compensate for the second fundamental wave; (e-13) calculating, by the thirteenth error calculator (53), an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0); (e-14) performing, by the fifth harmonic compensator 2 (54), performing proportional resonance (PR) control on the error signal output from the thirteenth error calculator (53) to compensate for the fifth harmonic; (e-15) calculating an error between the D-axis stop axis inverter voltage (Vlqs) and the reference level voltage (0), by the 14th error calculator (55); (e-16) performing, by the 7th harmonic compensator 2 (56), performing proportional resonance (PR) control on the error signal output from the 14th error calculator (55) to compensate for the 7th harmonic; (e-17) The 15th adder 57 compensates for the 5th harmonic output from the 5th harmonic compensator 2 54 and the 7th harmonic compensation output from the 7th harmonic compensator 2 56 Adding one value by the fourth order; (e-18) The sixteenth adder 58 compensates for the fourth-order added value output from the fifteenth adder 57 and the second-order fundamental wave output from the second-order fundamental wave compensator 52 Adding the value and the D-axis load current value (IIds) by a fifth order; (e-19) adding, by a seventeenth adder (59), the fifth-added value output from the sixteenth adder (58) and a D-axis inverter current value (Iids) by a sixth order; (e-20) The second coordinate axis converting unit 60 includes the third-order added signal output from the eleventh adder 50 and the sixth-order added signal output from the seventeenth adder 59. Converting the stationary axis coordinates of the corresponding axis into synchronization axis coordinates; (e-21) The Q-axis current controller 61 controls the Q-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method to control the Q-axis voltage control signal. Outputting (Vqref); And (e-22) the D-axis current controller 62 controls the D-axis signal output from the second coordinate axis converter 60 in a proportional integration (Kp+Ki/s) method to control the D-axis voltage. Outputting a signal Vdref; (e-23) an eighteenth error calculator (63) calculating an error between the synchronous Q-axis inverter reference voltage (ViqeCmd) and the synchronous Q-axis load voltage (Vlqe) of the DQ synchronous coordinate conversion value; (e-24) the step of repeatedly controlling, by the Q-axis repetition controller (64), the Q-axis error signal output from the eighteenth error calculator (63); (e-25) The 19th adder 65 adds the Q-axis signal output from the Q-axis current controller 61 and the Q-axis error signal output from the Q-axis repetition controller 64 to obtain a Q-axis voltage. Outputting a control signal Vqref; (e-26) calculating, by the twentieth error calculator (66), an error between the synchronous D-axis inverter reference voltage (VideCmd) and the synchronous D-axis load voltage (Vlde) of the DQ synchronous coordinate conversion value; (e-27) the step of repeatedly controlling, by the D-axis repetition controller 67, the D-axis error signal output from the twentieth error calculator (66); And (e-28) the 21st adder 68 adds the D-axis signal output from the D-axis current controller 62 and the D-axis error signal output from the D-axis repetition controller 67, It may include the step of outputting the voltage control signal (Vdref).

According to the present invention, in order to minimize the power deviation between each inverter, the power deviation value is compensated with a wired signal through V/F droop control and redundant parallel operation, thereby minimizing the power deviation in the normal state of wired communication, and In case of an error, there is an effect of continuously maintaining parallel operation by V/F droop control.

In addition, in the present invention, when at least one (m) of the No. 1 inverter to the No. N inverter is not operated, except for the non-operating inverters (Nm), the remaining inverters can evenly distribute power and operate. have.

In addition, when two or more inverters are connected in parallel and a load is commonly connected to two or more inverters, if the active power of the inverter increases, the voltage frequency output from the inverter is lowered to lower the increased active power, and the reactive power of the inverter. When this increases, the voltage output from the inverter is lowered to lower the increased reactive power, so that the load of two or more inverters connected in parallel can be equally controlled.

As a result, by maintaining the active power and reactive power of the inverter constant, it is possible to suppress an overcurrent output from the inverter due to a circulating current that may occur due to the active power deviation and the reactive power deviation between the inverters.

In addition, the present invention can compensate for the imbalance of the load voltage due to the load unbalance when two or more inverters are operated in parallel, and when controlling the V/F droop (Voltage/Frequency Droop), the active power and the reactive power By compensating for the deviation, the load sharing characteristics of the inverter can be improved.

In addition, in the present invention, when a plurality of inverters are operated in parallel, the deviation of active power and reactive power that may be generated from each inverter is more quickly compensated, thereby stabilizing the parallel operation state of the inverter.

1 is a block diagram schematically showing the configuration of a V/F droop parallel operation inverter redundancy apparatus according to an embodiment of the present invention.
2 is a block diagram schematically showing the internal configuration of each unit inverter according to an embodiment of the present invention.
3 is a block diagram showing a detailed configuration of each unit inverter according to an embodiment of the present invention.
4 is a block diagram schematically showing an internal configuration of an inverter voltage and current controller according to an embodiment of the present invention.
5 is a block diagram schematically showing an internal configuration of an inverter voltage-current control unit according to another embodiment of the present invention.
6 is a diagram illustrating an operation flowchart for explaining a method of controlling a V/F droop parallel operation inverter of each unit inverter according to an exemplary embodiment of the present invention.
7 is a flowchart illustrating an operation process of a V/F parallel droop control unit according to an embodiment of the present invention.
8 is a flowchart illustrating an operation process of a droop signal generator in a V/F parallel droop controller according to an embodiment of the present invention.
9A and 9B are flowcharts illustrating an operation process of the inverter voltage and current controller according to an embodiment of the present invention.
10A to 10C are flowcharts illustrating an operation process of the inverter voltage and current controller according to another embodiment of the present invention.
10A to 10C are diagrams showing graphs in which voltage and current are improved according to the operation of the inverter voltage-current controller according to an embodiment of the present invention.
11A is a graph showing a voltage waveform according to resonance control during a nonlinear load of an inverter voltage current controller according to an embodiment of the present invention.
11B is a graph showing the results of analyzing the voltage waveform distortion of FIG. 10A.
11C is a graph showing when the inductor value is the same (virtual deviation zero (0)) at the output side.
11D is a graph showing when the inductor values at the output side are not the same (virtual deviation is inserted) and are different.
12 is a diagram illustrating an operation flow diagram (communication configuration) for explaining a method for redundantly operating a V/F droop parallel operation inverter according to an embodiment of the present invention.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only this embodiment is intended to complete the disclosure of the present invention, and the general knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to the possessor, and the invention is only defined by the scope of the claims. Accordingly, in some embodiments, well-known process steps, well-known device structures, and well-known techniques have not been described in detail in order to avoid obscuring interpretation of the present invention. The same reference numerals refer to the same elements throughout the specification.

In the drawings, the thicknesses are enlarged in order to clearly express various layers and regions. Like reference numerals are attached to similar parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the case where the other part is "directly above", but also the case where there is another part in the middle. Conversely, when one part is "directly above" another part, it means that there is no other part in the middle. Further, when a part such as a layer, film, region, plate, etc. is said to be "under" another part, this includes not only the case where the other part is "directly below", but also the case where there is another part in the middle. Conversely, when one part is "right below" another part, it means that there is no other part in the middle.

Spatially relative terms "below", "beneath", "lower", "above", "upper", etc. It may be used to easily describe the correlation between the device or components and other devices or components. Spatially relative terms should be understood as terms including different directions of the device during use or operation in addition to the directions shown in the drawings. For example, if an element shown in the figure is turned over, an element described as “below” or “beneath” of another element may be placed “above” another element. Accordingly, the exemplary term “below” may include both directions below and above. The device may be oriented in other directions, and thus spatially relative terms may be interpreted according to the orientation.

In the present specification, when a part is said to be connected to another part, this includes not only a case in which it is directly connected, but also a case in which it is electrically connected with another element interposed therebetween. In addition, when a part includes a certain component, this means that other components may be further included rather than excluding other components unless otherwise specified.

In the present specification, terms such as first, second, and third may be used to describe various elements, but these elements are not limited by the terms. The terms are used for the purpose of distinguishing one component from other components. For example, without departing from the scope of the present invention, a first component may be referred to as a second or third component, and similarly, a second or third component may be alternately named.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used with meanings that can be commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not interpreted ideally or excessively unless explicitly defined specifically.

Hereinafter, an all-solid-state composite electrode based on a metal support, a method of manufacturing the same, and an all-solid secondary battery having the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing the configuration of a V/F droop parallel operation inverter redundancy apparatus according to an embodiment of the present invention.

1, a V/F droop parallel operation inverter redundancy apparatus 1000 according to an embodiment of the present invention includes a first unit inverter 1010, a second unit inverter 1020 to an Nth unit inverter 1030. Includes.

The first unit inverter 1010 converts the applied DC power into AC power, filters the PWM pulse signal of the AC power, converts it into a sine wave form, and supplies it to the load, and a three-phase bypass voltage applied from the bypass line ( VBYP), inverter current (IID), three-phase load current (ILD), and three-phase load voltage (VLD) are converted into a DQ synchronous coordinate signal by DQ conversion, and the three-phase load current (ILD) and the three-phase load voltage The DQ synchronization coordinate signal for (VLD) is PQ converted to generate active power (P) and reactive power (Q) and compensated to calculate the first active power reference value (Pref) and the first reactive power reference value (Qref). Output to the unit 2 inverter 1020.

The second unit inverter 1020 uses the first active power reference value Pref and the first reactive power reference value Qref applied from the first unit inverter 1010 to be a relative active power reference value Pm and a relative reactive power reference value, respectively. As (Qm), the difference between the relative active power reference value (Pm) and the second active power reference value (Pref) is proportionally integrated (Kp+Ki/s) and the second active power reference value (Pref) The value obtained by applying the active power droop factor (Kpdrp) to the value is generated as an active power droop reference signal (PdrpRef), and the difference between the relative reactive power reference value (Qm) and its second reactive power reference value (Qref) is proportionally integrated (Kp). The value obtained by applying the reactive power droop coefficient (Kqdrp) to the difference between the +Ki/s) value and the second reactive power reference value (Qref) is generated as a reactive power droop reference signal (QdrpRef) to generate the output voltage frequency, output voltage, and The output current is controlled, and the second active power reference value Pref and the second reactive power reference value Qref are output to the next third unit inverter.

In this way, the inverters of each unit perform the same operation as described above, and the Nth unit inverter 1030 includes the N-1th active power reference value (Pref) and the N-1th reactive power applied from the N-1th inverter. Using the reference value (Qref) as the relative active power reference value (Pm) and the relative reactive power reference value (Qm), respectively, the difference between the relative active power reference value (Pm) and its Nth active power reference value (Pref) is proportionally integrated (Kp). A value obtained by applying an active power droop factor (Kpdrp) to the difference between +Ki/s) and the Nth active power reference value Pref is generated as an active power droop reference signal PdrpRef, and the relative reactive power reference value ( Reactive power droop coefficient (Kqdrp) is applied to the difference between Qm) and its Nth reactive power reference value (Qref) proportionally integrated (Kp+Ki/s) and the Nth reactive power reference value (Qref). By generating a value as a reactive power droop reference signal (QdrpRef), the output voltage frequency, output voltage, and output current are controlled.

The V/F droop parallel operation inverter redundancy apparatus 1000 of the above-described configuration is not operated when at least one (m) of the first unit inverter 1010 to the unit N unit inverter 1030 is not operated. Excluding the inverters (Nm), the remaining inverters are uniformly distributed and operated.

2 is a block diagram schematically showing the internal configuration of each unit inverter according to an embodiment of the present invention.

1, in each unit inverter 100 according to an embodiment of the present invention, two or more inverters are connected in parallel, and each inverter includes an inverter stage 110 and an inverter control unit 120 do.

The inverter stage 110 converts the DC power applied to the inverter into AC power, filters the PWM pulse signal of the AC power, converts it into a sinusoidal wave, and supplies it to the load. It receives 3-phase AC power and supplies it to the load.

The inverter control unit 120 includes a three-phase bypass voltage (VBYP) applied from the bypass line 6, an inverter current (IID) detected from the inverter stage 110, a three-phase load current (ILD), and a three-phase load voltage. DQ conversion of (VLD) to generate a DQ synchronization coordinate signal, and PQ conversion and compensation of DQ synchronization coordinate signals (Vlqe, Vlde, Ilqe, Ilde) for three-phase load current (ILD) and three-phase load voltage (VLD). Thus, the active power reference value Pref and the reactive power reference value Qref are calculated.

In addition, the inverter control unit 120 proportionally integrates the difference between the active power reference value Pref and the active power reference value Pm of other inverters (Kp+Ki/s) and the active power droop on the difference value between the active power reference value. The value obtained by applying the coefficient (Kpdrp) is generated as the active power droop reference signal (PdrpRef), and the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of other inverters is proportionally integrated (Kp+Ki/s). The value obtained by applying the reactive power droop factor (Kqdrp) to the difference between the reactive power reference value (Qref) and the reactive power droop factor (Kqdrp) is generated as a reactive power droop reference signal (QdrpRef), and the output voltage frequency, output voltage, and current of the inverter are controlled.

The inverter stage 110 includes an inverter switch 1, an IGBT power conversion unit 3, a bypass switch 4 and an LC filter unit 5.

The IGBT power conversion unit 3 converts DC power applied to the inverter into AC power and outputs an inverter current according to a PWM pulse signal.

The LC filter unit 5 filters the PWM pulse signal output from the IGBT power conversion unit 3 and converts it into a sine wave form.

The inverter switch 1 is connected to the output terminal of the LC filter unit 5 to switch the filtered inverter current to flow to the load.

The bypass switch 4 is connected to the output terminal of the inverter switch 1 to switch the three-phase AC power input from the bypass line 6 to the load side.

The inverter control unit 120 includes a synchronization signal generation unit 7, a DQ conversion unit 9, a V/F (Voltage/Frequency) parallel droop control unit 11, an inverse DQ conversion unit 13, and a first Q-axis error calculator. (14), an inverter voltage and current control unit 15, a frequency control unit 17, an SV PWM (Space Vector Pulse Width Modulation) conversion unit 19, and the like.

The DQ conversion unit 9 converts the inverter current IID output from the IGBT power conversion unit 3 and the three-phase load voltage VLD and the three-phase load current ILD output from the LC filter unit 5. The first DQ conversion is performed to generate DQ stop coordinate conversion signals (Vlqs, Vlds, Ilqs Ilds, Iiqs Iids), and the three-phase bypass voltage (VBYP) applied from the bypass line (6) is converted into a synchronization signal generator (7). The first DQ conversion is performed in accordance with the synchronization signal (ThetaByp) provided from, to generate the DQ synchronization coordinate conversion signal (Vbde) of the 3-phase bypass voltage, and the DQ stop coordinate conversion signal (Vlqs, Vlds, Ilqs Ilds, Iiqs Iids) is frequency The second DQ conversion is performed in accordance with the drop application synchronization signal ThetaLd2 provided from the control unit 17 to generate and output the DQ synchronization coordinate conversion signals Vlqe, Vlde, Ilqe, Ilde, Iiqe, and Iide.

The synchronization signal generation unit 7 generates a DQ synchronization coordinate conversion signal Vbde of the three-phase bypass voltage converted by the DQ conversion unit 9 and a three-phase bypass voltage synchronization signal (ThetaByp, ThetaLd) in phase. .

The Q-axis first error calculator 14 calculates the error between the reactive power droop reference signal (QdrpRef) and the Q-axis voltage reference signal (Vref (q axis)) to calculate the synchronous Q-axis inverter reference voltage signal (Vref (ViqeCmd)). Prints.

The inverter voltage and current control unit 15 receives a synchronous Q-axis inverter reference voltage signal (Vref(ViqeCmd)) and a synchronous D-axis inverter reference voltage (0(VideCmd)) signal, and receives DQ synchronous coordinate conversion signals (Vlqe, Vlde, and Ilqe). , Ilde) to control the load voltage and load current of the inverter to output a Q-axis voltage control signal (Vqref) and a D-axis voltage control signal (Vdref).

The DQ inverse conversion unit 13 receives the Q-axis voltage control signal Vqref and the D-axis voltage control signal Vdref from the inverter voltage current control unit 15 and converts it into a three-phase signal according to the control signal of the frequency control unit 17. Thus, it outputs a command signal for adjusting the output voltage and frequency of the inverter.

The SV PWM conversion unit 19 converts the command signal output from the DQ inverse conversion unit 13 into a space vector pulse width modulation signal (SV PWM) for switching the IGBT (Insulated Gate Bipolar Transistor) of the IGBT power conversion unit 3. Convert.

The V/F (Voltage/Frequency) parallel droop control unit 11 compensates the phase angle of the three-phase load current input from the DQ conversion unit 9 using the current phase angle compensation value provided from the parameter stored in the memory, and The new active power reference value (Pref) and the reactive power reference value (Qref) were calculated using the three-phase load current compensated for the angle and the three-phase load voltage input from the DQ converter 9, and the active power of the inverter was increased. In order to lower the voltage frequency output from the inverter by using the active power reference value (Pref), the difference between the active power reference value (Pref) and the active power reference value (Pm) of other inverters is proportionally integrated (Kp+Ki/s). The voltage output from the inverter using the reactive power reference value when the active power droop reference signal (PdrpRef) is applied to the difference between the active power reference value and the active power reference value as the active power droop reference signal (PdrpRef). In order to reduce the value of the reactive power reference value (Qref) and the reactive power reference value (Qm) of other inverters proportionally integrated (Kp+Ki/s) and the reactive power reference value (Qref), the reactive power droop coefficient ( Kqdrp) is applied as a reactive power droop reference signal (QdrpRef).

The frequency control unit 17 subtracts the active power droop reference signal (PdrpRef) from the three-phase bypass voltage synchronization signal (ThetaLd) output from the synchronization signal generator 7 to generate a droop application synchronization signal (ThetaLd2) and converts DQ. Output to the sub (9) and the DQ inverse transform unit (13).

3 is a block diagram showing a detailed configuration of each unit inverter according to an embodiment of the present invention.

3, in each unit inverter 100 according to an embodiment of the present invention, the V/F parallel droop control unit 11 includes a PQ conversion unit 21, a phase error compensation unit 23, and a droop signal generation unit. It includes (25).

The PQ conversion unit 21 receives the DQ synchronization coordinate conversion signals (Vlqe, Vlde, Ilqe Ilde) for the three-phase load voltage and the three-phase load current from the DQ conversion unit 9, and is supplied to the load (P). And reactive power (Q) values are calculated.

The phase error compensation unit 23 compensates the phase angle of the three-phase load current input from the DQ converter 9 using the current phase angle compensation value provided from the parameter stored in the memory to create a parallel droop control signal. Then, a new active power reference signal Pref and a reactive power reference signal Qref are calculated using the three-phase load current compensated for the phase angle and the three-phase load voltage transmitted from the DQ converter 9.

The droop signal generator 25 uses the active power reference value Pref when the active power of the inverter is increased to lower the voltage frequency output from the inverter. The effective power droop value obtained by applying the droop coefficient (Kpdrp) to the difference between the relative active power reference value (Pm) received from the relative active power reference value (Pm) proportionally integrated (Kp+Ki/s) and the active power reference value In order to lower the voltage output from the inverter by generating it as a reference signal (PdrpRef) and using the reactive power reference value when the reactive power of the inverter increases, its own reactive power reference value (Qref) and the relative reactive power reference value of the previous unit inverter The value obtained by applying the droop coefficient (Kqdrp) to the difference between the difference in (Qm) proportionally integrated (Kp+Ki/s) and the reactive power reference value (Qref) is calculated as the reactive power droop reference signal (QdrpRef) as shown in Equation 2 below. ).

In Equation 1, PdrpRef represents the V-F Droop active power compensation reference value, Kp represents the active power compensation gain, Pref represents the active power, Kpd represents the active power variation gain, and dPref represents the active power variation.

In Equation 2, QdrpRef represents the V-F Droop reactive power compensation reference value, Kq represents the reactive power compensation gain, Qref represents the reactive power, Kqd represents the reactive power variation gain, and dQref represents the reactive power variation.

The droop signal generation unit 25 includes a second error calculator 31, a first-order proportional integrator 32, a third error calculator 33, an active power droop application unit 34, and a fourth error calculator 35, It includes a second proportional integrator 36, a fifth error calculator 37, a reactive power droop application unit 38, and the like.

The second error calculator 31 calculates an error between the active power reference value Pref and the active power reference value Pm of another inverter.

The first proportional integrator 32 performs a first proportional integration (Kp+Ki/s) of the value output from the second error calculator 31.

The third error calculator 33 calculates an error between the first-order proportional integration value and the active power reference value Pref.

The active power droop application unit 34 generates an active power droop reference signal PdrpRef by applying the active power droop coefficient Kpdrp to the value output from the third error calculator 33.

The fourth error calculator 35 calculates an error between the reactive power reference value Qref and the reactive power reference value Qm of another inverter.

The second-order proportional integrator 36 performs a second-order proportional integration (Kp+Ki/s) of the value output from the fourth error calculator 35.

The fifth error calculator 37 calculates an error between the second-order proportionally integrated value and the reactive power reference value Qref.

The reactive power droop application unit 38 generates a reactive power droop reference signal QdrpRef by applying the reactive power droop coefficient Kqdrp to the value output from the fifth error calculator 37.

In FIG. 3, the frequency control unit 17 includes a reactive power droop reference signal QdrpRef output from the V/F parallel droop control unit 11 from the bypass voltage synchronization signal ThetaLd output from the synchronization signal generator 7. ) And a frequency subtractor 73 for outputting the droop application synchronization signal ThetaLd2.

Further, the synchronization signal generation unit 7 includes a first-order phase locked loop (PLL) 87 and a second-order phase locked loop 89.

The primary phase locked loop 87 outputs a primary bypass synchronization signal ThetaByp synchronized with the Q-axis voltage signal of the 3-phase bypass voltage converted by the DQ converter 9.

The second phase locked loop 89 outputs the first bypass synchronization signal ThetaByp output from the first phase locked loop 87 and the second bypass synchronization signal ThetaLd in duplex synchronization.

In FIG. 3, the DQ conversion unit 9 includes a load voltage primary DQ conversion unit 79, a load voltage secondary DQ conversion unit 80, a bypass voltage DQ conversion unit 81, and a load current 1 A secondary DQ conversion section 83, a load current secondary DQ conversion section 84, an inverter current primary DQ conversion section 85, an inverter current secondary DQ conversion section 86, and the like.

The load voltage primary DQ conversion unit 79 performs primary DQ conversion (a, b) of the three-phase load voltage supplied to the load from the LC filter unit 5 to obtain the primary DQ synchronous coordinate conversion values (Vlqs, Vlds). Print it out.

The load voltage secondary DQ conversion unit 80 converts the primary DQ stop coordinate conversion values (Vlqs, Vlds) converted first by the load voltage primary DQ conversion unit 79 to the secondary DQ and converts the secondary DQ synchronous coordinates. Output as converted values (Vlqe, Vlde).

The bypass voltage DQ conversion unit 81 DQ-converts the 3-phase bypass voltage VBYP bypassed from the bypass line 6 and outputs a DQ synchronous coordinate conversion value Vbde.

The load current primary DQ conversion unit 83 converts the three-phase load current (ILD) supplied to the load from the LC filter unit 5 to the first DQ conversion (a, b) to convert the primary DQ synchronous coordinate conversion value (Ilqs). ,Ilds).

The load current secondary DQ conversion unit 84 converts the primary DQ stop coordinate conversion values (Ilqs, Ilds) converted first by the load current primary DQ conversion unit 83 to the secondary DQ to convert the secondary DQ synchronous coordinates. Output as converted values (Ilqe, Ilde).

The inverter current primary DQ conversion unit 85 converts the three-phase inverter current (IID) output from the IGBT power conversion unit 3 into the primary DQ conversion (a, b), and converts the primary DQ stationary coordinate values (Iiqs, Iids). ).

The inverter current secondary DQ conversion unit 86 converts the primary DQ stop coordinate conversion values (Iiqs, Iids) converted first by the inverter current primary DQ conversion unit 85 to the secondary DQ and converts the secondary DQ synchronous coordinates. Output as converted value (Iiqe, Iide).

4 is a block diagram schematically showing an internal configuration of an inverter voltage-current control unit according to an embodiment of the present invention.

4, the inverter voltage and current control unit 15 according to an embodiment of the present invention includes a first coordinate axis conversion unit 41, a sixth error calculator 42, a Q-axis fundamental wave compensator 43, and a seventh axis. Error calculator (44), 5th harmonic compensator 1 (45), 8th error calculator (46), 7th harmonic compensator 1 (47), 9th adder (48), 10th adder (49), 11th adder ( 50), 12th error calculator 51, D-axis fundamental wave compensator 52, 13th error calculator 53, 5th harmonic compensator 2 (54), 14th error calculator 55, 7th harmonic compensator 2 (56), 15th adder (57), 16th adder (58), 17th adder (59), second coordinate axis conversion unit 60, Q-axis current controller 61, D-axis current controller 62, etc. Includes.

The first coordinate axis conversion unit 41 converts the synchronous axis coordinates of the synchronous Q-axis inverter reference voltage (Vref(Viqe)) and the synchronous D-axis inverter reference voltage (0(Vide)) into stationary axis coordinates, and is based on the Q-axis load. The voltage (Vlqs_ref) and the D-axis load reference voltage (Vlds_ref) are output.

The sixth error calculator 42 calculates an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs.

The Q-axis fundamental wave compensator 43 compensates the Q-axis fundamental wave by controlling the error signal output from the sixth error calculator 42 by proportional resonance (PR) control.

The seventh error calculator 44 calculates an error between the Q-axis stop axis inverter voltage Vlqs and the reference level voltage 0.

The fifth harmonic compensator 1 45 compensates for the fifth harmonic by controlling the error signal output from the seventh error calculator 44 by proportional resonance (PR) control.

The eighth error calculator 46 calculates an error between the stationary axis inverter voltage Vlqs and the reference level voltage 0.

The 7th harmonic compensator 1 47 compensates for the 7th harmonic by controlling the error signal output from the 8th error calculator 46 with proportional resonance (PR) control.

The ninth adder 48 adds the fifth harmonic-compensated value output from the fifth harmonic compensator 1 (45) and the seventh harmonic-compensated value output from the seventh harmonic compensator 1 (47) as a first order.

The tenth adder 49 includes a primary added value output from the ninth adder 48, a Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 43, and a Q-axis load current value (IIqs). All are added to the second order.

The eleventh adder 50 thirdly adds the second-added value output from the tenth adder 49 and the Q-axis inverter current value Iiqs.

The twelfth error calculator 51 calculates an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds.

The D-axis fundamental wave compensator 52 compensates the D-axis fundamental wave by controlling the error signal output from the twelfth error calculator 51 by proportional resonance (PR) control.

The thirteenth error calculator 53 calculates an error between the D-axis stop axis inverter voltage Vlds and the reference level voltage 0.

The fifth harmonic compensator 2 54 compensates for the fifth harmonic by controlling the error signal output from the thirteenth error calculator 53 with proportional resonance (PR) control.

The fourteenth error calculator 55 calculates an error between the D-axis stop axis inverter voltage Vlqs and the reference level voltage 0.

The 7th harmonic compensator 2 (56) compensates for the 7th harmonic by controlling the error signal output from the 14th error calculator 55 by proportional resonance (PR) control.

The fifteenth adder 57 adds the fifth harmonic-compensated value output from the fifth harmonic compensator 254 and the seventh harmonic-compensated value output from the seventh harmonic compensator 256 to the fourth order.

The sixteenth adder 58 includes a fourth-order added value output from the fifteenth adder 57, a D-axis fundamental wave compensated value output from the D-axis fundamental wave compensator 52, and a D-axis load current value (IIds). ) Are added to the 5th order.

The seventeenth adder 59 adds the fifth-order added value output from the sixteenth adder 58 and the D-axis inverter current value Iids by the sixth order.

The second coordinate axis conversion unit 60 converts the stationary axis coordinates of the third-added signal output from the eleventh adder 50 and the sixth-added signal output from the seventeenth adder 59 into synchronous axis coordinates. do.

The Q-axis current controller 61 outputs a Q-axis voltage control signal Vqref by controlling the current in a proportional integration (Kp+Ki/s) method on the Q-axis signal output from the second coordinate axis conversion unit 60.

The D-axis current controller 62 controls the current on the D-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method, and outputs the D-axis voltage control signal Vdref.

5 is a block diagram schematically showing an internal configuration of an inverter voltage-current control unit according to another embodiment of the present invention.

5, the inverter voltage and current control unit 15 according to another embodiment of the present invention includes a first coordinate axis conversion unit 41, a sixth error calculator 42, a Q-axis fundamental wave compensator 43, and 7 error calculator (44), 5th harmonic compensator 1 (45), 8th harmonic compensator (46), 7th harmonic compensator 1 (47), 9th adder (48), 10th adder (49), 11th adder (50), 12th error calculator (51), D-axis fundamental wave compensator (52), 13th error calculator (53), 5th harmonic compensator 2 (54), 14th error calculator (55), 7th harmonic compensator 2 (56), 15th adder (57), 16th adder (58), 17th adder (59), second coordinate axis conversion unit 60, Q-axis current controller 61, D-axis current controller 62 , An 18th error calculator 63, a Q axis iteration controller 64, a 19th adder 65, a 20th error calculator 66, a D axis iteration controller 67, a 21st adder 68, and the like. .

The first coordinate axis conversion unit 41 converts the synchronous axis coordinates of the synchronous Q-axis inverter reference voltage (Vref(Viqe)) and the synchronous D-axis inverter reference voltage (0(Vide)) into stationary axis coordinates, and is based on the Q-axis load. The voltage (Vlqs_ref) and the D-axis load reference voltage (Vlds_ref) are output.

The sixth error calculator 42 calculates an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs.

The Q-axis fundamental wave compensator 43 compensates the Q-axis fundamental wave by controlling the error signal output from the sixth error calculator 42 by proportional resonance (PR) control.

The seventh error calculator 44 calculates an error between the Q-axis stop axis inverter voltage Vlqs and the reference level voltage 0.

The fifth harmonic compensator 1 45 compensates for the fifth harmonic by controlling the error signal output from the seventh error calculator 44 by proportional resonance (PR) control.

The eighth error calculator 46 calculates an error between the stationary axis inverter voltage Vlqs and the reference level voltage 0.

The 7th harmonic compensator 1 47 compensates for the 7th harmonic by controlling the error signal output from the 8th error calculator 46 with proportional resonance (PR) control.

The ninth adder 48 adds the fifth harmonic-compensated value output from the fifth harmonic compensator 1 (45) and the seventh harmonic-compensated value output from the seventh harmonic compensator 1 (47) as a first order.

The tenth adder 49 includes a primary added value output from the ninth adder 48, a Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 43, and a Q-axis load current value (IIqs). All are added to the second order.

The eleventh adder 50 thirdly adds the second-added value output from the tenth adder 49 and the Q-axis inverter current value Iiqs.

The twelfth error calculator 51 calculates an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds.

The D-axis fundamental wave compensator 52 compensates the D-axis fundamental wave by controlling the error signal output from the twelfth error calculator 51 by proportional resonance (PR) control.

The thirteenth error calculator 53 calculates an error between the D-axis stop axis inverter voltage Vlds and the reference level voltage 0.

The fifth harmonic compensator 2 54 compensates for the fifth harmonic by controlling the error signal output from the thirteenth error calculator 53 with proportional resonance (PR) control.

The fourteenth error calculator 55 calculates an error between the D-axis stop axis inverter voltage Vlqs and the reference level voltage 0.

The 7th harmonic compensator 2 (56) compensates for the 7th harmonic by controlling the error signal output from the 14th error calculator 55 by proportional resonance (PR) control.

The fifteenth adder 57 adds the fifth harmonic-compensated value output from the fifth harmonic compensator 254 and the seventh harmonic-compensated value output from the seventh harmonic compensator 256 to the fourth order.

The sixteenth adder 58 includes a fourth-order added value output from the fifteenth adder 57, a D-axis fundamental wave compensated value output from the D-axis fundamental wave compensator 52, and a D-axis load current value (IIds). ) Are added to the 5th order.

The seventeenth adder 59 adds the fifth-order added value output from the sixteenth adder 58 and the D-axis inverter current value Iids by the sixth order.

The second coordinate axis conversion unit 60 converts the stationary axis coordinates of the third-added signal output from the eleventh adder 50 and the sixth-added signal output from the seventeenth adder 59 into synchronous axis coordinates. do.

The Q-axis current controller 61 controls the current on the Q-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method.

The D-axis current controller 62 controls the current on the D-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method.

The eighteenth error calculator 63 calculates an error between the synchronous Q-axis inverter reference voltage ViqeCmd and the synchronous Q-axis load voltage Vlqe of the DQ synchronous coordinate conversion value.

The Q-axis repetition controller 64 repeatedly controls the Q-axis error signal output from the eighteenth error calculator 63.

The nineteenth adder 65 adds the Q-axis signal output from the Q-axis current controller 61 and the Q-axis error signal output from the Q-axis repeat controller 64 to output a Q-axis voltage control signal Vqref. .

The twentieth error calculator 66 calculates an error between the synchronous D-axis inverter reference voltage VideCmd and the synchronous D-axis load voltage Vlde of the DQ synchronous coordinate conversion value.

The D-axis repetition controller 67 repeatedly controls the D-axis error signal output from the twentieth error calculator 66.

The 21st adder 68 adds the D-axis signal output from the D-axis current controller 62 and the D-axis error signal output from the D-axis repeat controller 67 to output a D-axis voltage control signal Vdref. .

6 is a diagram illustrating an operation flowchart for explaining a method of controlling a V/F droop parallel operation inverter of each unit inverter according to an exemplary embodiment of the present invention.

6, in each unit inverter 100 according to an embodiment of the present invention, the DQ conversion unit 9 includes an inverter current IID output from the IGBT power conversion unit 3 and an LC filter unit 5 ), the three-phase load voltage (VLD), the three-phase load current (ILD), and the three-phase bypass voltage (VBYP) applied from the bypass line (6) are supplied from the synchronization signal generator (7). ThetaByp) and the drop-applied synchronization signal (ThetaLd2) provided from the frequency control unit 17 by DQ conversion, and DQ stop and synchronization coordinate conversion signals (Vlqs, Vlds, Vlqe, Vlde, Ilqs Ilds, Ilqe Ilde, Iiqs Iids, Iiqe Iide, Vbde) is output (S510).

In addition, the V/F parallel droop control unit 11 compensates the phase angle of the three-phase load current input from the DQ conversion unit 9 using the current phase angle compensation value provided from the parameter stored in the memory, and the phase angle is New active power reference value (Pref) and reactive power reference value (Qref) are calculated using the compensated 3-phase load current and 3-phase load voltage input from the DQ converter (9), and effective when the active power of the inverter increases. In order to lower the voltage frequency output from the inverter using the power reference value (Pref), the difference between the active power reference value (Pref) and the active power reference value (Pm) of other inverters is proportionally integrated (Kp+Ki/s) and the above In order to lower the voltage output from the inverter using the reactive power reference value when the active power droop reference signal (PdrpRef) is applied to the difference between the active power reference value and the droop factor (Kpdrp). , The difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of other inverters is proportionally integrated (Kp+Ki/s) and the difference between the reactive power reference value (Qref) and the droop factor (Kqdrp) applied Is generated as a reactive power droop reference signal QdrpRef (S520).

In addition, the synchronization signal generation unit 7 is a three-phase bypass voltage synchronization signal (ThetaByp, ThetaLd) in phase with the DQ synchronization coordinate conversion signal (Vbqe) of the three-phase bypass voltage converted by the DQ conversion unit 9 Generates (S530).

In addition, the first Q-axis error calculator 14 calculates an error between the reactive power droop reference signal QdrpRef and the Q-axis voltage reference signal Vref (q axis) to calculate the synchronous Q-axis inverter reference voltage Vref (Viqe )) outputs a signal (S540).

In addition, the inverter voltage and current control unit 15 receives the synchronous Q-axis inverter reference voltage (Vref(Viqe)) signal and the synchronous D-axis inverter reference voltage (0(Vide)) signal, and the DQ stop and synchronous coordinate conversion signal ( The load voltage and load current of the inverter are controlled according to Vlqs, Vlds, Vlqe, Vlde, Ilqs Ilds, Ilqe Ilde), and outputs a Q-axis voltage control signal (Vqref) and a D-axis voltage control signal (Vdref) (S550).

In addition, the frequency control unit 17 receives the active power droop reference signal PdrpRef from the DQ synchronization coordinate conversion signal Vbde output from the synchronization signal generator 7 and the in-phase three-phase bypass voltage synchronization signal ThetaLd. It subtracts and outputs the droop application synchronization signal ThetaLd2 (S560).

In addition, the DQ inverse conversion unit 13 receives the Q-axis voltage control signal Vqref and the D-axis voltage control signal Vdref from the inverter voltage and current control unit 15, and receives a three-phase signal according to the control signal of the frequency control unit 17. It converts into a signal and outputs a command signal for adjusting the output voltage and frequency of the inverter (S570).

In addition, the SV PWM conversion unit 19 is a spatial vector pulse width modulated signal (SV) for switching the IGBT (Insulated Gate Bipolar Transistor) of the IGBT power conversion unit 3 to the command signal output from the DQ inverse conversion unit 13 PWM: Space Vector Pulse Width Modulation) and output to the IGBT power conversion unit 3 (S580).

7 is a flowchart illustrating an operation process of a V/F parallel droop control unit according to an embodiment of the present invention.

Referring to FIG. 7, in the V/F parallel drop control unit 11 according to an embodiment of the present invention, the PQ conversion unit 21 includes a DQ for a three-phase load voltage and a three-phase load current from the DQ conversion unit 9. The synchronous coordinate conversion signal (Vlqe, Vlde, Ilqe Ilde) is received and the active power (P) and reactive power (Q) values supplied to the load are calculated (S610).

In addition, the phase error compensation unit 23 uses the current phase angle compensation value provided from the parameter stored in the memory to create a parallel droop control signal, and the phase of the three-phase load current received from the DQ converter 9 The angle is compensated, and a new active power reference signal (Pref) and a reactive power reference signal (Qref) are calculated using the three-phase load current for which the phase angle is compensated and the three-phase load voltage transmitted from the DQ converter 9. (S620).

In addition, the droop signal generation unit 25 uses the active power reference value Pref to lower the voltage frequency output from the inverter when the active power of the inverter increases, so that the active power reference value Pref is different from the active power of the inverter. Proportional integration (Kp+Ki/s) of the difference of the reference value (Pm) and the value of applying the droop coefficient (Kpdrp) to the difference value of the reference value of active power are generated as the active power droop reference signal (PdrpRef), and the inverter is invalidated. In order to lower the voltage output from the inverter by using the reactive power reference value when the power is increased, the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of other inverters is proportionally integrated (Kp+Ki/s). A value obtained by applying the droop coefficient Kqdrp to the difference value between the reactive power reference value Qref and the reactive power reference value Qref is generated as a reactive power droop reference signal QdrpRef (S630).

8 is a flowchart illustrating an operation process of a droop signal generator in a V/F parallel droop controller according to an embodiment of the present invention.

Referring to FIG. 8, in the V/F parallel droop control unit 11 according to an embodiment of the present invention, the droop signal generation unit 25 includes the second error calculator 31 of an inverter different from the active power reference value Pref. The error of the active power reference value Pm is calculated (S710).

In addition, the first-order proportional integrator 32 performs a first-order proportional integration (Kp+Ki/s) of the value output from the second error calculator 31 (S720).

In addition, the third error calculator 33 calculates an error between the first-order proportional integration value and the active power reference value Pref (S730).

In addition, the active power droop application unit 34 generates an active power droop reference signal PdrpRef by applying the active power droop coefficient Kpdrp to the value output from the third error calculator 33 (S740).

Further, the fourth error calculator 35 calculates an error between the reactive power reference value Qref and the reactive power reference value Qm of another inverter (S750).

In addition, the second-order proportional integrator 36 performs a second-order proportional integration (Kp+Ki/s) of the value output from the fourth error calculator 35 (S760).

In addition, the fifth error calculator 37 calculates an error between the second-order proportional integration value and the reactive power reference value Qref (S770).

In addition, the reactive power droop application unit 38 applies the reactive power droop coefficient Kqdrp to the value output from the fifth error calculator 37 to generate the reactive power droop reference signal QdrpRef (S780).

On the other hand, in a UPS inverter load, especially a nonlinear load (rectifier), the inverter output voltage causes distortion. This can adversely affect load-side equipment, including equipment, and cause unexpected problems. Therefore, in order to improve the quality of inverter power, a resonance controller with infinite gain for a fixed frequency in a three-phase stationary coordinate system is applied as a harmonic compensator to compensate and supply the harmonic current required by the inverter load, thereby improving the distortion ratio of the inverter output voltage. I can. Accordingly, the present invention is simpler than a conventional harmonic compensator (repetition controller or FFT) to implement a formula and gain setting, and stably operates in a dynamic load with fast response.

9A and 9B are flowcharts illustrating an operation process of the inverter voltage and current controller according to an embodiment of the present invention.

4, 9A and 9B, in the inverter voltage current control unit 15 according to an embodiment of the present invention, the first coordinate axis conversion unit 41 is synchronized with the synchronous Q-axis inverter reference voltage Vref (ViqeCmd). The synchronous axis coordinates for the axis inverter reference voltage 0 (VideCmd) are converted to the stationary axis coordinates, and the Q-axis load reference voltage (Vlqs_ref) and the D-axis load reference voltage (Vlds_ref) are output (S801).

Further, the sixth error calculator 42 calculates an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs (S802).

In addition, the Q-axis fundamental wave compensator 43 compensates the Q-axis fundamental wave by controlling the error signal output from the sixth error calculator 42 according to Equation 3 below (S803).

는 기본파 공진 보상값을 나타내고,

는 비례 이득을 나타내며,

는 공진 이득을 나타내며,

는 대역 주파수를 나타내며,

는 기본 주파수를 나타낸다.In Equation 3,

Represents the fundamental wave resonance compensation value,

Represents the proportional gain,

Represents the resonance gain,

Represents the band frequency,

Represents the fundamental frequency.

Further, the seventh error calculator 44 calculates an error between the Q-axis stop axis inverter voltage Vlqs and the reference level voltage 0 (S804).

In addition, the fifth harmonic compensator 1 45 compensates for the fifth harmonic by controlling the error signal output from the seventh error calculator 44 by proportional resonance (PR) control according to Equation 4 below (S805).

는 고조파 공진 보상값을 나타내고,

는 공진 이득을 나타내며,

는 대역 주파수를 나타내며,

는 고조파 주파수를 나타낸다.In Equation 4,

Represents the harmonic resonance compensation value,

Represents the resonance gain,

Represents the band frequency,

Represents the harmonic frequency.

Further, the eighth error calculator 46 calculates an error between the stationary axis inverter voltage Vlqs and the reference level voltage 0 (S806).

In addition, the 7th harmonic compensator 1 47 performs proportional resonance (PR) control on the error signal output from the 8th error calculator 46 according to Equation 4 to compensate for the 7th harmonic (S807).

In addition, the ninth adder 48 adds the fifth harmonic-compensated value output from the fifth harmonic compensator 1 (45) and the seventh harmonic-compensated value output from the seventh harmonic compensator 1 (47). (S808).

In addition, the tenth adder 49 includes a primary added value output from the ninth adder 48, a Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 43, and a Q-axis load current All of the values IIqs are added secondarily (S809).

Further, the eleventh adder 50 thirdly adds the second-added value output from the tenth adder 49 and the Q-axis inverter current value Iiqs (S810).

Further, the twelfth error calculator 51 calculates an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds (S811).

In addition, the D-axis fundamental wave compensator 52 compensates the D-axis fundamental wave by controlling the error signal output from the twelfth error calculator 51 according to Equation 3 in proportional resonance (PR) (S812).

Further, the thirteenth error calculator 53 calculates an error between the D-axis stop axis inverter voltage Vlds and the reference level voltage 0 (S813).

In addition, the fifth harmonic compensator 2 54 compensates for the fifth harmonic by controlling the error signal output from the thirteenth error calculator 53 by proportional resonance (PR) control according to Equation 4 (S814).

Further, the 14th error calculator 55 calculates an error between the D-axis stop axis inverter voltage Vlqs and the reference level voltage 0 (S815).

In addition, the 7th harmonic compensator 2 56 performs proportional resonance (PR) control on the error signal output from the 14th error calculator 55 according to Equation 4 to compensate for the 7th harmonic (S816).

In addition, the fifteenth adder 57 adds the fifth harmonic-compensated value output from the fifth harmonic compensator 2 (54) and the seventh harmonic-compensated value output from the seventh harmonic compensator 2 (56) by the fourth order. (S817).

In addition, the sixteenth adder 58 includes a fourth-order added value output from the fifteenth adder 57, a Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 52, and a D-axis load current. All the values IIds are added 5th order (S818).

Further, the seventeenth adder 59 adds the fifth-added value output from the sixteenth adder 58 and the D-axis inverter current value Iids sixth order (S819).

In addition, the second coordinate axis conversion unit 60 synchronizes the stop axis coordinates of the third-added signal output from the eleventh adder 50 and the sixth-added signal output from the seventeenth adder 59. Converts to coordinates (S820).

In addition, the Q-axis current controller 61 controls the current in a proportional integration (Kp+Ki/s) method on the Q-axis signal output from the second coordinate axis conversion unit 60 to provide a Q-axis voltage control signal (Vqref). Output (S821).

In addition, the D-axis current controller 62 controls the current in a proportional integration (Kp+Ki/s) method on the D-axis signal output from the second coordinate axis conversion unit 60 to provide a D-axis voltage control signal (Vdref). Output (S822).

On the other hand, the first unit inverter 1010 to the Nth unit inverter 1020 may calculate the power deviation compensation (Perr, Qerr) according to the following equation (5).

In Equation 5, Perr represents the active power deviation compensation value, Pref (Pm) represents the master active power, Pref represents the active power, Qerr represents the reactive power deviation compensation value, and Qref (Qm) represents the master invalid power. Represents power, and Qref represents reactive power.

10A to 10C are flowcharts illustrating an operation process of the inverter voltage and current controller according to another embodiment of the present invention.

5 and 10A to 10C, in the inverter voltage and current control unit 15 according to another embodiment of the present invention, the first coordinate axis conversion unit 41 is a first coordinate axis conversion unit 41 is a synchronous Q-axis inverter Convert the synchronous axis coordinates for the reference voltage Vref (ViqeCmd) and the synchronous D-axis inverter reference voltage 0 (VideCmd) into the stop axis coordinates, and output the Q-axis load reference voltage (Vlqs_ref) and the D-axis load reference voltage (Vlds_ref) ( S901).

Further, the sixth error calculator 42 calculates an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs (S902).

In addition, the Q-axis fundamental wave compensator 43 compensates the Q-axis fundamental wave by controlling the error signal output from the sixth error calculator 42 in proportional resonance (PR) according to Equation 3 (S903).

Further, the seventh error calculator 44 calculates an error between the Q-axis stop axis inverter voltage Vlqs and the reference level voltage 0 (S904).

In addition, the fifth harmonic compensator 1 45 compensates for the fifth harmonic by controlling the error signal output from the seventh error calculator 44 by proportional resonance (PR) control according to Equation 4 (S905).

Further, the eighth error calculator 46 calculates an error between the stationary axis inverter voltage Vlqs and the reference level voltage 0 (S906).

In addition, the 7th harmonic compensator 1 47 compensates for the 7th harmonic by controlling the error signal output from the 8th error calculator 46 according to Equation 4 in proportional resonance (PR) (S907).

In addition, the ninth adder 48 adds the fifth harmonic-compensated value output from the fifth harmonic compensator 1 (45) and the seventh harmonic-compensated value output from the seventh harmonic compensator 1 (47). (S908).

In addition, the tenth adder 49 includes a primary added value output from the ninth adder 48, a Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 43, and a Q-axis load current All values (IIqs) are added by the second order (S909).

Further, the eleventh adder 50 thirdly adds the second-added value output from the tenth adder 49 and the Q-axis inverter current value Iiqs (S910).

Further, the twelfth error calculator 51 calculates an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds (S911).

In addition, the D-axis fundamental wave compensator 52 compensates the D-axis fundamental wave by controlling the error signal output from the twelfth error calculator 51 according to Equation 3 in proportional resonance (PR) (S912).

Further, the thirteenth error calculator 53 calculates an error between the D-axis stop axis inverter voltage Vlds and the reference level voltage 0 (S913).

In addition, the fifth harmonic compensator 2 54 compensates for the fifth harmonic by controlling the error signal output from the thirteenth error calculator 53 by proportional resonance (PR) control according to Equation 4 (S914).

Further, the 14th error calculator 55 calculates an error between the D-axis stop axis inverter voltage Vlqs and the reference level voltage 0 (S915).

In addition, the 7th harmonic compensator 2 56 performs proportional resonance (PR) control on the error signal output from the 14th error calculator 55 according to Equation 4 to compensate for the 7th harmonic (S916).

In addition, the fifteenth adder 57 adds the fifth harmonic-compensated value output from the fifth harmonic compensator 2 (54) and the seventh harmonic-compensated value output from the seventh harmonic compensator 2 (56) by the fourth order. (S917).

In addition, the 16th adder 58 includes a fourth-order added value output from the 15th adder 57, a D-axis fundamental wave compensated value output from the D-axis fundamental wave compensator 52, and a D-axis load current. All the values (IIds) are added 5th order (S918).

Further, the seventeenth adder 59 adds the fifth-added value output from the sixteenth adder 58 and the D-axis inverter current value Iids sixth order (S919).

In addition, the second coordinate axis conversion unit 60 synchronizes the stop axis coordinates of the third-added signal output from the eleventh adder 50 and the sixth-added signal output from the seventeenth adder 59. Convert to coordinates (S920).

In addition, the Q-axis current controller 61 controls the current in a proportional integration (Kp+Ki/s) method on the Q-axis signal output from the second coordinate axis conversion unit 60 to provide a Q-axis voltage control signal (Vqref). Output (S921).

In addition, the D-axis current controller 62 controls the current in a proportional integration (Kp+Ki/s) method on the D-axis signal output from the second coordinate axis conversion unit 60 to provide a D-axis voltage control signal (Vdref). Output (S922).

Further, the eighteenth error calculator 63 calculates an error between the synchronous Q-axis inverter reference voltage ViqeCmd and the synchronous Q-axis load voltage Vlqe of the DQ synchronous coordinate conversion value (S923).

Further, the Q-axis repetition controller 64 repeatedly controls the Q-axis error signal output from the eighteenth error calculator 63 (S924).

In addition, the nineteenth adder 65 adds the Q-axis signal output from the Q-axis current controller 61 and the Q-axis error signal output from the Q-axis repeat controller 64 to provide a Q-axis voltage control signal (Vqref). Is output (S925).

Further, the twentieth error calculator 66 calculates an error between the synchronous D-axis inverter reference voltage VideCmd and the synchronous D-axis load voltage Vlde of the DQ synchronous coordinate conversion value (S926).

Further, the D-axis repetition controller 67 repeatedly controls the D-axis error signal output from the twentieth error calculator 66 (S927).

In addition, the 21st adder 68 adds the D-axis signal output from the D-axis current controller 62 and the D-axis error signal output from the D-axis repetition controller 67 to provide a D-axis voltage control signal (Vdref). Is output (S928).

Accordingly, the inverter voltage-current control unit 15 according to the present invention can obtain an improved waveform as shown in FIGS. 11A to 11D by compensating for the power deviation. 11A is a graph showing a voltage waveform according to resonance control during a nonlinear load of an inverter voltage current controller according to an embodiment of the present invention. 11B is a graph showing the results of analyzing the voltage waveform distortion of FIG. 10A. In Fig. 11b, the load current includes a nonlinear harmonic current, and the output voltage waveform distortion at this time shows the state of the 3rd, 5th, 7th, 11th, and 13th order, and it can be seen that the lower the better, the better. have. Fig. 11c is a graph showing when the inductor value is the same (virtual deviation zero (0)) at the output side, the fast graph in Fig. 11c shows that the power deviation is compensated, and the slow graph compensates for the power deviation. It can be seen that this is in the off state. 11D is a graph showing when the inductor values at the output side are not the same (virtual deviation insertion) and are different. In FIG. 10D, it can be seen that the fast graph shows that the compensation of the power deviation is turned on, and the slow graph shows that the compensation of the power deviation is turned off. That is, a slight variation in power appears.

12 is a diagram illustrating an operation flow diagram for explaining a method of redundantly operating a V/F droop parallel operation inverter according to an embodiment of the present invention.

Referring to FIG. 12, in the V/F droop parallel operation inverter redundancy apparatus 1000 according to an embodiment of the present invention, the first unit inverter 1010 converts the applied DC power into AC power and performs a PWM pulse of the AC power. Filters the signal, converts it into a sinusoidal wave, and supplies it to the load, and the three-phase bypass voltage (VBYP) applied from the bypass line, the inverter current (IID), the three-phase load current (ILD), and the three-phase load voltage (VLD) Is converted into a DQ synchronous coordinate value, and the three-phase load current (ILD) and three-phase load voltage (VLD) for the DQ synchronous coordinate value are converted into active power (P) and reactive power (Q) values and compensated to The reference value Pref and the reactive power reference value Qref are calculated and output to the second unit inverter 1020 (S1010).

Subsequently, the second unit inverter 1020 uses the active power reference value (Pref) and the reactive power reference value (Qref) applied from the first unit inverter 1010 to the relative active power reference value (Pm) and the relative reactive power reference value (Qm), respectively. As a result, the difference between the relative active power reference value (Pm) and the active power reference value (Pref) is proportionally integrated (Kp+Ki/s) and the difference between the active power reference value (Pref) and the active power droop coefficient (Kpdrp). ) Is applied to the active power droop reference signal (PdrpRef), and the difference between the relative reactive power reference value (Qm) and the reactive power reference value (Qref) is proportionally integrated (Kp+Ki/s) and reactive power The output voltage frequency, output voltage and output current are controlled by generating a value obtained by applying the reactive power droop factor (Kqdrp) to the difference value of the reference value (Qref) as a reactive power droop reference signal (QdrpRef), and controlling the output voltage frequency, output voltage and output current, and controlling the active power reference value (Pref ) And the reactive power reference value (Qref) are output to the next unit inverter (S1020).

Thereafter, the Nth inverter 1030 uses the active power reference value (Pref) and the reactive power reference value (Qref) applied from the N-1th inverter as a relative active power reference value (Pm) and a relative reactive power reference value (Qm), respectively. Thus, the difference between the relative active power reference value (Pm) and the active power reference value (Pref) is proportionally integrated (Kp+Ki/s) and the difference between the active power reference value (Pref) and the active power droop coefficient (Kpdrp). The applied value is generated as the active power droop reference signal (PdrpRef), and the difference between the relative reactive power reference value (Qm) and the reactive power reference value (Qref) is proportionally integrated (Kp+Ki/s) and the reactive power reference value A value obtained by applying the reactive power droop coefficient (Kqdrp) to the difference value of (Qref) is generated as a reactive power droop reference signal (QdrpRef) to control the output voltage frequency, output voltage, and output current (S1030).

Here, the V/F droop parallel operation inverter redundancy device 1000 excludes inverters that do not operate when at least one (m) of the first to the Nth inverter 1010 to the Nth inverter 1030 is not operated. And the remaining inverters operate by distributing power uniformly.

The first to the Nth inverter 1010 to the Nth inverter 1030, the active power deviation compensation (Perr) and reactive power deviation compensation (Qerr) values according to Equation 5 above with respect to the power deviation compensation (Perr, Qerr). By calculating, each unit inverter compensates for the active power and the reactive power to the compensation value calculated as described above, so that each unit inverter can equalize the load burden.

As described above, in the present invention, when two or more inverters are connected in parallel and a load is commonly connected to two or more inverters, when the active power of the inverter increases, the voltage frequency output from the inverter is decreased to reduce the increased active power. When the reactive power of the inverter is lowered, the increased reactive power can be lowered by lowering the voltage output from the inverter.

As a result, by keeping the active power and reactive power of the inverter constant, it is possible to suppress the output of overcurrent from the inverter due to the circulating current that may occur due to the active power deviation and the reactive power deviation between the inverters.

In addition, according to the present invention, when a plurality of inverters are operated in parallel, the deviation of active power and reactive power that may be generated from each inverter is more quickly compensated, thereby stabilizing the parallel operation state of the inverter.

Therefore, when two or more inverters are operated in parallel, it is possible to compensate for the unbalance of the load voltage due to the unbalance of the load, and compensate for the deviation between the active and reactive power when controlling the V/F droop (Voltage/Frequency Droop). Thus, the load sharing characteristics of the inverter can be improved.

As described above, according to the present invention, when at least one of the first to Nth inverters (m) is not operated, except for the non-operated inverters (Nm), the remaining inverters uniformly distribute power. Thus, by equally adjusting the load sharing ratio between two or more inverters connected in parallel, V, which eliminates the deviation between active power and reactive power of each inverter, and suppresses circulating current that may be caused by power deviation between inverters. /F droop parallel operation inverter redundancy device and method can be realized.

In the above, the embodiments of the present invention have been mainly described, but various changes or modifications can be made at the level of a person skilled in the art. Such changes and modifications may be said to belong to the present invention as long as they do not depart from the scope of the technical idea provided by the present invention. Therefore, the scope of the present invention should be determined by the claims set forth below.

1000: V/F droop parallel operation inverter redundancy device
1010: Unit 1 inverter
1020: Unit 2 inverter
1030: Unit 3 inverter
100: each unit inverter 110: inverter stage
120: inverter control unit 1: inverter switch
3: IGBT power conversion unit 4: Bypass switch
5: LC filter unit 6: bypass line
7: synchronization signal generation unit 9: DQ conversion unit
11: V/F parallel droop control unit 13: DQ inverse transform unit
14: first Q-axis error calculator 15: inverter voltage and current control unit
17: frequency control unit 19: SV PWM conversion unit
21: PQ conversion unit 23: phase error compensation unit
25: droop signal generator 31: second error calculator
32: 1st proportional integrator 33: 3rd error calculator
34: active power droop application unit 35: fourth error calculator
36: 2nd proportional integrator 37: 5th error calculator
38: reactive power droop application unit 41: first coordinate axis conversion unit
42: 6th error calculator 43: Q-axis fundamental wave compensator
44: 7th error calculator 45: 5th harmonic compensator 1
46: 8th error calculator 47: 7th harmonic compensator 1
48: 9th adder 49: 10th adder
50: 11th adder 51: 12th error calculator
52: D-axis fundamental wave compensator 53: 13th error calculator
54: 5th harmonic compensator 2 55: 14th error calculator
56: 7th harmonic compensator 2 57: 15th adder
58: 16th adder 59: 17th adder
60: second coordinate axis conversion unit 61: Q-axis current controller
62: D-axis current controller 63: 18th error calculator
64: Q axis repeat controller 65: 19th adder
66: 20th error calculator 67: D-axis repeat controller
68: 21st adder 73: frequency subtractor
79: load voltage primary DQ conversion unit 80: load voltage secondary DQ conversion unit
81: bypass voltage DQ conversion unit 83: load current primary DQ conversion unit
84: load current secondary DQ conversion unit 85: inverter current primary DQ conversion unit
86: inverter current secondary DQ conversion unit 87: first phase locked loop
89: 2nd phase locked loop

Claims (19)

V/F droop parallel operation inverter redundancy device in which two or more inverters are connected in parallel.
The applied DC power is converted into AC power, the PWM pulse signal of the AC power is filtered, converted into a sinusoidal wave, and supplied to the load, and the three-phase bypass voltage (VBYP) applied from the bypass line, and the inverter current (IID) , 3-phase load current (ILD) and 3-phase load voltage (VLD) are DQ converted to generate a DQ synchronization coordinate signal, and DQ synchronization coordinates for the 3-phase load current (ILD) and the 3-phase load voltage (VLD) PQ converts the signal to generate active power (P) and reactive power (Q) and compensates for the first active power reference value (Pref) and the first reactive power reference value (Qref) to be calculated and output to the second unit inverter. Exhalation inverter;
The relative active power reference value by using the first active power reference value (Pref) and the first reactive power reference value (Qref) applied from the first unit inverter as the relative active power reference value (Pm) and the relative reactive power reference value (Qm), respectively. The active power droop coefficient (Kpdrp) is proportionally integrated (Kp+Ki/s) of the difference between (Pm) and its second active power reference value (Pref) and the difference between the second active power reference value (Pref). The applied value is generated as an active power droop reference signal (PdrpRef), and the difference between the relative reactive power reference value (Qm) and its second reactive power reference value (Qref) is proportionally integrated (Kp+Ki/s) and the above The value obtained by applying the reactive power droop coefficient (Kqdrp) to the difference value of the second reactive power reference value (Qref) is generated as a reactive power droop reference signal (QdrpRef) to control the output voltage frequency, output voltage, and output current. A second unit inverter for outputting a second reference value of active power Pref and a second reference value of reactive power Qref to the next unit inverter; And
Using the N-1th active power reference value (Pref) and the N-1th reactive power reference value (Qref) applied from the N-1th inverter as the relative active power reference value (Pm) and the relative reactive power reference value (Qm), respectively, Active power droop on the difference between the relative active power reference value (Pm) and the Nth active power reference value (Pref) proportionally integrated (Kp+Ki/s) and the Nth active power reference value (Pref) The value to which the coefficient (Kpdrp) is applied is generated as an active power droop reference signal (PdrpRef), and the difference between the relative reactive power reference value (Qm) and its Nth reactive power reference value (Qref) is proportionally integrated (Kp+Ki/s). ), a value obtained by applying a reactive power droop coefficient (Kqdrp) to the difference between one value and the Nth reactive power reference value (Qref) is generated as a reactive power droop reference signal (QdrpRef), and the output voltage frequency, output voltage, and output current are Including; Nth unit inverter to control
When at least one (m) of the first to the Nth inverter is not operated, except for the non-operated inverters (Nm), the remaining inverters are operated by uniformly distributing power. Droop parallel operation inverter redundancy device.
The method of claim 1,
The first to the Nth inverters calculate power deviation compensation values (Perr, Qerr) according to the following equation, V/F droop parallel operation inverter redundancy.

Here, Perr represents the active power deviation compensation value, Pref (Pm) represents the master active power, Pref represents the active power reference value, Qerr represents the reactive power deviation compensation value, and Qref (Qm) represents the master reactive power. And Qref represents the reactive power reference value.
The method of claim 1,
At least one inverter of the first unit to the Nth unit inverter,
Converts the applied DC power into AC power, filters the PWM pulse signal of the AC power, converts it into a sine wave form and supplies it to a load, and receives 3-phase AC power from the bypass line when the inverter fails An inverter stage supplying the load to the load; And
DQ synchronization coordinates by DQ conversion of the three-phase bypass voltage (VBYP) applied from the bypass line, the inverter current (IID) detected from the inverter stage, the three-phase load current (ILD), and the three-phase load voltage (VLD). Generated as a signal, and PQ converted and compensated for the DQ synchronous coordinate signal for the three-phase load current (ILD) and the three-phase load voltage (VLD) to calculate the active power reference value (Pref) and the reactive power reference value (Qref). And, the active power droop coefficient is the difference between the active power reference value (Pref) and the active power reference value (Pm) of another inverter proportionally integrated (Kp+Ki/s) and the active power reference value (Pref). Kpdrp) is applied to the active power droop reference signal (PdrpRef), and the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of another inverter is proportionally integrated (Kp+Ki/s). An inverter control unit that generates a value obtained by applying a reactive power droop coefficient (Kqdrp) to the difference value of the reactive power reference value (Qref) as a reactive power droop reference signal (QdrpRef) to control the output voltage frequency, output voltage, and current of the inverter ;
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 3,
The inverter stage,
An IGBT power converter (3) converting DC power applied to the inverter into AC power and outputting an inverter current according to a PWM pulse signal;
An LC filter unit 5 filtering the PWM pulse signal output from the IGBT power conversion unit 3 and converting it into a sine wave form;
An inverter switch (1) connected to the output terminal of the LC filter unit (5) to switch the filtered inverter current to flow to a load; And
A bypass switch (4) connected to the output terminal of the inverter switch (1) to switch the supply of the three-phase AC power input from the bypass line to the load side;
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 4,
The inverter control unit,
The inverter current (IID) output from the IGBT power conversion unit (3), and the three-phase load voltage (VLD) and the three-phase load current (ILD) output from the LC filter unit 5 are converted to DQ by primary DQ conversion. A stop coordinate conversion signal (Vlqs, Vlds, Ilqs Ilds, Iiqs Iids) is generated, and the three-phase bypass voltage (VBYP) applied from the bypass line is applied to the synchronization signal (ThetaByp) provided from the synchronization signal generator 7 According to the first DQ conversion, a DQ synchronous coordinate conversion signal (Vbde) of the three-phase bypass voltage is generated, and the DQ stop coordinate conversion signals (Vlqs, Vlds, Ilqs Ilds, Iiqs Iids) are provided from the frequency control unit 17. A DQ conversion unit 9 for generating and outputting DQ synchronization coordinate conversion signals (Vlqe, Vlde, Ilqe, Ilde, Iiqe, Iide) by performing a second DQ conversion in accordance with the drop applied synchronization signal (ThetaLd2);
A synchronization signal generator (7) that generates a DQ synchronization coordinate conversion signal (Vbde) of the three-phase bypass voltage converted by the DQ conversion unit (9) and a three-phase bypass voltage synchronization signal (ThetaByp, ThetaLd) in phase. );
Q-axis first error calculator (14) calculating an error between the reactive power droop reference signal (QdrpRef) and the Q-axis voltage reference signal (Vref (q axis)) and outputting a synchronous Q-axis inverter reference voltage Vref (ViqeCmd) signal (14) );
The synchronous Q-axis inverter reference voltage signal (Vref(ViqeCmd)) and the synchronous D-axis inverter reference voltage signal (0(VideCmd)) are received, and the DQ synchronous coordinate conversion signal (Vlqe, Vlde, Ilqe, Ilde) An inverter voltage and current controller 15 for controlling a load voltage and a load current of the inverter to output a Q-axis voltage control signal Vqref and a D-axis voltage control signal Vdref;
The inverter voltage and current control unit 15 receives the Q-axis voltage control signal Vqref and the D-axis voltage control signal Vdref, converts it into a three-phase signal according to the control signal of the frequency control unit 17, A DQ inverse transform unit 13 for outputting a command signal for adjusting an output voltage and a frequency;
The command signal output from the DQ inverse conversion unit 13 is converted into a space vector pulse width modulation signal (SV PWM) for switching the IGBT (Insulated Gate Bipolar Transistor) of the IGBT power conversion unit 3 SV PWM conversion unit 19 to convert;
The phase angle of the three-phase load current input from the DQ converter 9 is compensated by using the current phase angle compensation value provided from the parameter stored in the memory, and the phase angle is compensated for the three-phase load current and the DQ converter ( 9) The new active power reference value (Pref) and the reactive power reference value (Qref) are calculated using the three-phase load voltage input from 9), and the active power reference value (Pref) is used when the active power of the inverter is increased. In order to lower the voltage frequency output from the inverter, the difference between the active power reference value (Pref) and the active power reference value (Pm) of another inverter is proportionally integrated (Kp+Ki/s) and the difference between the active power reference value. In order to generate a value to which an active power droop coefficient (Kpdrp) is applied as an active power droop reference signal (PdrpRef), and to lower the voltage output from the inverter by using the reactive power reference value when the reactive power of the inverter is increased, the Reactive power droop coefficient (Kqdrp) is proportionally integrated (Kp+Ki/s) of the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of another inverter and the difference between the reactive power reference value (Qref). A voltage/frequency (V/F) parallel droop control unit 11 that generates the applied value as a reactive power droop reference signal QdrpRef; And
The active power droop reference signal PdrpRef is subtracted from the three-phase bypass voltage synchronization signal ThetaLd output from the synchronization signal generator 7 to generate a droop application synchronization signal ThetaLd2, and the DQ conversion unit ( 9) and a frequency control unit 17 outputting to the DQ inverse transform unit 13;
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 5,
The V/F parallel droop control unit,
A DQ synchronization coordinate conversion signal (Vlqe, Vlde, Ilqe Ilde) for a three-phase load voltage and a three-phase load current is received from the DQ converter 9, and the active power P and the reactive power Q are supplied to the load. ) A PQ conversion unit 21 that calculates a value;
To create a parallel droop control signal, the phase angle of the three-phase load current input from the DQ converter 9 is compensated using the current phase angle compensation value provided from the parameter stored in the memory, and the phase angle is compensated. A phase error compensating unit 23 for calculating the active power reference value Pref and the reactive power reference value Qref using a 3-phase load current and a 3-phase load voltage transmitted from the DQ converter 9; And
In order to lower the voltage frequency output from the inverter by using the active power reference value Pref when the active power of the inverter is increased, the difference between the active power reference value Pref and the active power reference value Pm of another inverter is determined. A value obtained by applying an active power droop factor (Kpdrp) to the difference between the proportional integral (Kp+Ki/s) value and the active power reference value is generated as the active power droop reference signal (PdrpRef), and the reactive power of the inverter is In order to lower the voltage output from the inverter by using the reactive power reference value when it is increased, the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of another inverter is proportionally integrated (Kp+Ki/s). A droop signal generator 25 for generating a value obtained by applying a reactive power droop coefficient Kqdrp to a difference between a value and the reactive power reference value Qref as the reactive power droop reference signal QdrpRef;
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 6,
The droop signal generation unit 25,
A second error calculator 31 for calculating an error between the active power reference value Pref and the active power reference value Pm of another inverter;
A first-order proportional integrator (32) for first-order proportional integration of the value output from the second error calculator (31);
A third error calculator (33) calculating an error between the first proportional integral value and the active power reference value (Pref);
An active power droop applying unit 34 for generating an active power droop reference signal PdrpRef by applying an active power droop coefficient Kpdrp to the value output from the third error calculator 33;
A fourth error calculator 35 for calculating an error between the reactive power reference value Qref and the reactive power reference value Qm of another inverter;
A second-order proportional integrator 36 for second-order proportional integration (Kp+Ki/s) of the value output from the fourth error calculator (35);
A fifth error calculator (37) calculating an error between the second-order proportional integration value and the reactive power reference value (Qref); And
A reactive power droop applying unit 38 for generating a reactive power droop reference signal QdrpRef by applying a reactive power droop coefficient Kqdrp to the value output from the fifth error calculator 37;
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 5,
The inverter voltage current control unit 15,
The synchronous axis coordinates for the synchronous Q-axis inverter reference voltage signal (Vref(ViqeCmd)) and the synchronous D-axis inverter reference voltage signal (0(VideCmd)) are converted into stationary axis coordinates, and the Q-axis load reference voltage (Vlqs_ref) and A first coordinate axis conversion unit 41 outputting a D-axis load reference voltage Vlds_ref;
A sixth error calculator 42 for calculating an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs;
A Q-axis fundamental wave compensator 43 for compensating the Q-axis fundamental wave by controlling the error signal output from the sixth error calculator 42 by proportional resonance (PR) control;
A seventh error calculator 44 for calculating an error between the Q-axis stationary axis inverter voltage Vlqs and a reference level voltage 0;
A fifth harmonic compensator 1 (45) for compensating the fifth harmonic by controlling the error signal output from the seventh error calculator 44 by proportional resonance (PR) control;
An eighth error calculator (46) for calculating an error between the Q-axis stationary axis inverter voltage (Vlqs) and a reference level voltage (0);
A seventh harmonic compensator 1 47 for compensating for a seventh harmonic by controlling the error signal output from the eighth error calculator 46 by proportional resonance (PR) control;
A ninth adder (48) for first adding the 5th harmonic-compensated value output from the 5th harmonic compensator 1 (45) and the 7th harmonic compensation value output from the 7th harmonic compensator 1 (47) ;
The first added value output from the ninth adder 48, the Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 43, and the Q-axis load current value (Ilqs) are all 2 A tenth adder 49 for adding the difference;
An eleventh adder (50) for thirdly adding the second-added value output from the tenth adder (49) and a Q-axis inverter current value (Iiqs);
A twelfth error calculator 51 for calculating an error between the D-axis load reference voltage Vlds_ref and the D-axis stop-axis load inverter voltage Vlds;
A D-axis fundamental wave compensator 52 for compensating the D-axis fundamental wave by controlling the error signal output from the twelfth error calculator 51 by proportional resonance (PR) control;
A thirteenth error calculator (53) calculating an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0);
A fifth harmonic compensator 2 (54) for compensating the fifth harmonic by controlling the error signal output from the thirteenth error calculator (53) by proportional resonance (PR) control;
A 14th error calculator (55) for calculating an error between the D-axis stationary axis inverter voltage (Vlds) and a reference level voltage (0);
A 7th harmonic compensator 2 (56) for compensating the 7th harmonic by controlling the error signal output from the 14th error calculator (55) by proportional resonance (PR) control;
A fifteenth adder (57) for adding the fifth harmonic-compensated value output from the fifth harmonic compensator 2 (54) and the seventh harmonic-compensated value output from the seventh harmonic compensator 2 (56) by a fourth order ;
The fourth-order added value output from the fifteenth adder 57, the D-axis fundamental wave compensated value output from the D-axis fundamental wave compensator 52, and the D-axis load current value (IIds) are all 5 A sixteenth adder 58 for adding the difference;
A seventeenth adder (59) for adding the fifth-order added value output from the sixteenth adder (58) and the D-axis inverter current value (Iids) by a sixth order;
A second coordinate axis transformation for converting stationary axis coordinates of the third-added signal output from the eleventh adder (50) and the sixth-added signal output from the seventeenth adder (59) into synchronous axis coordinates Part 60;
A Q-axis current controller 61 for outputting a Q-axis voltage control signal Vqref by controlling the current in a proportional integration (Kp+Ki/s) method of the Q-axis signal output from the second coordinate-axis conversion unit 60; And
A D-axis current controller 62 for outputting a D-axis voltage control signal Vdref by controlling the current in a proportional integration (Kp+Ki/s) method of the D-axis signal output from the second coordinate axis conversion unit 60;
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 5,
The inverter voltage current control unit 15,
The synchronous axis coordinates for the synchronous Q-axis inverter reference voltage signal (Vref(ViqeCmd)) and the synchronous D-axis inverter reference voltage signal (0(VideCmd)) are converted into stationary axis coordinates, and the Q-axis load reference voltage (Vlqs_ref) and A first coordinate axis conversion unit 41 outputting a D-axis load reference voltage Vlds_ref;
A sixth error calculator 42 for calculating an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs;
A Q-axis fundamental wave compensator 43 for compensating the Q-axis fundamental wave by controlling the error signal output from the sixth error calculator 42 by proportional resonance (PR) control;
A seventh error calculator 44 for calculating an error between the Q-axis stationary axis inverter voltage Vlqs and a reference level voltage 0;
A fifth harmonic compensator 1 (45) for compensating the fifth harmonic by controlling the error signal output from the seventh error calculator 44 by proportional resonance (PR) control;
An eighth error calculator (46) for calculating an error between the Q-axis stationary axis inverter voltage (Vlqs) and a reference level voltage (0);
A seventh harmonic compensator 1 47 for compensating for a seventh harmonic by controlling the error signal output from the eighth error calculator 46 by proportional resonance (PR) control;
A ninth adder (48) for first adding the 5th harmonic-compensated value output from the 5th harmonic compensator 1 (45) and the 7th harmonic compensation value output from the 7th harmonic compensator 1 (47) ;
The first added value output from the ninth adder 48, the Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 43, and the Q-axis load current value (Ilqs) are all 2 A tenth adder 49 for adding the difference;
An eleventh adder (50) for thirdly adding the second-added value output from the tenth adder (49) and a Q-axis inverter current value (Iiqs);
A twelfth error calculator 51 for calculating an error between the D-axis load reference voltage Vlds_ref and the D-axis stop-axis load inverter voltage Vlds;
A D-axis fundamental wave compensator 52 for compensating the D-axis fundamental wave by controlling the error signal output from the twelfth error calculator 51 by proportional resonance (PR) control;
A thirteenth error calculator (53) calculating an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0);
A fifth harmonic compensator 2 (54) for compensating the fifth harmonic by controlling the error signal output from the thirteenth error calculator (53) by proportional resonance (PR) control;
A 14th error calculator (55) for calculating an error between the D-axis stationary axis inverter voltage (Vlds) and a reference level voltage (0);
A 7th harmonic compensator 2 (56) for compensating the 7th harmonic by controlling the error signal output from the 14th error calculator (55) by proportional resonance (PR) control;
A fifteenth adder (57) for adding the fifth harmonic-compensated value output from the fifth harmonic compensator 2 (54) and the seventh harmonic-compensated value output from the seventh harmonic compensator 2 (56) by a fourth order ;
The fourth-order added value output from the fifteenth adder 57, the D-axis fundamental wave compensated value output from the D-axis fundamental wave compensator 52, and the D-axis load current value (IIds) are all 5 A sixteenth adder 58 for adding the difference;
A seventeenth adder (59) for adding the fifth-order added value output from the sixteenth adder (58) and the D-axis inverter current value (Iids) by a sixth order;
A second coordinate axis transformation for converting stationary axis coordinates of the third-added signal output from the eleventh adder (50) and the sixth-added signal output from the seventeenth adder (59) into synchronous axis coordinates Part 60;
A Q-axis current controller 61 for controlling the current in a proportional integration (Kp+Ki/s) method of the Q-axis signal output from the second coordinate-axis conversion unit 60; [[And]]
A D-axis current controller 62 for controlling a current in a proportional integration (Kp+Ki/s) method of the D-axis signal output from the second coordinate axis conversion unit 60;
An eighteenth error calculator (63) calculating an error between the synchronous Q-axis inverter reference voltage signal Vref(ViqeCmd) and the synchronous Q-axis load voltage Vlqe of the DQ synchronous coordinate conversion signal;
A Q-axis repetition controller 64 for repeatedly controlling a Q-axis error signal output from the eighteenth error calculator 63;
A 19th adder (65) for outputting a Q-axis voltage control signal (Vqref) by adding the Q-axis signal output from the Q-axis current controller (61) and the Q-axis error signal output from the Q-axis repeat controller (64). );
A twentieth error calculator (66) for calculating an error between the synchronous D-axis inverter reference voltage signal (VideCmd) and the synchronous D-axis load voltage (Vlde) of the DQ synchronous coordinate conversion signal;
A D-axis repetition controller 67 that repeatedly controls the D-axis error signal output from the twentieth error calculator (66); And
A 21st adder (68) for outputting a D-axis voltage control signal (Vdref) by adding the D-axis signal output from the D-axis current controller (62) and the D-axis error signal output from the D-axis repeat controller (67). );
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 5,
The frequency control unit 17,
The droop by subtracting the active power droop reference signal PdrpRef output from the V/F parallel droop control unit 11 from the three-phase bypass voltage synchronization signal ThetaLd output from the synchronization signal generator 7 A frequency subtractor 73 for generating an applied synchronization signal ThetaLd2 and outputting it to the DQ converter 9 and the DQ inverse converter 13;
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 5,
The synchronization signal generation unit 7,
A first-order phase locked loop 87 that outputs a first-order bypass synchronization signal ThetaByp synchronized with the DQ synchronization coordinate conversion signal Vbde of the three-phase bypass voltage converted by the DQ conversion unit 9 ( PLL: Phase Locked Loop); And
A second-order phase-locked loop (89) for outputting a second-order bypass synchronization signal (ThetaLd) in synchronization with the first-order bypass synchronization signal (ThetaByp) output from the first-order phase-locked loop (87);
V/F droop parallel operation inverter redundancy device comprising a.
The method of claim 5,
The DQ conversion unit 9,
The first DQ conversion of the load voltage to output the first DQ stop coordinate conversion signals (Vlqs, Vlds) by first DQ conversion (a, b) of the three-phase load voltage (VLD) output from the LC filter unit 5 Part 79;
The first DQ stop coordinate conversion signal (Vlqs, Vlds) converted by the load voltage first DQ conversion unit 79 is converted to the second DQ and output as the second DQ synchronous coordinate conversion signal (Vlqe, Vlde). Load voltage secondary DQ conversion unit 80;
A bypass voltage DQ converter 81 for converting the three-phase bypass voltage VBYP bypassed from the bypass line 6 to DQ and outputting a DQ synchronous coordinate conversion value Vbde;
First-order DQ conversion of the three-phase load current (ILD) output from the LC filter unit 5 as a first-order DQ conversion (a, b) and output as a first-order DQ stop coordinate conversion signal (Ilqs, Ilds) Part 83;
The primary DQ stop coordinate conversion value (Ilqs, Ilds) converted by the load current primary DQ conversion unit 83 is converted into the secondary DQ conversion value (Ilqe, Ilde) and output as the secondary DQ synchronous coordinate conversion value (Ilqe, Ilde). Load current secondary DQ conversion unit 84;
Inverter current primary DQ conversion for outputting primary DQ synchronous coordinate conversion values (Iiqs, Iids) by primary DQ conversion (a, b) of the 3-phase inverter current (IID) output from the IGBT power conversion unit 3 Part 85; And
The inverter current primary DQ conversion unit 85 converts the primary DQ synchronization coordinate conversion signals (Iiqs, Iids) converted to the secondary DQ conversion signals (Iiqs, Iids) to the secondary DQ synchronization coordinate conversion signals (Iiqe, Iide). Inverter current secondary DQ conversion unit 86;
V/F droop parallel operation inverter redundancy device comprising a.
V/F droop parallel operation inverter redundancy method in which two or more inverters are connected in parallel,
(A) The DC power applied by the No. 1 inverter is converted into AC power, the PWM pulse signal of the AC power is filtered, converted into a sinusoidal wave, and supplied to the load, and a three-phase bypass voltage applied from the bypass line ( VBYP), inverter current (IID), three-phase load current (ILD), and three-phase load voltage (VLD) are converted into a DQ synchronous coordinate signal by DQ conversion, and the three-phase load current (ILD) and the three-phase load voltage The DQ synchronization coordinate signal for (VLD) is PQ converted to generate active power (P) and reactive power (Q) and compensated to calculate the first active power reference value (Pref) and the first reactive power reference value (Qref). Outputting to the second unit inverter;
(B) The first active power reference value (Pref) and the first reactive power reference value (Qref) applied by the second unit inverter from the first unit inverter are used as a relative active power reference value (Pm) and a relative reactive power reference value (Qm), respectively. As a result, the difference between the relative active power reference value Pm and its second active power reference value Pref is proportionally integrated (Kp+Ki/s) and the difference between the second active power reference value Pref The value to which the active power droop coefficient (Kpdrp) is applied is generated as an active power droop reference signal (PdrpRef), and the difference between the relative reactive power reference value (Qm) and its second reactive power reference value (Qref) is proportionally integrated (Kp+). The value obtained by applying the reactive power droop coefficient (Kqdrp) to the difference between the Ki/s) value and the second reactive power reference value (Qref) is generated as a reactive power droop reference signal (QdrpRef) and output voltage frequency, output voltage and output Controlling a current and outputting the second active power reference value Pref and the second reactive power reference value Qref to a next unit inverter; And
(C) The N-1th active power reference value (Pref) and the N-1th reactive power reference value (Qref) applied from the N-1th inverter are relative to the active power reference value (Pm) and the relative active power reference value (Pm), respectively. As the reactive power reference value Qm, the difference between the relative active power reference value Pm and the own Nth active power reference value Pref is proportionally integrated (Kp+Ki/s), and the Nth active power reference value ( A value obtained by applying an active power droop factor (Kpdrp) to the difference value of Pref) is generated as an active power droop reference signal (PdrpRef), and the difference between the relative reactive power reference value (Qm) and its Nth reactive power reference value (Qref) The value obtained by applying the reactive power droop coefficient (Kqdrp) to the difference between the proportional integral (Kp+Ki/s) and the Nth reactive power reference value (Qref) is generated as a reactive power droop reference signal (QdrpRef) and output. Controlling voltage frequency, output voltage and output current; Including,
When at least one (m) of the first to the Nth inverter is not operated, except for the non-operated inverters (Nm), the remaining inverters are operated by uniformly distributing power. Droop parallel operation inverter redundancy method.
The method of claim 13,
In the steps (a) to (c), the first to the Nth inverters calculate the power deviation compensation values (Perr, Qerr) according to the following equation, V/F droop parallel operation Inverter redundancy method.

Here, Perr represents the active power deviation compensation value, Pref (Pm) represents the master active power, Pref represents the active power reference value, Qerr represents the reactive power deviation compensation value, and Qref (Qm) represents the master reactive power. And Qref represents the reactive power reference value.
The method of claim 13,
At least one inverter of the first unit to the Nth unit inverter in steps (a) to (c),
(a) The DQ conversion unit 9 includes an inverter current (IID) output from the IGBT power conversion unit 3, and a three-phase load voltage (VLD) and a three-phase load current output from the LC filter unit 5 (ILD) is converted to primary DQ to generate DQ stop coordinate conversion signals (Vlqs, Vlds, Ilqs Ilds, Iiqs Iids), and a three-phase bypass voltage (VBYP) applied from the bypass line is converted into a synchronization signal generator ( 7), the DQ synchronous coordinate conversion signal Vbde of the three-phase bypass voltage is generated by first-order DQ conversion according to the synchronization signal (ThetaByp) provided from), and the DQ stop coordinate conversion signal (Vlqs, Vlds, Ilqs Ilds, Iiqs) Generating and outputting DQ synchronization coordinate conversion signals (Vlqe, Vlde, Ilqe, Ilde, Iiqe , Iide) by second-order DQ transforming Iids) according to the drop application synchronization signal ThetaLd2 provided from the frequency control unit 17;
(b) The phase angle of the three-phase load current input from the DQ converter 9 by the V/F (Voltage/Frequency) parallel droop control unit 11 using the current phase angle compensation value provided from the parameter stored in the memory. Compensates for, and calculates a new active power reference value (Pref) and a reactive power reference value (Qref) using the 3-phase load current compensated for the phase angle and the 3-phase load voltage input from the DQ converter 9, and the In order to lower the voltage frequency output from the inverter by using the active power reference value (Pref) when the active power of the inverter is increased, the difference between the active power reference value (Pref) and the active power reference value (Pm) of another inverter is proportional. The value obtained by applying the active power droop coefficient (Kpdrp) to the difference between the integral (Kp+Ki/s) value and the active power reference value is generated as an active power droop reference signal (PdrpRef), and the reactive power of the inverter has been increased. In order to lower the voltage output from the inverter by using the reactive power reference value, the difference between the reactive power reference value (Qref) and the reactive power reference value (Qm) of another inverter is proportionally integrated (Kp+Ki/s) Generating a value obtained by applying a reactive power droop coefficient Kqdrp to the difference value of the reactive power reference value Qref as a reactive power droop reference signal QdrpRef;
(c) The synchronization signal generation unit 7 is a three-phase bypass voltage synchronization signal (ThetaByp) in phase with the DQ synchronization coordinate conversion signal (Vbde) of the three-phase bypass voltage converted by the DQ conversion unit (9). , ThetaLd) generating;
(d) The first Q-axis error calculator 14 calculates an error between the reactive power droop reference signal QdrpRef and the Q-axis voltage reference signal Vref (q axis), and calculates the synchronous Q-axis inverter reference voltage Vref( Outputting a ViqeCmd) signal;
(e) The inverter voltage and current control unit 15 receives the synchronous Q-axis inverter reference voltage signal Vref (ViqeCmd) and the synchronous D-axis inverter reference voltage signal 0 (VideCmd), and the DQ synchronous coordinate conversion signal Outputting a Q-axis voltage control signal (Vqref) and a D-axis voltage control signal (Vdref) by controlling a load voltage and a load current of the inverter according to (Vlqe, Vlde, Ilqe, Ilde);
(f) The frequency control unit 17 subtracts the active power droop reference signal PdrpRef from the three-phase bypass voltage synchronization signal ThetaLd output from the synchronization signal generator 7 to apply a droop application synchronization signal ( Generating ThetaLd2) and outputting it to the DQ transform unit 9 and the DQ inverse transform unit 13;
(g) The DQ inverse conversion unit 13 receives the Q-axis voltage control signal Vqref and the D-axis voltage control signal Vdref from the inverter voltage current control unit 15, and a control signal of the frequency control unit 17 Converting into a three-phase signal according to the step of outputting a command signal for adjusting an output voltage and a frequency of the inverter; And
(h) SV PWM conversion unit 19, a spatial vector pulse width modulation for switching the IGBT (Insulated Gate Bipolar Transistor) of the IGBT power conversion unit 3 to the command signal output from the DQ inverse conversion unit 13 Converting a signal (SV PWM: Space Vector Pulse Width Modulation) and outputting it to the IGBT power converter 3;
V/F droop parallel operation inverter redundancy method to perform.
The method of claim 15,
The step (b),
(b-1) The PQ conversion unit 21 receives the DQ synchronization coordinate conversion signals (Vlqe, Vlde, Ilqe Ilde) for the three-phase load voltage and the three-phase load current from the DQ conversion unit 9, and the load Calculating values of active power (P) and reactive power (Q) supplied to the device;
(b-2) The phase error compensation unit 23 receives a three-phase input from the DQ conversion unit 9 using a current phase angle compensation value provided from a parameter stored in the memory to create a parallel droop control signal. The active power reference value Pref and the reactive power reference value Qref are compensated for the phase angle of the load current, and the three-phase load current for which the phase angle is compensated and the three-phase load voltage transmitted from the DQ converter 9 are used. ) Calculating; And
(b-3) In order to lower the voltage frequency output from the inverter by using the active power reference value Pref when the active power of the inverter increases, the active power reference value Pref ) And the difference between the active power reference value (Pm) of other inverters and the value obtained by applying the active power droop factor (Kpdrp) to the difference between the active power reference value (Kp+Ki/s) and the active power reference value. In order to lower the voltage output from the inverter by generating a signal (PdrpRef) and using the reactive power reference value when the reactive power of the inverter increases, the reactive power reference value (Qm) of a different inverter than the reactive power reference value (Qref) ), a value obtained by applying a reactive power droop coefficient (Kqdrp) to the difference between the proportional integration (Kp+Ki/s) of the difference and the reactive power reference value (Qref) as the reactive power droop reference signal (QdrpRef). step;
V/F droop parallel operation inverter redundancy method comprising a.
The method of claim 16,
The step (b-3),
(b-3-1) calculating, by the second error calculator 31, an error between the active power reference value Pref and the active power reference value Pm of another inverter;
(b-3-2) the first-order proportional integrator 32 performs a first-order proportional integration (Kp+Ki/s) of the value output from the second error calculator 31;
(b-3-3) calculating, by a third error calculator (33), an error between the first-order proportional integration value and the active power reference value (Pref);
(b-3-4) The active power droop application unit 34 generates an active power droop reference signal (PdrpRef) by applying an active power droop coefficient (Kpdrp) to the value output from the third error calculator (33). The step of doing;
(b-3-5) calculating, by the fourth error calculator 35, an error between the reactive power reference value Qref and the reactive power reference value Qm of another inverter;
(b-3-6) the second-order proportional integrator 36 performs a second-order proportional integration (Kp+Ki/s) of the value output from the fourth error calculator 35;
(b-3-7) calculating, by a fifth error calculator (37), an error between the second-order proportional integration value and the reactive power reference value (Qref); And
(b-3-8) The reactive power droop application unit 38 generates a reactive power droop reference signal (QdrpRef) by applying a reactive power droop coefficient (Kqdrp) to the value output from the fifth error calculator 37. The step of doing;
V/F droop parallel operation inverter redundancy method comprising a.
The method of claim 15,
The step (e),
(e-1) The first coordinate axis conversion unit 41 calculates the synchronous axis coordinates for the synchronous Q-axis inverter reference voltage signal Vref(ViqeCmd) and the synchronous D-axis inverter reference voltage signal 0(VideCmd). Converting the coordinates to a stop axis and outputting a Q-axis load reference voltage (Vlqs_ref) and a D-axis load reference voltage (Vlds_ref);
(e-2) calculating, by the sixth error calculator 42, an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs;
(e-3) Compensating the Q-axis fundamental wave by controlling, by the Q-axis fundamental wave compensator 43, proportional resonance (PR) control of the error signal output from the sixth error calculator 42;
(e-4) calculating, by the seventh error calculator (44), an error between the Q-axis stop axis inverter voltage (Vlqs) and a reference level voltage (0);
(e-5) performing, by the fifth harmonic compensator 1 (45), performing proportional resonance (PR) control on the error signal output from the seventh error calculator 44 to compensate for the fifth harmonic;
(e-6) calculating, by the eighth error calculator 46, an error between the Q-axis stop axis inverter voltage Vlqs and a reference level voltage 0;
(e-7) performing, by the 7th harmonic compensator 1 (47), performing proportional resonance (PR) control on the error signal output from the eighth error calculator (46) to compensate for the 7th harmonic;
(e-8) The ninth adder 48 compensates for the fifth harmonic output from the fifth harmonic compensator 1 (45) and the seventh harmonic compensation output from the seventh harmonic compensator 1 (47). Adding one value first;
(e-9) The tenth adder 49 includes the first-order added value output from the ninth adder 48 and the Q-axis fundamental wave compensated value output from the Q-axis fundamental wave compensator 43 And secondly adding all of the Q-axis load current values (Ilqs);
(e-10) the eleventh adder 50 thirdly adding the second-added value output from the tenth adder 49 and the Q-axis inverter current value Iiqs;
(e-11) calculating, by the twelfth error calculator 51, an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds;
(e-12) Compensating the D-axis fundamental wave by controlling, by the D-axis fundamental wave compensator 52, the error signal output from the twelfth error calculator 51 by proportional resonance (PR) control;
(e-13) calculating, by the thirteenth error calculator (53), an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0);
(e-14) performing, by the fifth harmonic compensator 2 (54), performing proportional resonance (PR) control on the error signal output from the thirteenth error calculator (53) to compensate for the fifth harmonic;
(e-15) calculating, by the 14th error calculator (55), an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0);
(e-16) performing, by the 7th harmonic compensator 2 (56), performing proportional resonance (PR) control on the error signal output from the 14th error calculator (55) to compensate for the 7th harmonic;
(e-17) The 15th adder 57 compensates for the 5th harmonic output from the 5th harmonic compensator 2 54 and the 7th harmonic compensation output from the 7th harmonic compensator 2 56 Adding one value by the fourth order;
(e-18) The 16th adder 58 compensates for the fourth-order added value output from the 15th adder 57 and the D-axis fundamental wave output from the D-axis fundamental wave compensator 52. Adding the value and the D-axis load current value (IIds) by a fifth order;
(e-19) adding, by a seventeenth adder (59), the fifth-added value output from the sixteenth adder (58) and a D-axis inverter current value (Iids) by a sixth order;
(e-20) The second coordinate axis converting unit 60 includes the third-order added signal output from the eleventh adder 50 and the sixth-order added signal output from the seventeenth adder 59. Converting the stationary axis coordinates for the synchronous axis coordinates;
(e-21) The Q-axis current controller 61 controls the Q-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method to control the Q-axis voltage control signal. Outputting (Vqref); And
(e-22) The D-axis current controller 62 controls the D-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method to control the D-axis voltage control signal. Outputting (Vdref);
V/F droop parallel operation inverter redundancy method comprising a.
The method of claim 15,
The step (e),
(e-1) The first coordinate axis conversion unit 41 calculates the synchronous axis coordinates for the synchronous Q-axis inverter reference voltage signal Vref(ViqeCmd) and the synchronous D-axis inverter reference voltage signal 0(VideCmd). Converting the coordinates to a stop axis and outputting a Q-axis load reference voltage (Vlqs_ref) and a D-axis load reference voltage (Vlds_ref);
(e-2) calculating, by the sixth error calculator 42, an error between the Q-axis load reference voltage Vlqs_ref and the Q-axis stop axis inverter voltage Vlqs;
(e-3) Compensating the Q-axis fundamental wave by controlling, by the Q-axis fundamental wave compensator 43, proportional resonance (PR) control of the error signal output from the sixth error calculator 42;
(e-4) calculating, by the seventh error calculator (44), an error between the Q-axis stop axis inverter voltage (Vlqs) and a reference level voltage (0);
(e-5) performing, by the fifth harmonic compensator 1 (45), performing proportional resonance (PR) control on the error signal output from the seventh error calculator 44 to compensate for the fifth harmonic;
(e-6) calculating, by the eighth error calculator 46, an error between the Q-axis stop axis inverter voltage Vlqs and a reference level voltage 0;
(e-7) performing, by the 7th harmonic compensator 1 (47), performing proportional resonance (PR) control on the error signal output from the eighth error calculator (46) to compensate for the 7th harmonic;
(e-8) The ninth adder 48 compensates for the fifth harmonic output from the fifth harmonic compensator 1 (45) and the seventh harmonic compensation output from the seventh harmonic compensator 1 (47). Adding one value first;
(e-9) The tenth adder 49 compensates for the first-order added value output from the ninth adder 48 and the first-order fundamental wave output from the first-order fundamental wave compensator 43 Adding the value and the Q-axis load current value (Ilqs) to the second order;
(e-10) the eleventh adder 50 thirdly adding the second-added value output from the tenth adder 49 and the Q-axis inverter current value Iiqs;
(e-11) calculating, by the twelfth error calculator 51, an error between the D-axis load reference voltage Vlds_ref and the D-axis stop axis inverter voltage Vlds;
(e-12) Compensating the D-axis fundamental wave by controlling, by the D-axis fundamental wave compensator 52, the error signal output from the twelfth error calculator 51 by proportional resonance (PR) control;
(e-13) calculating, by the thirteenth error calculator (53), an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0);
(e-14) performing, by the fifth harmonic compensator 2 (54), performing proportional resonance (PR) control on the error signal output from the thirteenth error calculator (53) to compensate for the fifth harmonic;
(e-15) calculating, by the 14th error calculator (55), an error between the D-axis stop axis inverter voltage (Vlds) and a reference level voltage (0);
(e-16) performing, by the 7th harmonic compensator 2 (56), performing proportional resonance (PR) control on the error signal output from the 14th error calculator (55) to compensate for the 7th harmonic;
(e-17) The 15th adder 57 compensates for the 5th harmonic output from the 5th harmonic compensator 2 54 and the 7th harmonic compensation output from the 7th harmonic compensator 2 56 Adding one value by the fourth order;
(e-18) The 16th adder 58 compensates for the fourth-order added value output from the 15th adder 57 and the D-axis fundamental wave output from the D-axis fundamental wave compensator 52. Adding the value and the D-axis load current value (IIds) by a fifth order;
(e-19) adding, by a seventeenth adder (59), the fifth-added value output from the sixteenth adder (58) and a D-axis inverter current value (Iids) by a sixth order;
(e-20) The second coordinate axis converting unit 60 includes the third-order added signal output from the eleventh adder 50 and the sixth-order added signal output from the seventeenth adder 59. Converting the stationary axis coordinates for the synchronous axis coordinates;
(e-21) The Q-axis current controller 61 controls the Q-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method to control the Q-axis voltage control signal. Outputting (Vqref); And
(e-22) The D-axis current controller 62 controls the D-axis signal output from the second coordinate axis conversion unit 60 in a proportional integration (Kp+Ki/s) method to control the D-axis voltage control signal. Outputting (Vdref);
(e-23) The 18th error calculator 63 calculates an error between the synchronous Q-axis inverter reference voltage signal Vref(ViqeCmd) and the synchronous Q-axis load voltage Vlqe of the DQ synchronous coordinate conversion signal. step;
(e-24) the step of repeatedly controlling, by the Q-axis repetition controller (64), the Q-axis error signal output from the eighteenth error calculator (63);
(e-25) The 19th adder 65 adds the Q-axis signal output from the Q-axis current controller 61 and the Q-axis error signal output from the Q-axis repetition controller 64 to obtain a Q-axis voltage. Outputting a control signal Vqref;
(e-26) calculating, by the twentieth error calculator (66), an error between the synchronous D-axis inverter reference voltage signal (VideCmd) and the synchronous D-axis load voltage (Vlde) of the DQ synchronous coordinate conversion signal;
(e-27) the step of repeatedly controlling, by the D-axis repetition controller 67, the D-axis error signal output from the twentieth error calculator (66); And
(e-28) The 21st adder 68 adds the D-axis signal output from the D-axis current controller 62 and the D-axis error signal output from the D-axis repeat controller 67 to obtain the D-axis voltage. Outputting a control signal Vdref;
V/F droop parallel operation inverter redundancy method comprising a.

Images