KR102242281B1 - Apparatus and method for mapping binary to ternary and its reverse - Google Patents

Abstract

An apparatus for converting binary data to ternary data and vice versa is described, comprising: a first look-up table (LUT) with a mapping of 19 binary bits to 12 ternary trees; And first logic for receiving a binary input and converting the binary input to a ternary output according to the first LUT.

Description

Apparatus and method for mapping binary to ternary and vice versa {APPARATUS AND METHOD FOR MAPPING BINARY TO TERNARY AND ITS REVERSE}

Priority claim

This application has priority to U.S. Patent Application Serial No. 14/490,307 filed September 18, 2014, which is incorporated herein by reference in its entirety, entitled "APPARATUS AND METHOD FOR MAPPING BINARY TO TERNARY AND ITS REVERSE" Insist.

Flash memory can be designed using single level cells that store a single bit of information in each memory cell, or as multilevel cells that store multiple bits of information in each memory cell. In general, single-level cells are more durable than multi-level cells. However, multilevel cells provide a higher storage density than single level cells. A multilevel cell memory (eg, a flash memory) is composed of multilevel cells, each of which can store a plurality of state of charge or levels. Each of the state of charge is associated with a memory element bit pattern. The multi-level cell memory is configurable to store _{multiple threshold voltage levels (V t ).}

The multi-level cell memory can store more than one bit of data based on the number of state of charge. For example, a multilevel cell memory capable of storing 4 charge states (or 4 Vt levels) can store 2 bits of data, and a multilevel capable of storing 8 charge states (or 8 Vt levels). A cell memory can store 3 bits of data, and a multi-level cell capable of storing 16 charge states can store 4 bits of data. For each of the n-bit multi-level cell memories, various memory element bit patterns may be associated with each of the different states of charge. The reference voltage can separate the various states of charge. For example, the first reference voltage can separate level 3 and level 2, the second voltage reference can separate level 1 and level 2, and the third reference voltage can separate level 0 and level 1. have.

Binary information can be directly mapped to single level cell memory. However, multilevel cells require a memory mapping operation that maps binary information to the number of levels of the multilevel cells. Binary-triple mapping is a function that takes binary data and maps it to a ternary symbol. A typical binary-to-ternary mapping first obtains the decimal representation of a binary string and then maps this decimal number to its ternary representation. The compression obtained by this mapping is close to the theoretical limit. For example, 1 kilobyte bits (ie, 8192 bits) can be mapped to 5169 ternary symbols. The compression obtained is 1.5848, which is close to the theoretical limit. The theoretical storage limit for each 3-level memory cell is Log2(3) = 1.5849 bits.

One problem with this typical binary-to-ternary mapping is that error propagation occurs. Consider the binary string "000...001111" to be stored. The decimal representation of this string is 15 and the ternary representation is "000..00120". This ternary character string stored as level information in the cells (eg, in a NAND flash memory) is read back. Since there is an error when reading from the memory (e.g., NAND flash memory), "0000...00121" is read again (i.e., the last level 0 is read as level 1). The binary representation for this noisy reading is "000...0010000". Thus, a single level of error is converted to 5 bits in a read error. A typical mapping has an error propagation by a factor of 3.5, which means that the bit error rate is 3.5 times the level error rate.

Embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure, but this should not be construed as limiting the disclosure to the specific embodiments, description and understanding. It's for only.
1 shows a hardware architecture using look-up tables (LUTs) to map binary to ternary and vice versa, in accordance with some embodiments of the present disclosure.
2 illustrates a LUT having a 19 bit binary input and a 12 trit ternary symbol output with a ternary representation of a power of 2, in accordance with some embodiments of the present disclosure.
3 illustrates a LUT having a 12-treat ternary symbol input and a 19-bit binary output with a binary representation of a power of 3, in accordance with some embodiments of the present disclosure.
FIG. 4 illustrates a memory architecture for storing data in a multilevel (eg, three-level) memory cell according to the hardware architecture of FIG. 1, in accordance with some embodiments of the present disclosure.
5 shows a flow diagram of a method of mapping binary to ternary and vice versa, in accordance with some embodiments of the present disclosure.
6 illustrates a smart device or computer system or System-on-Chip (SoC) having an apparatus for mapping binary data to and vice versa, in accordance with some embodiments.

For flash memories (e.g., NAND memories) used in a multi-level storage mode (e.g., three threshold voltage level mode), there are various ways in which binary bits can be mapped to three threshold levels. . For example, the payload may be first protected by Error Protection Code (ECC) and then binary ECC bits may be mapped from the binary domain to the ternary domain. Another way is to first perform a binary-to-three-way mapping of the payload and then let the three-way ECC code act on the stern data. There are distinct advantages to using the three-way ECC method. The binary ECC scheme may require that the levels read from the memory are first converted from the ternary domain to the binary domain. Because there is an error in the read ternary levels, there is an error propagation by a factor of 2 when ternary symbols are converted to binary bits.

However, when the three-way ECC schemes are used, the three-way ECC first corrects all errors. Working on noise-free data, the ternary-binary mapping provides error-free binary bits. The typical binary-to-three mapping is very complex to implement. For example, the ECC codeword size for sample data is approximately 4.6 kilobyte bits or approximately 37,665 bits. If these 37,665 bits are to be converted to their corresponding ternary representation, then the number of gates is 4*37665 = 150,000 gates. A similar number of gates are required for ternary-binary mapping, which maps ternary data to binary data during readout using typical binary-to-ternary mapping. Various embodiments describe in detail an optimal binary-three-dimensional map and its hardware implementation.

The mapping described in some embodiments is a 19-12 mapping that takes 19 binary bits and maps them to 12 ternary symbols (or treats) using a look-up table (LUT). The theoretical storage limit for each 3-level memory cell is Log2(3) = 1.5849 bits. In some embodiments, the transform causes 1.5833 bits to be mapped to one ternary symbol, which is closer to the theoretical limit of 1.5849 bits per cell (bpc). In some embodiments, the hardware implementation of this mapping uses logic gates in the range of 100 gates, which is much less complex than the hardware for a typical binary-to-ternary mapping.

The embodiments are described with respect to storage in a 3-level memory (eg, 3-level NAND, 3-level phase change memory, etc.), but embodiments are not limited thereto. In some embodiments, for 6-level programming, the 19-12 mapping can be generalized as follows. For example, the levels of 6-level programming are divided into two groups-a first group of L0, L1 and L2 and a second group of L3, L4 and L5, where'L' represents the level. In some embodiments, one bit is used to determine the group (ie, the first group or the second group), and then the 19-12 map is used to store 1.583 bpc within the three levels of the group. By these embodiments, a storage of 2.583 bpc is achieved. The manner described in various embodiments can be extended to programming of any multiple of 2 or 3 levels. For example, 9-level programming, 12-level programming, 18-level programming, 27-level programming, etc.

In the following description, a number of details are discussed to provide a more thorough description of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present disclosure.

Note that in the corresponding figures of the embodiments, signals are represented by lines. Some lines may be thicker, to indicate more constituent signal paths, and/or may have arrows at one or more ends to indicate the main information flow direction. These indications are not intended to be limiting. Rather, lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic unit. Any represented signal may actually include one or more signals that may move in either direction and may be implemented in any suitable type of signaling scheme, as dictated by design requirements or preferences.

Throughout the specification and in the claims, the term “connected” means a direct electrical connection between objects to which the connection is made, without any intermediate device. The term "coupled" means a direct electrical connection between the objects to which the connection is made or an indirect connection through one or more passive or active intermediate devices. The term “circuit” means one or more passive and/or active components arranged to cooperate with each other to provide a desired function. The term “signal” means at least one current signal, voltage signal, or data/clock signal. The meaning of the singular expressions "a", "an" and "the" includes plural references. The meaning of "in" includes "in" and "on".

The terms "substantially", "close", "approximately", "near" and "about" are generally within ±20% of the target value. Say. Unless otherwise specified, the use of the ordinal adjectives “first”, “second” and “third”, etc. to describe a common object only indicates that different instances of similar objects are being mentioned, and thus described object It is not intended to imply that they must be in a given order, either temporally, spatially, ranking or in any other way.

1 shows a hardware architecture 100 using LUTs to map binary to ternary and vice versa, in accordance with some embodiments of the present disclosure. In some embodiments, the architecture 100 includes a first logic 101, a first LUT 102, a buffer(s) 103, a second logic 104, and a second LUT 105. . In some embodiments, the first logic 101 includes combinatorial logic and/or a finite state machine (FSM) that accesses the first LUT 102 to convert a binary input into a three-digit symbol output.

In some embodiments, the first logic 101 includes logic to initialize the ternary output value to zero. In some embodiments, the first logic 101 then checks the position of 1s in a 19-bit tuple (ie, binary input). In some embodiments, wherever a 1 is detected in the binary input, its ternary representation is read from the first LUT 102 and added to the ternary value (which is initially initialized to zero). The first LUT 102 is described with reference to FIG. 2, according to some embodiments. Referring back to Figure 1, in some embodiments, the addition occurs in the ternary domain. In some embodiments, when all 1s in the 19-bit tuple are considered, a 12-triple symbol value is obtained and provided as a ternary output.

In some embodiments, the second logic 104 includes logic to initialize the binary output to zero. In some embodiments, the second logic 104 then checks the position of 1s in the 12-treat symbol (ie, buffered strikeout output). In some embodiments, wherever a 1 is detected in the buffered ternary output, its binary representation is read from the second LUT 105 and added to the binary value (which is initially initialized to 0). The second LUT 105 is described with reference to FIG. 3, according to some embodiments. Referring again to Figure 1, in some embodiments, the addition occurs in the binary domain. In some embodiments, when all 1s in the 12-treat symbol are considered, a 19-bit binary value is obtained and provided as a binary output. The hardware implementation of the second logic 104 may be similar to the hardware implementation of the first logic 101.

Using these mappings, some embodiments can efficiently convert binary data to the ternary domain at the encoder during a write operation, and efficiently convert the ternary data to binary form at the decoder during a read operation. In some embodiments, 19-12 mapping provides the most efficient mapping to the theoretical limit of 1.585 bpc.

2 shows a LUT 200 (e.g., a first LUT 102) having a 19-bit binary input and a 12-treat ternary symbol output with a ternary representation of a power of 2, according to some embodiments of the present disclosure. ). It is noted that those elements of FIG. 2 having the same reference numbers (or names) as those of any other figure may operate or function in any manner similar to that described, but are not limited to such. In some embodiments, LUT 200 has 19 items corresponding to a power of 2 in ternary for every power of 2 from 0 to 18.

In some embodiments, LUT 200 is implemented with non-volatile memory. Examples of nonvolatile memories include phase change memory (PCM), three-dimensional cross-point memory, resistive memory, nanowire memory, ferro-electric transistor random access memory (FeTRAM), flash memory such as NAND or NOR, and memristor technology. Incorporating magneto-resistive random access (MRAM) memory technology, spin transfer torque (STT)-MRAM, and more. In other embodiments, the LUT 200 is implemented with different types of storage circuits.

3 shows a LUT 300 (e.g., a second LUT 105) having a 12-treat ternary symbol input and a 19-bit binary output with a binary representation of a power of 3, according to some embodiments of the present disclosure. Shows. It is noted that those elements of FIG. 3 having the same reference numbers (or names) as those of any other figure may operate or function in any manner similar to that described, but are not limited to such. In some embodiments, LUT 300 has 12 items corresponding to powers of 3 from 0 to 11. In some embodiments, LUT 300 is implemented with non-volatile memory. In another embodiment, LUT 300 is implemented with different types of storage circuits.

FIG. 4 shows a memory architecture 400 for storing data in a multilevel memory (eg, 3-level memory) according to the hardware architecture of FIG. 1, in accordance with some embodiments of the present disclosure. It is noted that those elements of FIG. 4 having the same reference numbers (or names) as those of any other figure may operate or function in any manner similar to that described, but are not limited to such.

The memory architecture 400 may be a solid state drive (SSD), according to some embodiments. In other embodiments, other types of architectures may be used. Thus, in order not to obscure the embodiments, a simplified version of the memory architecture 400 is shown. Those of skill in the art will understand that there are other logic and circuits required for the full operation of architecture 400. For example, input/output (I/O) buffers (Serial Advanced Technology Attachment (SATA) interface, etc.) and corresponding circuits are not shown.

In some embodiments, the memory architecture 400 includes a three-level memory 401 (e.g., a three-level NAND flash memory, a three-level phase change memory (PCM), etc.) and a processor 402 (e.g. For example, a memory controller). Although memory 401 is shown as a single unit, it may include a plurality of nonvolatile memory subunits, each having a three-level memory cell. In some embodiments, the memory 401 may be integrated within the processor 402 on the same package. In some embodiments, the memory 401 may be separate on a separate die but may be on the same package or on different packages.

For some memories (eg, L06 NAND), a nonvolatile memory cell (eg, a 3-level NAND cell) is programmed to 3 levels (ie, bits are mapped to 3 levels). Some embodiments describe a 1.5 bit/cell programming scheme. This involves programming 3 bits into two nonvolatile memory cells. The two nonvolatile memory cells can jointly represent nine combinations. One of the combinations remains unprogrammed and the remaining 8 combinations are uniquely mapped to 3 bits. Thus, 1.5 bits are stored per nonvolatile memory cell. The theoretical storage limit for each nonvolatile memory cell is actually 1.5849 bits. Therefore, storing at 1.5 bits/cell is inefficient. Architecture 100 and SSD 400 describe hardware and associated methods for substantially reaching the storage limit of 1.5849 bits/cell, in accordance with some embodiments of the present disclosure.

In some embodiments, the processor 402 includes an encoder 403, a decoder 404, a first logic 101 (i.e., a Binary to Ternary (B2T) converter), a first LUT 102, It includes a second logic 104 (ie, a Ternary to Binary (T2B) converter), and a second LUT 105. In some embodiments, the input binary data (data_in) is received by the B2T converter 101 which converts data_in to ternary dataT1 using the mapping of the first LUT 102 as described with reference to FIG. 1. Convert. Referring again to FIG. 4, in some embodiments, the ternary dataT1 is encoded by an encoder 403 that generates encoded data (ie, encoded level information) for storage in memory 401.

When data is requested by the processor 402, the encoded data is retrieved from the memory 401 and decoded by the decoder 404. The output dataT2 of the decoder 404 is ternary data because the encoded data was ternary data. In some embodiments, dataT2 is received by a T2B converter 105, which converts dataT2 to a binary output data_out using the mapping of the second LUT 105 as described with reference to FIG. 1. Here, in the error-free level information output data by the decoder 404, data_out is mapped to the binary domain by the T2B converter 105.

Referring back to FIG. 4, in some embodiments, the encoder 403 is a Low Density Parity Check (LDPC) encoder and the decoder 404 is an LDPC decoder. In other embodiments, other types of encoding and corresponding decoding schemes may be used. For example, Bose, Chaudhuri, and Hocquenghem (BCH) encoding and a corresponding decoding scheme may be used. In some embodiments, non-binary LDPC codes provide better performance than binary LDPC codes at the cost of additional hardware. In the case of ternary codes, according to some embodiments, the additional hardware cost is minimal. Residual Bit-Error Rate (RBER) gains of some embodiments are significant compared to binary codes. For example, RBER gains due to ternary LDPC codes and compact binary to ternary mapping described with reference to various embodiments are approximately 1.53 times, allowing an RBER of 2.3e-2.

5 shows a flow diagram 500 of a method of mapping binary to ternary and vice versa, in accordance with some embodiments of the present disclosure. It is noted that those elements of FIG. 5 having the same reference numbers (or names) as those of any other figure may operate or function in any manner similar to that described, but are not limited to such.

Although the blocks in the flowchart with reference to FIG. 5 are shown in a specific order, the order of operations may be modified. Accordingly, the illustrated embodiments may be performed in a different order, and some operations/blocks may be performed in parallel. Some of the blocks and/or operations listed in FIG. 5 are optional according to certain embodiments. The numbering of the blocks presented is for clarity, and is not intended to define the order of operations in which various blocks should occur. Also, operations from various flows can be used in various combinations.

At block 501, a binary input is received by the first logic 101. At block 502, the binary input is converted to a ternary output by the first logic 101 according to the first LUT 102, where the first LUT 102 is 19 binary bits as shown with reference to FIG. Includes a mapping of 12 ternary treatments. In some embodiments, the first logic 101 initializes the ternary output value to zero. In some embodiments, the first logic 101 checks the position of 1s in the 19-bit binary input. In some embodiments, wherever a 1 is detected in the binary input, its ternary representation is read from the first LUT 102 and added to the ternary value (which is initially initialized to zero). In some embodiments, when all 1s in the 19-bit binary input are considered, a 12-triple symbol value is obtained and provided as a ternary output for storage in a memory (eg, memory 401).

Referring again to FIG. 5, at block 503, a struck out output is retrieved from memory (eg, memory 401) and provided to second logic 104. At block 504, the second logic 104 converts the ternary output to a binary output according to the second LUT 105, where the second LUT 105 is Includes mapping to 19 binary bits.

In some embodiments, the second logic 104 includes logic to initialize the binary output to zero. In some embodiments, the second logic 104 then checks the position of 1s in the 12-treat symbol (ie, the ternary output retrieved from the memory 401). In some embodiments, wherever a 1 is detected in the ternary output, its binary representation is read from the second LUT 105 and added to the binary value (which is initially initialized to 0). In some embodiments, the addition occurs in the binary domain. In some embodiments, when all 1s in the 12-treat symbol are considered, a 19-bit binary value is obtained and provided as a binary output.

6 illustrates a smart device or computer system or System-on-Chip (SoC) having an apparatus for mapping binary to ternary and vice versa, in accordance with some embodiments. It is noted that those elements of FIG. 6 having the same reference numbers (or names) as those of any other figure may operate or function in any manner similar to that described, but are not limited to such.

6 shows a block diagram of an embodiment of a mobile device in which flat surface interface connectors may be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, mobile phone or smart-phone, wireless-enabled e-reader, or other wireless mobile device. It will be appreciated that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

In some embodiments, computing device 1600 includes a first processor 1610 having an apparatus for mapping binary to ternary and vice versa, in accordance with some embodiments discussed. Other blocks of computing device 1600 may also include an apparatus for mapping binary to ternary and vice versa in accordance with some embodiments. Various embodiments of the present disclosure may also include a network interface in 1670, such as a wireless interface, such that a system embodiment may be incorporated into a wireless device, for example a cell phone or personal digital assistant.

In one embodiment, processor 1610 (and/or processor 1690) includes one or more physical devices such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. can do. Processing operations performed by the processor 1610 include execution of an operating platform or operating system on which application and/or device functions are executed. These processing operations include operations related to input/output (I/O) with a human user or with other devices, operations related to power management, and/or connecting computing device 1600 to another device. Includes related actions. These processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device 1600 includes hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components related to providing audio functions to the computing device. Indicative audio subsystem 1620 is included. Audio functions may include speaker and/or headphone output as well as microphone input. Devices for these functions may be integrated into computing device 1600 or may be connected to computing device 1600. In one embodiment, a user interacts with computing device 1600 by providing audio instructions that are received and processed by processor 1610.

The display subsystem 1630 is a hardware (e.g., display devices) and software (e.g., drivers) component that provides a visual and/or tactile display for a user to interact with the computing device 1600. Show them. The display subsystem 1630 includes a display interface 1632 that includes a specific screen or hardware device used to present a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 may be operated to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. In addition, the I/O controller 1640 shows a point of connection for additional devices that connect to the computing device 1600 through which a user can interact with the system. For example, devices that can be attached to the computing device 1600 include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or in a specific application such as a card reader or other device. Other I/O devices may be included for use.

As mentioned above, I/O controller 1640 may interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device may provide input or instructions to one or more applications or functions of computing device 1600. Further, the audio output may be provided instead of the display output or in addition to the display output. In another example, if display subsystem 1630 includes a touch screen, the display device also serves as an input device that can be at least partially managed by I/O controller 1640. Additional buttons or switches may also exist on computing device 1600 that provide I/O functions managed by I/O controller 1640.

In one embodiment, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in computing device 1600. The input (such as filtering for noise, adjusting displays for brightness detection, applying flash to a camera, or other features), as well as providing environmental input to the system to influence its actions, It can be part of a direct user interaction.

In one embodiment, computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operations. Memory subsystem 1660 includes memory devices that store information on computing device 1600. The memory may include non-volatile (state does not change when power to the memory device is cut off) and/or volatile (state is indeterminate when power to the memory device is cut off) memory devices. The memory subsystem 1660 may store application data, user data, music, photos, documents, or other data, as well as system data (long term or temporary) related to the execution of applications and functions of the computing device 1600. .

Elements of the embodiment may also be used as a machine-readable medium (e.g., memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any other processes discussed herein). Is provided. This machine-readable medium (e.g., memory 1660) includes flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change Memory (PCM), or other type of machine-readable medium suitable for storing electronic or computer-executable instructions, but is not limited thereto. For example, embodiments of the present disclosure may be directed from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by data signals via a communication link (e.g., modem or network connection). It can be downloaded as a computer program (eg BIOS) that can be transferred.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components that enable computing device 1600 to communicate with external devices. For example, drivers, protocol stacks). Computing device 1600 may be peripheral devices such as headsets, printers, or other devices, as well as separate devices such as other computing devices, wireless access points or base stations.

Connectivity 1670 may include a number of different types of connectivity. To generalize, the computing device 1600 is shown as having cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 is a global system for mobile communications (GSM) or variants or derivatives, code division multiple access (CDMA) or variants or derivatives, time division multiplexing (TDM) or variants or derivatives, Or generally refers to cellular network connectivity provided by wireless carriers, such as other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to non-cellular wireless connectivity, and personal area networks (such as Bluetooth, Near Field, etc.), (Wi-Fi )), and/or wide area networks (such as WiMax), or other wireless communications.

Peripheral device connections 1680 include hardware interfaces and connectors that make up the peripheral device connections, as well as software components (eg, drivers, protocol stacks). Computing device 1600 may be peripherals to other computing devices (“from” 1684), as well as having peripherals connected to itself (“from” 1684). I will understand the point. Computing device 1600 is often “docked” to connect to other computing devices for purposes such as managing (eg, downloading and/or uploading, changing, synchronizing) content on computing device 1600. It has a connector. Further, the docking connector may allow the computing device 1600 to connect to certain peripheral devices that allow the computing device 1600 to control content output to, for example, audiovisual or other systems.

In addition to a proprietary docking connector or other dedicated connection hardware, computing device 1600 may make peripheral connections 1680 through common or standards-based connectors. Common types include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire or other Can contain types.

Reference herein to “an embodiment”, “one embodiment”, “some embodiments”, or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is not necessarily It means that it is included in at least some embodiments, not all embodiments. The various appearances of “an embodiment”, “one embodiment”, or “some embodiments” are not necessarily all referring to the same embodiment. If the specification states that a component, feature, structure, or characteristic is "may, might," or "could", the particular component, feature, structure, or characteristic is not required to be included. . When reference is made to an "a, an" element in the specification or claim, this does not imply that there is only one element. Where reference is made to an “additional” element in the specification or claim, it does not preclude that there are more than one additional element.

Further, certain features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment can be combined with the second embodiment anywhere as long as certain features, structures, functions, or features related to the two embodiments are not mutually exclusive.

While the present disclosure has been described with its specific embodiments, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in view of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the embodiments discussed. Embodiments of the present disclosure are intended to cover all such alternatives, modifications and variations as falling within the broad scope of the appended claims.

In addition, well-known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown in the figures presented in order to simplify description and discussion, and not to obscure the disclosure. In addition, arrangements may be shown in block diagram form, which is to avoid obscuring the disclosure, and taking into account the fact that the details of implementation of such block diagram arrangements are highly dependent on the platform on which the present disclosure is to be implemented. (I.e., these details will be within the understanding of those skilled in the relevant field). When specific details (e.g., circuits) are presented to describe exemplary embodiments of the present disclosure, to those skilled in the art, the present disclosure may be used without these specific details, or without such specific details. It will be apparent that these can be implemented by changing them. Accordingly, the description should be regarded as illustrative instead of limiting.

The following examples relate to further embodiments. The details in these examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein can also be implemented for a method or process.

For example, a first LUT having a mapping of 19 binary bits to 12 ternary trees; And first logic for receiving a binary input and converting the binary input to a ternary output according to the first LUT. In some embodiments, the apparatus comprises: a second LUT having a mapping of 12 ternary treats to 19 binary bits; And second logic for receiving the ternary output and converting it to a binary output according to the second LUT. In some embodiments, the first LUT includes 19 items corresponding to power-of-two values ternary to powers of two from 0 to 18.

In some embodiments, the second LUT includes 12 items corresponding to powers of 3 values in binary for powers of 3 from 0 to 11. In some embodiments, the first logic includes logic to initialize the ternary output to zero. In some embodiments, the first logic includes logic to determine the position of 1s in the binary input. In some embodiments, the binary input has 19 binary bits. In some embodiments, the first logic includes logic to detect a 1 in the binary input. In some embodiments, the first logic includes logic to read a ternary representation from the first LUT according to a corresponding position of 1 from a position of 1s in the binary input.

In some embodiments, the first logic includes an adder that generates the ternary output by adding the ternary expression to the initialized ternary output in the ternary domain. In some embodiments, the ternary output is a 12 ternary symbol value. In some embodiments, the second logic includes logic to read the ternary output and initialize the binary output to zero. In some embodiments, the second logic comprises: logic to determine a position of 1s in the 12 strikeout treats of the strikeout output; Logic to read a binary representation from the second LUT according to the corresponding position of 1 from the position of 1s in the ternary input; And an adder for generating the binary output by adding the binary representation to the initialized binary output in the binary domain.

In another example, non-volatile memory; A processor coupled to the non-volatile memory, the processor comprising: a first LUT having a mapping of 19 binary bits to 12 ternary trees; A second LUT with a mapping of 12 ternary treats to 19 binary bits; First logic for receiving a binary input and converting the binary input to a ternary output according to the first LUT; And an encoder receiving the ternary output, encoding the ternary output, and generating an encoded ternary output for storage in the non-volatile memory; And a wireless interface that allows the processor to communicate with another device.

In some embodiments, the system includes a decoder that decodes the encoded ternary output and generates a decoded ternary output. In some embodiments, the system includes second logic to receive the decoded ternary output and convert it to a binary output according to the second LUT. In some embodiments, the encoder is a ternary LDPC encoder and the decoder is a ternary LDPC decoder. In some embodiments, the first LUT includes 19 items corresponding to powers of 2 values in ternary for a power of 2 from 0 to 18, and the second LUT is a power of 3 from 0 to 11. Contains 12 items that correspond to powers of 3 values in binary over the square.

In yet another example, receiving a binary input; And converting the binary input to a ternary output according to a first LUT, wherein the first LUT has a mapping of 19 binary bits to 12 ternary trees. In some embodiments, the method further comprises: receiving the strikeout output; And converting the ternary output into a binary output according to a second LUT, wherein the second LUT has a mapping of 12 ternary treats to 19 binary bits. In some embodiments, the first LUT includes 19 items corresponding to power-of-two values ternary to powers of two from 0 to 18. In some embodiments, the second LUT includes 12 items corresponding to powers of 3 values in binary for powers of 3 from 0 to 11. In some embodiments, the method includes initializing the ternary output to zero. In some embodiments, the method includes determining the position of 1s in the binary input. In some embodiments, the binary input has 19 binary bits.

In some embodiments, the method includes detecting a 1 in the binary input. In some embodiments, the method includes reading a ternary representation from the first LUT according to a corresponding position of 1 from a position of 1s in the binary input. In some embodiments, the method includes, in a ternary domain, adding the ternary representation to the initialized ternary output to generate the ternary output. In some embodiments, the ternary output is a 12 ternary symbol value. In some embodiments, the method further comprises: reading the struck out output; And initializing the binary output to zero.

In some embodiments, the method includes determining the location of 1s in the 12 strikeout treats of the strikeout output. In some embodiments, the method includes reading a binary representation from the second LUT according to the corresponding position of 1 from the position of 1s in the ternary input. In some embodiments, the method includes, in a binary domain, adding the binary representation to the initialized binary output to generate the binary output.

In yet another example, means for receiving a binary input; And means for converting the binary input to a ternary output in accordance with a first LUT, the first LUT having a mapping of 19 binary bits to 12 ternary trees. In some embodiments, the device comprises: means for receiving the strikeout output; And means for converting the ternary output to a binary output according to a second LUT, wherein the second LUT has a mapping of 12 ternary treats to 19 binary bits. In some embodiments, the first LUT includes 19 items corresponding to power-of-two values ternary to powers of two from 0 to 18. In some embodiments, the second LUT includes 12 items corresponding to powers of 3 values in binary for powers of 3 from 0 to 11.

In some embodiments, the device includes means for initializing the strikeout output to zero. In some embodiments, the apparatus includes means for determining the position of 1s in the binary input. In some embodiments, the binary input has 19 binary bits. In some embodiments, the apparatus includes means for detecting a 1 in the binary input. In some embodiments, the apparatus includes means for reading a ternary representation from the first LUT according to a corresponding position of 1 from a position of 1s in the binary input.

In some embodiments, the apparatus includes means for generating the ternary output by adding the ternary representation to the initialized ternary output, in the ternary domain. In some embodiments, the ternary output is a 12 ternary symbol value. In some embodiments, the device comprises: means for reading the strikeout output; And means for initializing the binary output to zero. In some embodiments, the apparatus includes means for determining the location of 1s in the 12 strikeout treats of the strikeout output. In some embodiments, the apparatus includes means for reading a binary representation from the second LUT according to a corresponding position of 1 from a position of 1s in the ternary input. In some embodiments, the apparatus comprises, in the binary domain, means for generating the binary output by adding the binary representation to the initialized binary output.

In another example, non-volatile memory; A processor coupled to the non-volatile memory, the processor comprising a device according to the device; And a wireless interface that allows the processor to communicate with another device. In some embodiments, the non-volatile memory is either a NAND memory or a PCM. In some embodiments, the system includes a display interface that enables a display unit to display content processed by the processor.

A summary is provided to enable the reader to ascertain the nature and points of this technical disclosure. This summary is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims (25)

As a device,
A first look-up table (LUT) with mapping of 19 binary bits to 12 triplets-the first LUT is implemented in hardware as logic gates within a range of 100 gates, and the first LUT is Includes numbers representing:

-; And
A first logic communicatively coupled to the first LUT
Including,
Wherein the first logic receives a binary input and converts the binary input to a ternary output according to the first LUT, wherein the conversion to the ternary output is unique and lossless. The method of claim 1,
A second LUT with a mapping of 12 ternary treats to 19 binary bits; And
And a second logic for receiving the ternary output and converting it to a binary output according to the second LUT, wherein the conversion to the binary output is unique and lossless. The method of claim 1,
Wherein the first LUT comprises 19 items corresponding to power-of-two values in ternary for powers of two from 0 to 18. The method of claim 2,
Wherein the second LUT comprises 12 items corresponding to powers of 3 values in binary for powers of 3 from 0 to 11. The method of claim 1,
Wherein the first logic comprises logic to initialize the strikeout output to zero. The method of claim 5,
Wherein the first logic comprises logic to determine a position of ones in a binary input. The method of claim 6,
Wherein the binary input has 19 binary bits. The method of claim 6,
Wherein the first logic comprises logic to detect a 1 in the binary input. The method of claim 6,
Wherein the first logic comprises logic to read a ternary representation from the first LUT according to a corresponding position of 1 from a position of 1s in the binary input. The method of claim 9,
Wherein the first logic comprises an adder for generating the ternary output by adding the ternary representation to the initialized ternary output in the ternary domain. The method of claim 10,
Wherein the ternary output is a 12 ternary symbol value. The method of claim 2,
Wherein the second logic includes logic to read the ternary output and initialize the binary output to zero. The method of claim 12,
The second logic is:
Logic to determine positions of 1s in the 12 strikeout treats of the strikeout output;
Logic to read a binary representation from the second LUT according to the corresponding position of 1 from the position of 1s in the ternary output; And
In the binary domain, an adder that generates the binary output by adding the binary representation to the initialized binary output. As a system,
Nonvolatile memory;
A processor coupled to the nonvolatile memory; And
A wireless interface that allows the processor to communicate with another device
Including,
The processor is:
A first look-up table (LUT) with mapping of 19 binary bits to 12 ternary trees-the first LUT contains numbers representing the following:

-;
A second LUT with a mapping of 12 ternary treats to 19 binary bits-the second LUT contains numbers representing:

-;
A first logic for receiving a binary input and converting the binary input to a ternary output according to the first LUT, the conversion to the ternary output is inherent and lossless; And
And an encoder receiving the ternary output and encoding the ternary output to generate an encoded ternary output for storage in the non-volatile memory. The method of claim 14,
And a decoder that decodes the encoded ternary output to produce a decoded ternary output. The method of claim 15,
And a second logic for receiving the decoded ternary output and converting it to a binary output according to the second LUT, wherein the conversion to the binary output is unique and lossless. The method of claim 15,
The encoder is a ternary LDPC encoder and the decoder is a ternary LDPC decoder. The method of claim 14,
The first LUT includes 19 items corresponding to powers of 2 in ternary for powers of 2 from 0 to 18, and the second LUT is 3 in binary for powers of 3 from 0 to 11 A system comprising twelve items corresponding to powers of. delete delete delete delete delete delete delete

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