KR102242115B1 - Semiconductor device, semiconductor system and operating method of semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device. The semiconductor device of the present invention includes a driver configured to respectively output a complementary first signal and a second signal through a first node and a second node, and a first node according to the voltage of the first node and the voltage of the second node. And a receiver detector configured to determine whether an active receiving circuit is connected to the second node. The receiver detector, when at least one of the voltage of the first node and the voltage of the second node does not indicate that the active receiving circuit is connected, the receiving circuit in the active state is not connected to the first node and the second node. It is determined to be.

Description

A semiconductor device, a semiconductor system, and an operation method of a semiconductor device {SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND OPERATING METHOD OF SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device, a semiconductor system, and a method of operating the semiconductor device.

Various semiconductor elements or circuits are combined to form a semiconductor device that performs a specific function. For example, as a semiconductor device, an application processor (AP) that drives applications, a modem (modulator and demodulator, MODEM) that performs communication, an image signal processor (ISP) that processes an image signal, There is a digital signal processor (DSP) that processes digital signals, and a power management integrated circuit (PMIC) that controls power.

Semiconductor devices that perform various functions are combined to form a semiconductor system that provides convenience to users. For example, as semiconductor systems, there are smart phones, smart pads, smart watches, smart televisions, computers, notebook computers, and the like.

Semiconductor devices forming a semiconductor system are configured to communicate with each other. As the level of the voltage consumed by the semiconductor devices decreases and the frequency of signals used in the semiconductor devices increases, the probability of occurrence of a malfunction in communication between the semiconductor devices increases. Accordingly, there is a need for an apparatus and method for securing the reliability of communication between semiconductor devices.

An object of the present invention is to provide a semiconductor device, a semiconductor system, and a method of operating a semiconductor device with improved reliability.

A semiconductor device according to an embodiment of the present invention includes a driver configured to output a complementary first signal and a second signal through a first node and a second node, respectively, during normal operation; And a receiver detector configured to determine whether an active receiving circuit is connected to the first node and the second node according to the voltage of the first node and the voltage of the second node during the receiver detection operation, wherein the When at least one of the voltage of the first node and the voltage of the second node does not indicate that the active receiving circuit is connected during the receiver detection operation, the first node and the second node It is determined that the active receiving circuit is not connected to the node.

A semiconductor system according to an embodiment of the present invention includes: a first semiconductor device including transmission circuits; A second semiconductor device including receiving circuits; And channels respectively connecting the transmission circuits and the reception circuits, each of the transmission circuits being connected to a corresponding reception circuit through a first signal line and a second signal line of a corresponding channel, and the transmission circuit Each of them is configured to determine whether the corresponding receiving circuit is active according to the voltage of the first signal line and the voltage of the second signal line, and to be deactivated when the corresponding receiving circuit is inactive.

A method of operating a semiconductor device according to an embodiment of the present invention including a transmission circuit configured to output a first signal and a second signal through a first node and a second node, respectively, is increased from a common voltage to a first voltage. Outputting the first signal through the first node and outputting the second signal, which is reduced from the common voltage to a second voltage, through the second node; Detecting voltages of the first node and the second node; And determining whether an active receiving circuit is connected to the first node and the second node according to the voltage of the first node and the voltage of the second node, wherein the determining comprises the first Comparing the voltage of the node with a first reference voltage; Comparing the voltage of the second node with a second reference voltage; And determining whether the active receiving circuit is connected according to a comparison result of the voltage of the first node and the comparison result of the voltage of the second node.

According to embodiments of the present invention, reliability of an operation of determining whether a transmission circuit of a semiconductor device is connected to a reception circuit is improved. Accordingly, a semiconductor device, a semiconductor system, and a method of operating the semiconductor device with improved reliability are provided.

1 is a block diagram illustrating a semiconductor system according to an exemplary embodiment of the present invention.
2 shows a transmission circuit and a reception circuit corresponding thereto according to an embodiment of the present invention.
3 is a flowchart illustrating a receiver detection method according to an embodiment of the present invention.
4 is a circuit diagram showing a receiver detector according to an embodiment of the present invention.
5 is a circuit diagram showing a receiver according to a first example of the present invention.
6 are graphs showing changes in voltages when receiver detection is performed according to the first embodiment of the present invention.
7 shows an example in which a malfunction occurs in a first input node or a second input node.
8 is a circuit diagram showing a receiver according to a second example of the present invention.
9 are graphs showing changes in voltages when receiver detection is performed according to the second embodiment of the present invention.
10 shows another example in which a malfunction occurs in a first input node or a second input node.
11 is a block diagram illustrating a semiconductor system according to another exemplary embodiment of the present invention.
12 is a diagram illustrating a transmission/reception circuit according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to describe in detail enough to enable a person of ordinary skill in the art to easily implement the technical idea of the present invention. .

1 is a block diagram illustrating a semiconductor system 100 according to an exemplary embodiment. Referring to FIG. 1, a semiconductor system 100 includes a first semiconductor device 110 and a second semiconductor device 120.

The first semiconductor device 110 and the second semiconductor device 120 are configured to communicate with each other through first to Nth channels CH1 to CHN. The first semiconductor circuit 110 includes transmission circuits TX and reception circuits RX corresponding to the first to Nth channels CH1 to CHN, respectively. The second semiconductor circuit 120 includes reception circuits RX and transmission circuits TX corresponding to the first to Nth channels CH1 to CHN, respectively.

For example, in the first channel CH1, the transmission circuit TX of the first semiconductor device 110 is connected to the second semiconductor device 120 through the first signal line SP and the second signal line SN. It may be connected to the receiving circuit (RX) of. In the first channel CH1, the transmission circuit TX of the second semiconductor device 120 is transmitted through the first signal line SP and the second signal line SN. RX) can be connected. In the first channel CH1, the transmission circuit TX and the reception circuit RX of the first semiconductor device 110 are the same as the transmission circuit TX and the reception circuit RX of the second semiconductor device 120, respectively. It has a structure and can operate in the same way.

Each of the second to Nth channels CH2 to CHN may have the same configuration as the first channel CH1. Accordingly, detailed descriptions of the second to Nth channels CH2 to CHN are omitted.

Depending on the design of the semiconductor system 100, the number of active channels among the first to Nth channels CH1 to CHN of the first semiconductor device 110 and the second semiconductor device 120 may be determined. For example, the first semiconductor device 110 and the second semiconductor device 120 are connected through N channels, and K channels (K is an integer of 1 or more and N or less) among N channels are active channels. Can be used. N-K channels are set as inactive channels and may not be used.

As another example, the number of active channels may be determined according to structures of the first semiconductor device 110 and the second semiconductor device 120. For example, the first semiconductor device 110 may include transmission circuits TX and reception circuits RX corresponding to N channels. The second semiconductor device 120 may include transmission circuits TX and reception circuits RX corresponding to M channels (M is a positive integer less than N). The M transmitting circuits TX and the receiving circuits RX of the first semiconductor device 110 are M receiving circuits RX and the transmitting circuits of the second semiconductor device 120 through M channels. TX) can be connected respectively. The N-M transmission circuits TX and reception circuits RX of the first semiconductor device 110 cannot be connected to the reception circuits RX and the transmission circuits RX of the second semiconductor device 120. That is, in the first semiconductor device, M channels may be active channels and N-M channels may be inactive channels.

The number of channels of the first semiconductor device 110 or the second semiconductor device 120 is determined when the first semiconductor device 110 or the second semiconductor device 120 is manufactured. However, the number of active channels or the number of inactive channels of the first semiconductor device 110 or the second semiconductor device 120 is a characteristic of the semiconductor system 100, or the first semiconductor device 110 or the second semiconductor device ( It may vary depending on the characteristics of the counterpart device communicating with 120).

The first semiconductor device 110 or the second semiconductor device 120 may have a function of determining the number of active channels or the number of inactive channels. For example, the transmission circuits TX of the first semiconductor device 110 or the second semiconductor device 120 may have a receiver detection function that determines whether an active reception circuit RX is connected.

For example, when the reception circuit RX of the second semiconductor device 120 connected to the transmission circuit TX of the first semiconductor device 110 is active, the transmission circuit TX of the first semiconductor device 110 ) Can be determined that the active receiving circuit RX is connected. The transmission circuit TX of the first semiconductor device TX may be set to communicate with the reception circuit RX of the second semiconductor device 120.

For example, when the reception circuit RX of the second semiconductor device 120 connected to the transmission circuit TX of the first semiconductor device 110 is in an inactive state, the transmission circuit TX of the first semiconductor device 110 ) Can be determined that the active receiving circuit is not connected. The transmission circuit TX of the first semiconductor device TX may be deactivated and may be set not to communicate with the reception circuit RX of the second semiconductor device 120.

For example, when the reception circuit RX of the second semiconductor device 120 is not connected to the transmission circuit TX of the first semiconductor device 110, the transmission circuit TX of the first semiconductor device 110 It can be determined that the receiving circuit in the active state is not connected. The transmission circuit TX of the first semiconductor device TX may be deactivated.

Likewise, the transmission circuit TX of the second semiconductor circuit 120 may perform a receiver detection operation of determining whether an active reception circuit RX is connected.

For example, the first semiconductor circuit 110 or the second semiconductor circuit 120 may perform the above-described receiver detection operation when power is supplied. After the receiver detection operation is performed, the first semiconductor circuit 110 and the second semiconductor circuit 120 may communicate with each other through active channels.

2 shows a transmission circuit TX and a reception circuit RX corresponding thereto according to an embodiment of the present invention. Exemplarily, the transmission circuit TX is the transmission circuit TX of the first semiconductor device 110 or the second semiconductor device 120 of FIG. 1, and the reception circuit RX is the second semiconductor device 120 or It may be a receiving circuit RX of the first semiconductor device 110.

1 and 2, the transmission circuit TX includes a driver 111 and a receiver detector 113. During normal operation, the driver 111 receives input signals from the core circuit of the first semiconductor device 110 or the second semiconductor device 120 through the first input node IP and the second input node IN. can do. For example, when communication is performed between the first semiconductor device 110 and the second semiconductor device 120, complementary differential input signals are transmitted through the first input node IP and the second input node IN. Can be received.

During normal operation, the driver 111 may output output signals to the first signal path SP and the second signal path SN through the first output node TXP and the second output node TXN, respectively. have. For example, when communication is performed between the first semiconductor device 110 and the second semiconductor device 120, complementary differential output signals are transmitted through the first output node TXP and the second output node TXN. Can be output. For example, the driver 111 is a complementary differential output that transitions between a high level higher than the first common voltage VCMX and a low level lower than the first common voltage VCMX based on the first common voltage VCMX. Can output signals. The first common voltage VCMX may have an intermediate level between the power voltage VDD and the ground voltage VSS.

When the receiver detection operation is performed, the driver 111 outputs a signal increasing from the first common voltage VCMX to a high level higher than the first common voltage VCMX through the first output node TXP, and A signal that decreases from the first common voltage VCMX to a lower level than the first common voltage VCMX may be output through the second output node TXN. Voltages or signals supplied to the first output node TXP and the second output node TXN may be supplied through internal resistors IR.

The receiver detector 113 is configured to receive voltages of the first output node TXP and the second output node TXN. Based on the voltages of the first output node TXP and the second output node TXN, the receiver detector 113 has a receiving circuit ( RX) is configured to determine if it is connected. When it is determined that the receiving circuit RX in an active state is connected to the first output node TXP and the second output node TXN, the receiver detector 113 may activate the active signal ACT. When it is determined that the receiving circuit RX in an active state is not connected to the first output node TXP and the second output node TXN, the receiver detector 113 may deactivate the active signal ACT.

The receiving circuit RX includes first and second capacitors C1 and C2, a receiver 125, and a balance circuit 127. The first input node RXP and the second input node RXN of the receiver 125 are connected to the first and second signal paths SP and SN through the first and second capacitors C1 and C2, respectively. Connected. The receiver 125 may output signals to core circuits of the first semiconductor device 110 or the second semiconductor device 120 through the first output node OP and the second output node ON. For example, when the voltage of the first input node RXP is a high level higher than the second common voltage VCMR and the voltage of the second input node RXN is a low level lower than the second common voltage VCMR, The receiver 125 may output a high level through the first output node OP and a low level through the second output node ON. When the voltage of the first input node RXP is a low level lower than the second common voltage VCMR and the voltage of the second input node RXN is a high level higher than the second common voltage VCMR, the receiver 125 May output a low level through the first output node OP and a high level through the second output node ON.

The balance circuit 127 may include a first resistor R1 and a second resistor R2 connected in series between the first input node RXP and the second input node RXN. The first resistor R1 and the second resistor R2 may have the same resistance values. A second common voltage VCMR may be supplied to a node between the first resistor R1 and the second resistor R2. The balance circuit 127 may provide a balance between voltages of the first input node RXP and the second input node RXN. For example, the balance circuit 127 may control the voltage of the first input node RXP and the voltage of the second input node RXP to swing around the second common voltage VCMR.

For example, the second common voltage VCMR may be determined according to a termination voltage of the receiver 125. For example, when termination of the receiver 125 is a pull-up termination using the power voltage VDD, the second common voltage VCMR may be the power voltage VDD. That is, the voltage of the first input node RXP and the voltage of the second input node RXN may swing around the power voltage VDD. For example, when the termination of the receiver 125 is a pull-down termination using the ground voltage VSS, the second common voltage VCMR may be the ground voltage VSS. That is, the voltage of the first input node RXP and the voltage of the second input node RXN may swing around the ground voltage VSS.

3 is a flowchart illustrating a receiver detection method according to an embodiment of the present invention. 1 to 3, in step S110, the driver 111 of the transmitter TX transmits a first output signal VP and a second output node through a first output node TXP and a second output node TXN. The output signal VN can be output. For example, the first output signal VP may increase from the first common voltage VCMX to a high level higher than the first common voltage VCMX. The second output signal VN may decrease from the first common voltage VCMX to a lower level than the first common voltage VCMX.

In step S120, the receiver detector 113 of the transmitter TX may detect voltages of the first output node TXP and the second output node TXN of the driver 111.

In step S130, the receiver detector 113 may determine the state of the reception circuit RX by comparing the detected voltages of the first output node TXP and the second output node TXN with reference voltages, respectively. . For example, the receiver detector 113 may compare the voltage of the first output node TXP and the voltage of the second output node TXN with different reference voltages, respectively. For example, according to the comparison result, the receiver detector 113 may determine whether an active receiving circuit RX is connected to the first output node TXP and the second output node TXN.

4 is a circuit diagram showing a receiver detector 113 according to an embodiment of the present invention. 2 and 4, the receiver detector 113 includes third to sixth resistors R3 to R6, first and second comparators COMP1 and COMP2, and an AND operation unit AND. do.

The third to sixth resistors R3 to R6 may be connected in series between the power node to which the power voltage VDD is supplied and the ground node to which the ground voltage VSS is supplied. The voltage of the node between the third resistor R3 and the fourth resistor R4 adjacent to the power node may be used as the first reference voltage VREFP. The voltage of the node between the fifth resistor R5 and the sixth resistor R6 adjacent to the ground node may be used as the second reference voltage VREFN. That is, the third to fourth resistors R3 to R6 may form a voltage generator or a voltage divider that generates the first reference voltage VREFP and the second reference voltage VREFN. The voltage of the node between the fourth resistor R4 and the fifth resistor R5 may be the first common voltage VCMX. The first reference voltage VREFP may have a level higher than the first common voltage VCMX and lower than the power voltage VDD. The second reference voltage VREFN may have a level lower than the first common voltage VCMX and higher than the ground voltage VSS.

The first comparator COMP1 is configured to compare the first reference voltage VREFP and the voltage of the first output node TXP. The first reference voltage VREFP may be transmitted to the positive input of the first comparator COMP1, and the voltage of the first output node TXP may be transmitted to the negative input of the first comparator COMP1. The first comparator COMP1 may output a high level signal when the voltage of the first output node TXP is lower than the first reference voltage VREFP. The first comparator COMP1 may output a low level signal when the voltage of the first output node TXP is higher than the first reference voltage VREFP.

The second comparator COMP2 is configured to compare the second reference voltage VREFN and the voltage of the second output node TXN. The second reference voltage VREFN may be transmitted to the negative input of the second comparator COMP2, and the voltage of the second output node TXN may be transmitted to the positive input of the second comparator COMP2. The second comparator COMP2 may output a low level signal when the voltage of the second output node TXN is lower than the second reference voltage VREFN. The second comparator COMP2 may output a high level signal when the voltage of the second output node TXN is higher than the second reference voltage VREFN.

The AND operation unit AND is configured to perform an AND operation on the output signal of the first comparator COMP1 and the output signal of the second comparator COMP2. The operation result may be output as an activation signal ACT.

When the voltage of the first output node TXP is lower than the first reference voltage VREFP, the first comparator COMP1 outputs a high level signal. When the voltage of the second output node TXN is higher than the second reference voltage VREFN, the second comparator COMP2 outputs a high level signal. Accordingly, when the voltage of the first output node TXP is lower than the first reference voltage VREFP and the voltage of the second output node TXN is higher than the second reference voltage VREFN, the receiver detector 113 is at a high level. The activation signal ACT of is outputted. That is, it is determined that the active receiving circuit RX is connected to the first output node TXP and the second output node TXN.

On the other hand, when the voltage of the first output node TXP is higher than the first reference voltage VREFP or the voltage of the second output node TXN is lower than the second reference voltage VREFN, the receiver detector 113 A low-level active signal ACT is output. That is, it is determined that the active receiving circuit RX is not connected to the first output node TXP and the second output node TXN.

5 is a circuit diagram showing a receiver 125a according to a first example of the present invention. For example, configurations associated with the first input node RXP and configurations associated with the second input node RXN may be the same. Accordingly, for concise description, configurations associated with one of the first input node RXP and the second input node RXN of the receiver 125a are shown in FIG. 5. 2 and 5, the receiver 125a includes an overvoltage control unit ESD, a termination unit TU, and a comparison unit CU.

The overvoltage controller ESD may include diodes D1 and D2 connected in series between the power node to which the power voltage VDD is supplied and the ground node to which the ground voltage VSS is supplied. The overvoltage controller ESD may prevent an overvoltage from being supplied through the first input node RXP or the second input node RXN due to external noise or internal malfunction.

For example, a positive overvoltage flowing through the first input node RXP or the second input node RXN may be discharged to the power node through the first diode D1. When the voltage of the first input node RXP or the second input node RXN is higher than the power voltage VDD by the threshold voltage of the first diode D1, the first diode D1 becomes the first input node RXP. ) Or, a current path between the second input node RXN and the power node may be formed.

For example, a negative overvoltage introduced through the first input node RXP or the second input node RXN may be discharged to the ground node through the second diode D2. When the voltage of the first input node RXP or the second input node RXN is lower than the ground voltage VSS by the threshold voltage of the second diode D2, the second diode D2 becomes the first input node RXP. ) Or, a current path between the second input node RXN and the ground node may be formed.

For example, the threshold voltage of the first diode D1 or the second diode D2 may be greater than a normal amplitude of a signal received through the first input node RXP or the second input node RXN.

The termination unit TU is configured to provide impedance matching between the transmission circuit TX and the reception circuit RX. For example, the termination unit TU may be configured to provide impedance matching to the internal resistance IR of the driver 111 and the first signal line SP or the second signal line SN. The termination unit TU includes termination resistors R and transistors TR. The termination resistors R may be connected between the transistors TR and the first input node RXP or the second input node RXN. Each of the resistors R may be connected to a power node through transistors TR. The transistors TR may have a P-type.

Gates of the transistors TR may be controlled by the gate voltage VG. For example, when the receiver 125a or the reception circuit RX including the receiver 125a is set to an active state, the transistors TR may be turned on in response to the gate voltage VG. That is, the termination resistor R is applied to the first input node RXP or the second input node RXN. When the receiver 125a or the reception circuit RX including the receiver 125a is set to an inactive state, the transistors TR may be turned off in response to the gate voltage VG. That is, the termination resistor R may not be applied to the first input node RXP or the second input node RXN. For example, the first input node RXP or the second input node RXN may be floating, and a high impedance HIGH-Z may be applied to the first input node RXP or the second input node RXN. .

The comparator CU includes a comparator COMP. The comparator COMP may compare the voltage of the first input node RXP or the second input node RXN with the reference voltage VREF. The comparison result may be transmitted to the first output node OP or the second output node ON.

6 are graphs showing changes in voltages when receiver detection is performed according to the first embodiment of the present invention. Hereinafter, with reference to the first box B1 of FIGS. 2, 4, 5, and 6, the reception in an active state at the first output node TXP and the second output node TXN of the driver 111 Changes in voltages of the first output node TXP and the second output node TXN when the circuit RX is connected will be described.

First, referring to FIG. 2, during the receiver detection operation, the driver 111 outputs a signal rising from the first common voltage VCMX through the first output node TXP, and the first common voltage VCMX A signal that decreases from may be output through the second output node TXN. For example, the driver 111 may transmit a signal rising from the first common voltage VCMX to the power voltage VDD to the internal resistance IR of the first output node TXP. In addition, the driver 111 may transmit a signal that decreases from the first common voltage VCMX to the ground voltage VSS to the internal resistance IR of the second output node TXN.

The first output node TXP and the first input node RXP are connected through a first capacitor C1. When the voltage of the first output node TXP increases, the voltage of the first input node RXP also increases due to the coupling of the first capacitor C1. The second output node TXN and the second input node RXN are connected through a second capacitor C2. When the voltage of the second output node TXN decreases, the voltage of the second input node RXN also decreases due to the coupling of the second capacitor C2.

Referring to FIG. 5, when the transistors TR are turned on, the first input node RXP or the second input node RXN is connected to the power node through termination resistors R. That is, the termination resistors R function as a load connected to the first capacitor C1 or the second capacitor C2.

Accordingly, as shown in the first box B1 of FIGS. 2 and 6, the voltage increase amount corresponding to the first output node TXP (eg, the power voltage VDD from the first common voltage VCMX) The increase amount) is distributed by the internal resistance (IR) and the termination resistances (R). For example, the voltage of the first output node TXP may rise to a level lower than the first reference voltage VREFP during the first time T1 in which the first capacitor C1 is charged.

In addition, the amount of decrease in the voltage of the second output node TXN (for example, the amount of decrease that decreases from the first common voltage VCMX to the ground voltage VSS) is determined by the internal resistance IR and the termination resistors R. Is distributed by For example, the voltage of the second output node TXN may decrease to a level higher than the second reference voltage VREFN during the first time T1 in which the second capacitor C2 is charged.

4 and 6, when the voltage of the first output node TXP is lower than the first reference voltage VREFP and the voltage of the second output node TXN is higher than the second reference voltage VREFN, high The level activation signal ACT is output. Accordingly, it is determined that the active receiving circuit RX is connected to the first output node TXP and the second output node TXN.

Hereinafter, with reference to the second box B2 of FIGS. 2, 4, 5, and 6, the reception in the active state at the first output node TXP and the second output node TXN of the driver 111 Changes in voltages of the first output node TXP and the second output node TXN when the circuit RX is not connected will be described.

Exemplarily, when the receiving circuit RX having pull-up termination is deactivated, the receiving circuit RX may charge the first input node RXP and the second input node RXN with the power supply voltage VDD. I can. For example, referring to FIG. 5, the transistors TR are turned on, and the first input node RXP and the second input node RXN may be charged with the power voltage VDD. Thereafter, the transistors TR are turned off, and the receiving circuit RX may be deactivated.

When the transistors TR are ideally open, the first input node RXP or the second input node RXN is open and has a high impedance (HIGH-Z) state. For example, as shown in the second box B2 of FIGS. 2 and 6, the second output node TXN is understood to be connected to the high impedance (HIGH-Z) through the second capacitor C2. Can be. The voltage reduction amount corresponding to the second output node TXN (for example, the reduction amount decreasing from the first common voltage VCMX to the ground voltage VSS) is determined by the internal resistance IR and the termination resistors R. It is not distributed and can be applied to the second output node TXN. Accordingly, the voltage of the second output node TXN may decrease to a level lower than the second reference voltage VREFN. For example, the voltage of the second output node TXN may decrease during a second time T2 that is faster than the first time T1.

However, when the transistors TR are not ideally open, an error may occur in which the termination resistors R are applied to the first input node RXP or the second input node RXN. An example in which a malfunction occurs in the first input node RXP or the second input node RXN is illustrated in FIG. 7.

Referring to FIG. 7, one termination resistor R and one transistor TR corresponding thereto are shown. The transistor TR includes an N-type body B, a P-type first junction J1, a P-type second junction J2, and a gate G. A gate voltage VG may be supplied to the gate G. For example, the power voltage VDD is supplied as the gate voltage VG, so that the transistor TR may be turned off. The first junction J1 may be connected to a power node to which the power voltage VDD is supplied. The second junction J2 may be connected to the second input node RXN through the termination resistor R. The power voltage VDD may be biased to the body B.

Referring to the second box B2 of FIGS. 2 and 6 and FIG. 7, the voltage of the first output node TXP may increase from the first common voltage VCMX. According to the coupling by the first capacitor C1, the voltage of the first input node RXP may also increase. For example, the voltage of the first input node RXP may increase from the power voltage VDD.

The second junction J2 and the body B of the transistor TR form a PN junction. When the voltage of the second input node RXN is higher than the power voltage VDD, leakage may occur between the body B and the second junction J2 of the transistor TR. For example, when the second junction J2 of the transistor TR and the body B are forward biased, a current path may be formed between the first input node RXP and the body B. Accordingly, the termination resistor R may be applied to the first input node RXP. The increase amount of the voltage corresponding to the first output node TXP (for example, the increase amount from the first common voltage VCMX to the power supply voltage VDD) is the internal resistance IP of the first output node TXP And termination resistors R of the first input node RXP. Accordingly, the voltage of the first output node TXP may increase to a level lower than the first reference voltage VREFP.

4, in the receiver detector 113 according to an embodiment of the present invention, the voltage of the first output node TXP is lower than the first reference voltage VREFP and the voltage of the second output node TXN is When it is higher than the second reference voltage VREFN, it is determined that the activated reception circuit RX is connected to the first output node TXP and the second output node TXN. Accordingly, even when the above-described malfunction occurs, the receiver detector 113 can normally determine whether or not the activated receiving circuit RX is connected. Accordingly, the reliability of the semiconductor device including the receiver detector 113 and the receiver detector 113 is improved.

For example, the receiver detector 113 determines the active state of the receiving circuit RX using a slope at which the voltage of the first output node TXP increases and a slope at which the voltage of the second output node TXN decreases. Can be applied to As described with reference to FIG. 6, when the receiving circuit RX is activated, the voltage of the first output node TXP or the second output node TXN rises or decreases during the first time T1. On the other hand, when the receiving circuit RX is deactivated, the voltage of the first output node TXP or the second output node TXN rises or decreases for a second time T2 shorter than the first time T1. The receiver detector 113, according to whether the voltage of the first output node (TXP) or the second output node (TXN) reaches the intermediate voltage at a third time (T3) prior to the second time (T2), the receiving circuit ( RX)'s active state can be determined. For example, the intermediate voltage may be a voltage lower than the first reference voltage VREFP and higher than the first common voltage VCMX, or a voltage higher than the second reference voltage VREFN and lower than the first common voltage VCMX.

8 is a circuit diagram showing a receiver 125b according to a second example of the present invention. For example, configurations associated with the first input node RXP and configurations associated with the second input node RXN may be the same. Therefore, for concise description, configurations associated with one of the first input node RXP and the second input node RXN of the receiver 125b are shown in FIG. 8. 2 and 8, the receiver 125a includes an overvoltage control unit ESD, a termination unit TU, and a comparison unit CU.

The overvoltage controller ESD may include diodes D1 and D2 connected in series between the power node to which the power voltage VDD is supplied and the ground node to which the ground voltage VSS is supplied. The overvoltage controller ESD may prevent an overvoltage from being supplied through the first input node RXP or the second input node RXN due to external noise or internal malfunction.

The termination unit TU is configured to provide impedance matching between the transmission circuit TX and the reception circuit RX. The termination unit TU includes termination resistors R and transistors TR. The termination resistors R may be connected between the transistors TR and the first input node RXP or the second input node RXN. Each of the resistors R may be connected to the ground node through the transistors TR. The transistors TR may have an N-type.

Gates of the transistors TR may be controlled by the gate voltage VG. For example, when the receiver 125a or the reception circuit RX including the receiver 125a is set to an active state, the transistors TR may be turned on in response to the gate voltage VG. That is, the termination resistor R is applied to the first input node RXP or the second input node RXN. When the receiver 125a or the reception circuit RX including the receiver 125a is set to an inactive state, the transistors TR may be turned off in response to the gate voltage VG. That is, the termination resistor R may not be applied to the first input node RXP or the second input node RXN.

The comparator CU includes a comparator COMP. The comparator COMP may compare the voltage of the first input node RXP or the second input node RXN with the reference voltage VREF. The comparison result may be transmitted to the first output node OP or the second output node ON.

9 are graphs showing changes in voltages when receiver detection is performed according to the second embodiment of the present invention. Hereinafter, with reference to the first box B1 of FIGS. 2, 4, 8, and 9, the first output node TXP and the second output node TXN of the driver 111 receive an active state. Changes in voltages of the first output node TXP and the second output node TXN when the circuit RX is connected will be described.

First, referring to FIG. 2, during the receiver detection operation, the driver 111 outputs a signal rising from the first common voltage VCMX through the first output node TXP, and the first common voltage VCMX A signal that decreases from may be output through the second output node TXN.

Referring to FIG. 8, when the transistors TR are turned on, the first input node RXP or the second input node RXN is connected to the ground node through termination resistors R. That is, the termination resistors R function as a load connected to the first capacitor C1 or the second capacitor C2.

Accordingly, as shown in the first box B1 of FIGS. 2 and 9, the voltage increase amount corresponding to the first output node TXP (eg, the power voltage VDD from the first common voltage VCMX) The increase amount) is distributed by the internal resistance (IR) and the termination resistances (R). For example, the voltage of the first output node TXP may rise to a level lower than the first reference voltage VREFP during the first time T1 in which the first capacitor C1 is charged.

In addition, the amount of decrease in the voltage of the second output node TXN (for example, the amount of decrease that decreases from the first common voltage VCMX to the ground voltage VSS) is determined by the internal resistance IR and the termination resistors R. Is distributed by For example, the voltage of the second output node TXN may decrease to a level higher than the second reference voltage VREFN during the first time T1 in which the second capacitor C2 is charged.

Hereinafter, with reference to the second box B2 of FIGS. 2, 4, 8, and 9, the first output node TXP and the second output node TXN of the driver 111 receive an active state. Changes in voltages of the first output node TXP and the second output node TXN when the circuit RX is not connected will be described.

Exemplarily, when the receiving circuit RX having pull-down termination is deactivated, the receiving circuit RX may charge the first input node RXP and the second input node RXN to the ground voltage VSS. I can. For example, referring to FIG. 5, the transistors TR are turned on, and the first input node RXP and the second input node RXN may be charged to the ground voltage VSS. Thereafter, the transistors TR are turned off, and the receiving circuit RX may be deactivated.

When the transistors TR are ideally open, the first input node RXP or the second input node RXN is open and has a high impedance (HIGH-Z) state. The voltage increase amount corresponding to the first output node TXP (for example, the decrease amount increasing from the first common voltage VCMX to the power supply voltage VDD) is determined by the internal resistance IR and the termination resistors R. It is not distributed and can be applied to the first output node TXP. Accordingly, the voltage of the first output node TXP may increase to a level higher than the first reference voltage VREFP. For example, the voltage of the first output node TXP may increase during a second time T2 that is faster than the first time T1.

However, when the transistors TR are not ideally open, an error may occur in which the termination resistors R are applied to the first input node RXP or the second input node RXN. An example in which a malfunction occurs in the first input node RXP or the second input node RXN is illustrated in FIG. 10.

Referring to FIG. 10, one termination resistor R and one transistor TR corresponding thereto are shown. The transistor TR includes an N-type body B, a P-type first junction J1, a P-type second junction J2, and a gate G. A gate voltage VG may be supplied to the gate G. For example, the ground voltage VSS is supplied as the gate voltage VG, so that the transistor TR may be turned off. The first junction J1 may be connected to a ground node to which the ground voltage VSS is supplied. The second junction J2 may be connected to the first input node RXP through the termination resistor R. The ground voltage VSS may be biased to the body B.

Referring to the second box B2 of FIGS. 2 and 9 and FIG. 10, the voltage of the second output node TXN may decrease from the first common voltage VCMX. According to the coupling by the second capacitor C2, the voltage of the second input node RXN may also decrease. For example, the voltage of the second input node RXN may decrease from the ground voltage VSS.

The body B and the second junction J2 of the transistor TR form a PN junction. When the voltage of the second input node RXN is higher than the ground voltage VSS, leakage may occur between the body B of the transistor TR and the second junction J2. For example, when the body B and the second junction J2 of the transistor TR are forward biased, a current path may be formed between the second input node RXN and the body B. Accordingly, the termination resistor R may be applied to the second input node RXN. The amount of decrease in the voltage corresponding to the second output node TXN (for example, the decrease amount from the first common voltage VCMX to the ground voltage VSS) is the internal resistance IP of the second output node TXN. And termination resistors R of the second input node RXN. Accordingly, the voltage of the second output node TXN may decrease to a level higher than the second reference voltage VREFN.

4, in the receiver detector 113 according to an embodiment of the present invention, the voltage of the first output node TXP is lower than the first reference voltage VREFP and the voltage of the second output node TXN is When it is higher than the second reference voltage VREFN, it is determined that the activated reception circuit RX is connected to the first output node TXP and the second output node TXN. Accordingly, even when the above-described malfunction occurs, the receiver detector 113 can normally determine whether or not the activated receiving circuit RX is connected. Accordingly, the reliability of the semiconductor device including the receiver detector 113 and the receiver detector 113 is improved.

11 is a block diagram illustrating a semiconductor system 200 according to another exemplary embodiment of the present invention. Referring to FIG. 11, the semiconductor system 200 includes a first semiconductor device 210 and a second semiconductor device 220.

The first semiconductor device 210 and the second semiconductor device 220 are configured to communicate with each other through first to Nth channels CH1 to CHN. The first semiconductor circuit 210 includes transmission/reception circuits TRX corresponding to the first to Nth channels CH1 to CHN, respectively. The second semiconductor circuit 220 includes transmission/reception circuits TRX corresponding to the first to Nth channels CH1 to CHN, respectively.

For example, in the first channel CH1, the transmission/reception circuit TRX of the first semiconductor device 210 is connected to the second semiconductor device 220 through the first signal line SP and the second signal line SN. It may be connected to the transmit/receive circuit TRX of. In the first channel CH1, the transmission/reception circuit TRX of the first semiconductor device 210 has the same structure as the transmission/reception circuit TRX of the second semiconductor device 220 and may operate in the same manner.

The first semiconductor device 210 or the second semiconductor device 220 may have a function of determining the number of active channels or the number of inactive channels. For example, the transmission/reception circuits TRX of the first semiconductor device 210 or the second semiconductor device 220 may include a receiver detection operation that determines whether an active reception circuit RX is connected.

12 shows a transmission/reception circuit TRX according to another embodiment of the present invention. For example, one of the transmission/reception circuits TRX of the first semiconductor device 210 or the second semiconductor device 220 is illustrated in FIG. 12.

11 and 12, the transmission/reception circuit TRX includes a transmission circuit TX and a reception circuit RX. The transmission circuit TX includes a driver 211 and a receiver detector 213. The transmission circuit TX has the same structure as the transmission circuit TX described with reference to FIGS. 1 to 10 and can operate in the same manner. The receiving circuit RX includes first and second capacitors C1 and C2, a receiver 215, and a balance circuit 217. The reception circuit RX has the same structure as the reception circuit RX described with reference to FIGS. 1 to 10 and can operate in the same manner.

The transmission circuit TX and the reception circuit RX may share the first signal line SP and the second signal line SN. The first signal line SP may be connected in common to the first output node TXP of the transmitter 211 of the transmission circuit TX and the first capacitor C1 of the reception circuit RX. The second signal line SN may be connected in common to the second output node TXN of the transmitter 211 of the transmission circuit TX and the second capacitor C2 of the reception circuit RX. The transmission/reception circuit TRX may perform bidirectional communication using the first signal line SP and the second signal line SN.

As described with reference to FIGS. 1 to 10, the receiver detector 213 of the transmission circuit TX includes a receiving circuit in an active state of another semiconductor device at the first output node TXP and the second output node TXN. It is possible to determine whether (RX) is connected. For example, the receiver detector 211 of the transmission circuit TX of the transmission/reception circuit TRX of the first semiconductor device 210 may determine whether the transmission/reception circuit TRX of the second semiconductor device 220 is connected or the second It can be determined whether the reception circuit RX of the corresponding transmission/reception circuit TRX of the semiconductor device 220 is active.

When the receiver detector 211 of the transmission circuit TX of the transmission/reception circuit TRX of the first semiconductor device 210 performs a receiver detection operation, the reception circuit RX belonging to the same transmission/reception circuit TRX is deactivated. I can. For example, the termination resistors R of the receiver 215 of the receiving circuit RX may be electrically separated from the first input node RXP and the second input node RXN by the transistors TR. have.

13 is a block diagram illustrating a computing device 1000 according to an embodiment of the present invention. Referring to FIG. 13, the computing device 1000 includes a processor 1100, a memory 1200, a storage device 1300, a modem 1400, and a user interface 1500.

The processor 1100 may control all operations of the computing device 1000 and may perform logical operations. For example, the processor 1100 may be configured as a system-on-chip (SoC). The processor 1100 may be a general purpose processor, a special purpose processor, or an application processor.

The RAM 1200 may communicate with the processor 1100. The RAM 1200 may be the processor 1100 or the main memory of the computing device 1000. The processor 1100 may temporarily store code or data in the RAM 1200. The processor 1100 may execute code and process data using the RAM 1200. The processor 1100 may execute various software such as an operating system and an application using the RAM 1200. The processor 1100 may control all operations of the computing device 1000 using the RAM 1200. RAM 1200 is a volatile memory such as SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM), etc., or PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FeRAM ( Ferroelectric RAM) and the like.

The storage device 1300 may communicate with the processor 1100. The storage device 1300 may store data to be stored for a long time. That is, the processor 1100 may store data to be stored for a long time in the storage device 1300. The storage device 1300 may store a boot image for driving the computing device 1000. The storage device 1300 may store source codes of various software such as an operating system and an application. The storage device 1300 may store data processed by various software such as an operating system and an application.

For example, the processor 1100 loads source codes stored in the storage device 1300 into the RAM 1200 and executes the codes loaded in the RAM 1200, thereby driving various software such as an operating system and an application. have. The processor 1100 may load data stored in the storage device 1300 into the RAM 1200 and process the data loaded into the RAM 1200. The processor 1100 may store data to be stored in the RAM 1200 for a long period of time in the storage device 1300.

The storage device 1300 may include nonvolatile memory such as flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like.

The modem 1400 may communicate with an external device under the control of the processor 1100. For example, the modem 1400 may perform wired or wireless communication with an external device. Modem 140 is LTE (Long Term Evolution), WiMax (WiMax), GSM (Global System for Mobile communication), CDMA (Code Division Multiple Access), Bluetooth (Bluetooth), NFC (Near Field Communication), Wi-Fi (WiFi) , Various wireless communication methods such as RFID (Radio Frequency IDentification), or USB (Universal Serial Bus), SATA (Serial AT Attachment), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), Firewire , PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), SDIO, UART (Universal Asynchronous Receiver Transmitter), SPI (Serial Peripheral Interface) , HS-SPI (High Speed SPI), RS232, I2C (Inter-integrated Circuit), HS-I2C, I2S, (Integrated-interchip Sound), S/PDIF (Sony/Philips Digital Interface), MMC (MultiMedia Card), Communication may be performed based on at least one of various wired communication methods such as eMMC (embedded MMC).

The user interface 1500 may communicate with a user under the control of the processor 1100. For example, the user interface 1500 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, and the like. The user interface 150 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix OLED (AMOLED) display, an LED, a speaker, and a motor.

The processor 110, the RAM 1200, the storage device 1300, the modem 1400, and the user interface 1500 may correspond to the first semiconductor device 110 or 210 or the second semiconductor device 120 or 220, respectively. I can. That is, the transmission circuits TX and the reception circuits RX or the transmission/reception circuits TRX according to an embodiment of the present invention include the processor 110, the RAM 1200, the storage device 1300, and the modem 1400. And, it may be configured to perform communication between at least two of the user interface 1500.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope and technical spirit of the present invention. Therefore, the scope of the present invention should not be defined by being limited to the above-described embodiments, and should be defined by the claims and equivalents of the present invention as well as the claims to be described later.

100, 200; Semiconductor systems 110 and 210; First semiconductor device
120, 220; Second semiconductor devices 111 and 213; transmitter
113. 213; Receiver detectors 125, 215; receiving set
127, 217; Balance circuit 1100; Processor
1200; Random access memory 1300; Storage device
1400; Modem 1500; User interface

Claims (10)

During normal operation, a driver configured to output a complementary first signal and a second signal through the first node and the second node, respectively; And
In the receiver detection operation, including a receiver detector configured to determine whether an active receiving circuit is connected to the first node and the second node according to the voltage of the first node and the voltage of the second node,
The receiver detector, during the receiver detection operation, compares the voltage of the first node with a first reference voltage, compares the voltage of the second node with a second reference voltage, and compares the voltage of the first node A semiconductor device configured to determine whether the active receiving circuit is connected according to a result and a comparison result of the voltage of the second node. The method of claim 1,
The receiver detector,
When the voltage of the first node is higher than the first reference voltage or the voltage of the second node is lower than the second reference voltage lower than the first reference voltage, to determine that the receiving circuit in the active state is not connected Consisting of semiconductor device. The method of claim 1,
The receiver detector,
A semiconductor configured to determine that the receiving circuit in the active state is connected when the voltage of the first node is lower than the first reference voltage and the voltage of the second node is higher than the second reference voltage lower than the first reference voltage Device. The method of claim 1,
The receiver detector,
A first comparator configured to output a high level when the voltage of the first node is lower than a first reference voltage;
A second comparator configured to output a high level when the voltage of the second node is higher than a second reference voltage; And
And a logic gate configured to output an logical product of an output of the first comparator and an output of the second comparator,
When the output of the logic gate is at a high level, it is determined that the receiving circuit in the active state is connected. The method of claim 4,
The receiver detector,
Further comprising first to fourth resistors connected in series between the power node to which the power voltage is supplied and the ground node to which the ground voltage is supplied,
A voltage of a node between the first resistor and the second resistor adjacent to the power node is used as the first reference voltage,
A semiconductor device in which a voltage of a node between the third resistor and the fourth resistor adjacent to the ground node is used as the second reference voltage. The method of claim 1,
During the receiver detection operation, the driver outputs a signal that increases from a common voltage to a first voltage higher than the common voltage through the first node, and is lower than the common voltage from the common voltage through the second node. A semiconductor device configured to output a signal that decreases to a second voltage. A first semiconductor device including transmission circuits;
A second semiconductor device including receiving circuits; And
Including channels respectively connecting the transmitting circuits and the receiving circuits,
Each of the transmitting circuits is connected to a corresponding receiving circuit among the receiving circuits through a first signal line and a second signal line of a corresponding channel among the channels,
Each of the transmission circuits is configured to determine whether the corresponding reception circuit is active according to a voltage of the first signal line and a voltage of the second signal line, and to be deactivated when the corresponding reception circuit is inactive. Semiconductor system. The method of claim 7,
The first semiconductor device further includes second receiving circuits,
The second semiconductor device further includes second transmission circuits,
The semiconductor device further includes second channels respectively connecting the second transmission circuits and the second reception circuits. The method of claim 7,
The first semiconductor device further includes second receiving circuits,
The second semiconductor device further includes second transmission circuits,
The second transmission circuits are respectively connected to the second reception circuits through the channels. A method of operating a semiconductor device including a transmission circuit configured to output a first signal and a second signal through a first node and a second node, respectively:
Outputting the first signal increasing from a common voltage to a first voltage through the first node, and outputting the second signal decreasing from the common voltage to a second voltage through the second node;
Detecting voltages of the first node and the second node; And
Determining whether an active receiving circuit is connected to the first node and the second node according to the voltage of the first node and the voltage of the second node,
The determining step,
Comparing the voltage of the first node with a first reference voltage;
Comparing the voltage of the second node with a second reference voltage; And
And determining whether the active receiving circuit is connected according to a comparison result of the voltage of the first node and the voltage of the second node.

Images