KR102226284B1 - System-on-chip and driving method thereof - Google Patents

Abstract

A system-on-chip according to an embodiment of the present invention includes a master, a slave, and a first-in first-out (FIFO) connected to the master and the slave, and the The FIFO write operation is controlled by comparing the FIFO write pointer and the predicted write pointer, and the FIFO read pointer and the predicted read pointer are determined. In comparison, it includes an asynchronous interface for controlling the read operation of the FIFO.

Description

System-on-chip and its driving method {SYSTEM-ON-CHIP AND DRIVING METHOD THEREOF}

The present invention relates to a system on chip, and when a master and a slave are located at a distance and have different clock domains, a write pointer of a FIFO for stably transmitting data The present invention relates to a system-on-chip for controlling read and write operations of the FIFO so as to maintain a constant interval between the read pointer and the read pointer, and a driving method thereof.

When the clock domain is different between the master and the slave, an asynchronous interface may be used. The asynchronous interface may include first-in first-out (FIFO). The FIFO contains a write pointer and a read pointer.

When the write pointer and the read pointer cannot maintain a constant interval due to various uncertainties, the FIFO may have a full or empty state. Due to this, the protocol between the master and the slave may be broken.

An object of the present invention is to provide a system-on-chip capable of compensating for a write pointer or a read pointer in order to maintain a constant interval between a write pointer and a read pointer of a FIFO in the case of a remote interface having a different clock domain.

Another object of the present invention is to provide a method of driving the system-on-chip.

Another object of the present invention is to provide a mobile device including the system-on-chip.

In order to achieve the above object, a system-on-chip according to an embodiment of the present invention includes a master, a slave, and a first-in first-out (FIFO) connected to the master and the slave. ), and controlling a write operation of the FIFO by comparing a write pointer of the FIFO with an expected write pointer, and a read pointer and a predicted read pointer of the FIFO It includes an asynchronous interface for controlling the read operation of the FIFO by comparing (expected read pointer).

In one embodiment, the asynchronous interface includes a slave interface and a master interface, and the slave interface includes a slave sender, a slave clock domain crossing (CDC) block, and a slave receiver, and the master interface includes a master sender and a master interface. It includes a CDC block and a master receiver, each of the slave interface and the master interface has the same structure and performs the same operation, and each of the slave CDC block and the master CDC block includes the FIFO.

In one embodiment, the asynchronous interface generates a write enable signal for controlling a write operation of the FIFO according to a comparison result of the write pointer and the predicted write pointer.

In one embodiment, the FIFO stores data at an address indicated by the write pointer while the write activation signal is activated.

In one embodiment, the asynchronous interface generates a read enable signal for controlling a read operation of the FIFO according to a result of comparing the read pointer and the predicted read pointer.

In one embodiment, the FIFO transmits data stored in an address indicated by the read pointer to the master receiver or the slave receiver while the read activation signal is activated.

In one embodiment, the asynchronous interface may maintain a constant interval between the read pointer and the write pointer.

In one embodiment, the predicted read pointer is calculated based on the write pointer and the interval, and the predicted write pointer is calculated based on the read pointer and the interval.

In one embodiment, the asynchronous interface connects the master and the slave when the clock domains of the master and the slave are different from each other.

In one embodiment, a period for compensating the read pointer is determined using a most significant bit (MSB) of the write pointer, and a period for compensating the write pointer is determined using an MSB of the read pointer do.

A method of driving a system-on-chip according to another embodiment of the present invention includes an asynchronous interface including a master, a slave, and a first-in first-out (FIFO) for connecting the master and the slave. A method of driving a system-on-chip including an asynchronous interface, comprising: comparing a write pointer of the FIFO with an expected write pointer, and comparing the compared result. And controlling the write operation of the FIFO.

In one embodiment, the asynchronous interface includes a slave interface and a master interface, and the slave interface includes a slave sender, a slave clock domain crossing (CDC) block, and a slave receiver, and the master interface includes a master sender and a master interface. It includes a CDC block and a master receiver, each of the slave interface and the master interface has the same structure and performs the same operation, and each of the slave CDC block and the master CDC block includes the FIFO.

In an embodiment, the method includes comparing a read pointer of the FIFO with an expected read pointer, and controlling a read operation of the FIFO based on the compared result. .

In one embodiment, the asynchronous interface controls activation of a write enable signal for controlling a write operation of the FIFO according to a comparison result of the write pointer and the predicted write pointer, and the FIFO Stores data at an address indicated by the write pointer while the write activation signal is activated.

In one embodiment, the asynchronous interface controls activation of a read enable signal for controlling a read operation of the FIFO according to a comparison result of the read pointer and the predicted read pointer, and the FIFO While the read activation signal is activated, data stored at an address indicated by the read pointer is transmitted to the master receiver or the slave receiver.

A computer system according to another embodiment of the present invention includes a memory device and a system-on-chip for controlling the memory device, and the system-on-chip includes a master and a slave. (slave) and a first-in first-out (FIFO) for connecting the master and the slave, and the FIFO by comparing a write pointer of the FIFO with a predicted write pointer And an asynchronous interface that controls a read operation of the FIFO and controls a read operation of the FIFO by comparing a read pointer of the FIFO with an expected read pointer.

In one embodiment, the asynchronous interface includes a slave interface and a master interface, and the slave interface includes a slave sender, a slave clock domain crossing (CDC) block, and a slave receiver, and the master interface includes a master sender and a master interface. It includes a CDC block and a master receiver, each of the slave interface and the master interface has the same structure and performs the same operation, and each of the slave CDC block and the master CDC block includes the FIFO.

In one embodiment, the asynchronous interface generates a write enable signal for controlling a write operation of the FIFO according to a comparison result of the write pointer and the predicted write pointer, and the FIFO is the While the write activation signal is activated, data is stored at an address indicated by the write pointer.

In one embodiment, the asynchronous interface generates a read enable signal for controlling a read operation of the FIFO according to a comparison result of the read pointer and the predicted read pointer, and the FIFO is the While the read activation signal is activated, data stored at an address indicated by the read pointer is transmitted to the master receiver or the slave receiver.

In one embodiment, the system-on-chip includes an application processor.

In the case of a remote interface having a different clock domain, the system-on-chip according to an embodiment of the present invention may control the FIFO so that the interval between the write pointer and the read pointer of the FIFO can be kept constant when the CPU and the main bus are connected.

In addition, the system-on-chip can prevent the FIFO from becoming full or empty.

1 is a block diagram showing a system-on-chip according to an embodiment of the present invention.
2 is a block diagram showing a system-on-chip according to another embodiment of the present invention.
3 is a block diagram showing in detail the system-on-chip shown in FIG. 2.
4A is a block diagram illustrating a process of transmitting data from the CPU 10 to the main bus 20.
4B is a block diagram illustrating a process of transmitting data from the main bus 20 to the CPU 10.
FIG. 5 is a timing diagram showing the clocks of the CPU and the main bus shown in FIG. 3, and a method of generating a gated clock using the clocks of the CPU and the main bus.
6 is a block diagram showing in detail the master FIFO shown in FIG. 4A or the slave FIFO shown in FIG. 4B.
7 is a timing diagram illustrating a write activation signal shown in FIG. 4A or 4B.
8 is a timing diagram illustrating a read activation signal shown in FIG. 4A or 4B.
9 shows an embodiment of a computer system 210 including a system-on-chip shown in FIG. 1.
10 shows another embodiment of a computer system 220 including a system-on-chip shown in FIG. 1.
FIG. 11 shows a digital camera device 300 including a system-on-chip shown in FIG. 1.
12A and 12B illustrate a wearable device including a system-on-chip shown in FIG. 1.
13 shows a wearable device 500 including the system-on-chip shown in FIG. 1.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are exemplified for the purpose of describing the embodiments of the present invention only, and the embodiments of the present invention may be implemented in various forms. It should not be construed as being limited to the described embodiments.

In the present invention, various modifications may be made and various forms may be applied, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form disclosed, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. It should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the existence of disclosed features, numbers, steps, actions, components, parts, or a combination thereof, but one or more other features or numbers, It is to be understood that the presence or addition of steps, actions, components, parts or combinations thereof does not preclude the possibility of preliminary exclusion.

Unless otherwise defined, all terms used herein including technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessive formal meaning unless explicitly defined in this application. Does not.

Meanwhile, when a certain embodiment can be implemented differently, a function or operation specified in a specific block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be executed at the same time, or the blocks may be executed in reverse, depending on a related function or operation.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing a system-on-chip according to an embodiment of the present invention.

Referring to FIG. 1, a system-on-chip (1) includes a master (2), a slave (3), and an asynchronous interface (4) connecting the master (2) and the slave (3). Includes. In one embodiment, the master 2 may include any one of a Central Processing Unit (CPU), Direct Memory Access (DMA), and a 3-Dimensional Graphic Accelerator. Further, the slave 3 may include a main bus 20.

The asynchronous interface 4 includes a slave interface 5 and a master interface 6. The slave interface 5 and the master interface 6 will be described in detail in FIGS. 2 and 3.

The asynchronous interface 4 can be applied when the clock domains are different from each other. For example, the master 2 may operate in synchronization with a master clock. In addition, the slave 3 may operate in synchronization with a slave clock. The asynchronous interface 4 can connect between the master 2 and the slave 3.

The asynchronous interface 4 may include a first-in first-out (FIFO) for connecting the master 2 and the slave 3. The FIFO contains a read pointer and a write pointer. When the write pointer and the read pointer do not maintain a constant distance, the FIFO may have a full or empty state. Due to this, transmission between the master 2 and the slave 3 may be broken.

The system-on-chip 1 according to an embodiment of the present invention may maintain an interval between a write pointer and a read pointer of a FIFO. A method of maintaining an interval between a write pointer and a read pointer will be described in detail with reference to FIG. 3.

2 is a block diagram showing a system-on-chip according to another embodiment of the present invention.

Referring to FIG. 2, a system-on-chip (1) is a central processing unit (CPU) 10, a main bus 20, and first to third blocks 31-33. Includes. In one embodiment, the system-on-chip 1 may be applied to a mobile device or a wearable device.

In addition, the system-on-chip 1 includes a first asynchronous interface 15 connecting the CPU 10 and the main bus 20, and the main bus 20 and the first to third blocks 31-33, respectively. It may further include a second asynchronous interface 25 for connecting. The first to third blocks 31-33 refer to functional blocks that perform a function.

The first asynchronous interface 15 may include a first slave interface 16 and a first master interface 17. In addition, the second asynchronous interface 25 may include a second slave interface 26 and second to fourth master interfaces 27-29. The slave interface and the master interface will be described in detail in FIGS. 3, 4A and 4B.

Each of the first and second asynchronous interfaces 15 and 25 may be applied when the clock domains are different from each other. For example, the CPU 10 will operate in synchronization with the CPU clock. In addition, the main bus 20 will operate in synchronization with a bus clock. The first asynchronous interface 15 may connect the CPU 10 and the main bus 20.

Similarly, each of the first to third blocks 31-33 will operate in synchronization with their respective operation clocks. The second asynchronous interface 25 may connect the main bus 20 and the first to third blocks 31-33.

The CPU 10 may access the first to third blocks 31-33 through the main bus 20. For example, the CPU 10 may receive data from the first block 31 through the main bus 20. In addition, the CPU 10 may transmit data to the first block 31 through the main bus 20. In addition, the CPU 10 may receive data from the second block 32 through the main bus 20. In addition, the CPU 10 may transmit data to the second block 32 through the main bus 20. Likewise, the CPU 10 may receive data from the third block 33 via the main bus 20. In addition, the CPU 10 may transmit data to the third block 33 through the main bus 20.

In one embodiment, the CPU 10 may include an ARM processor. In addition, each of the first to third blocks 31 to 33 may include a memory device.

Meanwhile, the CPU 10 may operate in synchronization with a CPU clock. In addition, the main bus 20 may operate in synchronization with a bus clock. When the clock domains of the CPU 10 and the main bus 20 are different from each other, the first asynchronous interface 15 may include a first-in first out (FIFO) for storing data.

Likewise, the main bus 20 may operate in synchronization with a bus clock. Also, the first block 31 may operate in synchronization with a memory operation clock. When the clock domains of the main bus 20 and the first block 31 are different from each other, the second asynchronous interface 25 may include a FIFO for storing data.

If the FIFO is in a full/empty state, the performance of the system-on-chip 1 may deteriorate each time. Accordingly, the system-on-chip 1 can control the FIFO so that it is not in a full/empty state.

The system-on-chip 1 according to an embodiment of the present invention may compensate for a write pointer or a read pointer in order to maintain a constant interval between a write pointer and a read pointer of a FIFO. . A method of maintaining a constant interval between a write pointer and a read pointer will be described in FIG. 4A or 4B.

3 is a block diagram showing in detail the system-on-chip shown in FIG. 2.

2 and 3, a CPU 10, a first asynchronous interface 15, and a main bus 20 are shown in FIG. 3. The first asynchronous interface 15 according to an embodiment of the present invention may include a slave interface 16, a master interface 17, and a clock management unit 18.

The slave interface 16 includes a slave sender 16A, a slave clock domain crossing block 16B, and a slave receiver 16C. Similarly, the master interface 17 includes a master sender 17A, a master clock domain crossing block 17B, and a master receiver 17C.

The slave interface 16 and the master interface 17 have the same structure and perform the same operation.

The CPU 10 may transmit data to the main bus 20 through the slave interface 16 and the master interface 17. Specifically, the slave sender 16A may transmit data to the master receiver 17C through the master CDC block 17B. The master CDC block 17B includes a FIFO that stores data transmitted from the slave sender 16A. The writing operation in which the CPU 10 transmits data to the main bus 20 will be described in detail in FIG. 4A.

In addition, the main bus 20 may transmit data to the CPU 10 through the slave interface 16 and the master interface 17. Specifically, the master sender 17A may transmit data to the slave receiver 16C through the slave CDC block 16B. The slave CDC block 16B includes a FIFO that stores data transmitted from the master sender 17A. The read operation in which the CPU 10 receives data from the main bus 20 will be described in detail in FIG. 4B.

The clock management unit 18 may transmit clock information between the CPU 10 and the main bus 20 to the slave interface 16 and the master interface 17. For example, the clock management unit 18 transmits information (F_CCLK) about the CPU clock, which is the operation clock of the CPU 10, and information about the bus clock (F_BCLK), which is the operation clock of the main bus 20, to the slave interface 16. ) And the master interface 17.

In FIG. 3, the CPU 10 and the main bus 20 are only one embodiment of a first IP (intellectual property) and a second IP, respectively, but are not limited thereto and may be different IPs. Accordingly, when the first IP operates as a slave, the slave interface 16 can operate as a master interface, and when the second IP operates as a master, the master interface 17 can operate as a slave interface.

4A is a block diagram illustrating a process of transmitting data from the CPU 10 to the main bus 20. 4B is a block diagram illustrating a process of transmitting data from the main bus 20 to the CPU 10. That is, FIG. 4A describes the write operation of the CPU 10, and FIG. 4B describes the read operation of the CPU 10.

3 and 4A, the asynchronous interface 15 may include a slave sender 16A, a master CDC block 17B, and a master receiver 17C.

The slave sender 16A and the master CDC block 17B are in the same clock domain. Further, the master receiver 17C is in a different clock domain from the slave center 16A and the master CDC block 17B. That is, the read operation and the write operation of the master FIFO 17B_1 may be performed in different clock domains. For example, the CPU 10 can operate in synchronization with the CPU clock. The main bus 20 may operate in synchronization with a bus clock.

If the CPU clock is faster than the bus clock, the slave sender 16A synchronizes with the gated clock (GCLK) generated according to the speed ratio of the CPU clock and the bus clock to transfer the data D to the master FIFO. Will be transferred to (17B_1). That is, the gated clock may be generated so that the amount of data to be read and the amount of data to be written between the different clock domains are substantially the same by referring to the speed ratio of asynchronous clocks in different clock domains. A method of generating the gated clock GCLK will be described with reference to FIG. 5.

The slave sender 16A may include a first slave synchronizer 16A_1 and a slave write disable logic 16A_2. The first slave synchronizer 16A_1 may execute a buffer function for stably transmitting data. The slave write deactivation logic 16A_2 may deactivate a slave write enable signal (S_WE).

The master CDC block 17B may include a master first-in first-out (FIFO) 17B_1, a second master synchronizer 17B_2, and a master write interval checker 17B_3.

The master FIFO 17B_1 may store data D transmitted from the slave sender 16A in synchronization with the gated clock GCLK.

For example, the master FIFO 17B_1 may store data to be stored in the memory device through the main bus 20 for a write operation of the CPU 10. The master FIFO 17B_1 includes a write pointer WPTR indicating an address in which data is stored and a read pointer RPTR indicating an address to read data from. That is, the master FIFO 17B_1 may store data for a write operation of the CPU 10 according to the write pointer WPTR. In addition, the master FIFO 17B_1 may transmit the stored data to the main bus 20 through the master receiver 17C according to the read pointer RPTR. The write pointer WPTR and the read pointer RPTR of the master FIFO 17B_1 will be described in detail with reference to FIG. 6.

The second master synchronizer 17B_2 may have a depth for stably receiving the current read pointer RPTR from the master receiver 17C. The depth of the synchronizer means the number of clock cycles defined in order to synchronize the received signal and deliver the correct value.

The master write interval checker 17B_3 may generate an expected write pointer (EWPTR). As an embodiment, the master write interval checker 17B_3 may generate the predicted write pointer EWPTR according to Equation 1. The master write interval checker 17B_3 compares the current write pointer WPTR and the predicted write pointer EWPTR. The master write interval checker 17B_3 transmits the compared result to the slave write deactivation logic 16A_2 through the first slave synchronizer 16A_1.

The slave write deactivation logic 16A_2 may deactivate the slave write activation signal S_WE in response to the compared result. When the current write pointer WPTR is smaller than the predicted write pointer EWPTR, the slave write activation signal S_WE may be deactivated for one clock cycle. For example, if the current write pointer WPTR is 3'b011 and the predicted write pointer is 3'b010, the slave write deactivation logic 16A_2 generates a slave write activation signal S_WE in response to the compared result. During the clock, it can be disabled. The slave write activation signal S_WE will be described in detail with reference to FIG. 7.

The read pointer RPTR represents a value of a pointer for reading data D from the master FIFO 17B_1. The predicted read pointer ERPTR may be recognized by the master CDC block 17B, which is another clock domain, through the second master synchronizer 17B_2. When a signal is transmitted between asynchronous clock domains, a time point at which the signal is stably transmitted may be delayed for a clock modification due to jitter of the PLL of each clock domain or for stable signal transmission between different clock domains. For example, the read timing of the master FIFO 17B_1 cannot be accurately known from the master CPU 10. In order to solve this problem, the predicted read pointer ERPTR may be used instead of the read pointer RPTR.

In addition, the master write interval checker 17B_3 may calculate the predicted write pointer EWPTR based on the current read pointer RPTR and an interval between the write pointer WPTR and the read pointer RPTR. Here, the interval is a predetermined value that can be set in advance before data transmission, and means an interval to be maintained between the write pointer WPTR and the read pointer RPTR. That is, the predicted write pointer EWPTR means a target write pointer and can be expressed by Equation 1. Referring to Equation 1, a stably synchronized read pointer is generated by adding the depth of the second master synchronizer 17B_2 to the current read pointer RPTR, and a predetermined interval is added to the synchronized read pointer to be a target write pointer. The predicted light pointer (EWPTR) can be obtained. For example, if the depth of the second master synchronizer 17B_2 is 3, the interval is 3, and the current read pointer RPTR is 4, the predicted write pointer EWPTR is 10. In addition, when the size of the predicted write pointer EWPTR is 3-bit, the pointer is changed in a round robin manner, so that the predicted write pointer EWPTR becomes 2.

[ Equation One]

Predicted write pointer (EWPTR) = current read pointer + depth of the second master synchronizer 17B_2 + interval

The master receiver 17C includes a third master synchronizer 17C_1, a master read interval checker 17C_2, and a master read disable logic 17C_3.

The third master synchronizer 17C_1 may have a predetermined depth in order to stably receive the current write pointer WPTR.

The master read interval checker 17C_2 may generate an expected read pointer (ERPTR). As an embodiment, the master read interval checker 17C_2 may generate the predicted read pointer ERPTR according to Equation (2). The predicted read pointer ERPTR denotes a target read pointer and can be represented by Equation 2 Referring to Equation 2, a stably synchronized write pointer is generated by adding the depth of the third master synchronizer 17C_1 to the current write pointer WPTR, and a predetermined interval is subtracted from the synchronized write pointer to be a target read pointer. The predicted read pointer ERPTR can be obtained. The master read interval checker 17C_2 may compare the current read pointer RPTR and the predicted read pointer ERPTR.

The master read interval checker 17C_2 transmits the compared result to the master read deactivation logic 17C_3. The master read deactivation logic 17C_3 may deactivate the master read activation signal M_RE in response to the compared result. When the current read pointer RPTR is larger than the predicted read pointer ERPTR, the master read activation signal M_RE may be deactivated for one clock cycle. For example, if the current read pointer RPTR is 3'b001 and the predicted read pointer is 3'b000, the master read deactivation logic 17C_3 generates a master read activation signal M_RE in response to the compared result. During the clock, it can be disabled. The master read activation signal M_RE will be described in detail in FIG. 8.

Also, the master read interval checker 17C_2 may calculate the predicted read pointer ERPTR based on the current write pointer WPTR and the interval. That is, the predicted read pointer ERPTR may be represented by Equation 2. For example, if the depth of the third master synchronizer 17C_1 is 3, the interval is 3, and the current write pointer WPTR is 4, the predicted read pointer ERPTR is 4.

[ Equation 2]

Predicted read pointer (ERPTR) = current write pointer + depth of the third master synchronizer 17C_1-interval

3 and 4B, the asynchronous interface 15 may include a slave CDC block 16B, a slave receiver 16C, and a master sender 17A.

The master sender 17A and the slave CDC block 16B are in the same clock domain. That is, the read operation and the write operation of the slave FIFO 16B_1 may be performed in different clock domains. For example, the CPU 10 can operate in synchronization with the CPU clock. The main bus 20 may operate in synchronization with a bus clock. When the CPU clock is faster than the bus clock, the master sender 17A synchronizes with the gated clock (GCLK), which adjusts the CPU clock according to the speed ratio of the CPU clock and the bus clock, and transfers the data D to the slave FIFO It can be transmitted to (16B_1). That is, the gated clock may be generated so that the amount of data to be read and the amount of data to be written between the different clock domains are substantially the same by referring to the speed ratio of asynchronous clocks in different clock domains.

The master sender 17A may include a first master synchronizer 17A_1 and a master write disable logic 17A_2. The first master synchronizer 17A_1 may perform a buffer function for stably transmitting data.

The master write deactivation logic 17A_2 may deactivate a master write enable signal (M_WE).

The slave CDC block 16B may include a slave first-in first-out (FIFO) 16B_1, a second slave synchronizer 16B_2, and a slave write interval checker 16B_3.

The slave FIFO 16B_1 may store data D transmitted from the master sender 17A in synchronization with the gated clock GCLK.

For example, the slave FIFO 16B_1 may store data read from the memory device through the main bus 20 for a read operation of the CPU 10. The slave FIFO 16B_1 includes a write pointer WPTR indicating an address in which data is stored and a read pointer RPTR indicating an address to read data from. That is, the slave FIFO 16B_1 may store data for a read operation of the CPU 10 according to the write pointer WPTR. In addition, the slave FIFO 16B_1 may transmit the stored data to the CPU 10 through the slave receiver 16C according to the read pointer RPTR. The write pointer WPTR and the read pointer RPTR of the slave FIFO 16B_1 will be described in detail with reference to FIG. 6.

The second slave synchronizer 16B_2 may have a depth in order to stably receive the current read pointer RPTR.

The slave write interval checker 16B_3 may generate the predicted write pointer EWPTR. As an embodiment, the slave write interval checker 16B_3 may generate the predicted write pointer EWPTR according to Equation (1). The slave write interval checker 16B_3 compares the current write pointer WPTR and the predicted write pointer EWPTR. The slave write interval checker 16B_3 transmits the compared result to the master write deactivation logic 17A_2 through the first mast synchronizer 17A_1.

The master write deactivation logic 17A_2 may deactivate the master write activation signal M_WE in response to the compared result. For example, if the current write pointer WPTR is 3'b011 and the predicted write pointer is 3'b010, the master write deactivation logic 17A_2 generates a write activation signal WE in response to the compared result. While, it can be deactivated. The write activation signal WE will be described in detail in FIG. 7.

In addition, the slave write interval checker 16B_3 may calculate the predicted write pointer EWPTR based on the current read pointer RPTR and an interval between the write pointer WPTR and the read pointer RPTR. That is, the predicted write pointer EWPTR can be represented by Equation 1.

The slave receiver 16C includes a third slave synchronizer 16C_1, a slave read interval checker 16C_2, and a slave read disable logic 16C_3.

The third slave synchronizer 16C_1 may stably receive the current write pointer WPTR.

The slave read interval checker 16C_2 may generate the predicted read pointer ERPTR. As an embodiment, the slave read interval checker 16C_2 may generate the predicted read pointer ERPTR according to Equation (2). The slave read interval checker 16C_2 may compare the current read pointer RPTR and the predicted read pointer ERPTR.

The slave read interval checker 16C_2 transmits the compared result to the slave read deactivation logic 16C_3. The slave read deactivation logic 16C_3 may deactivate the slave read activation signal S_RE in response to the compared result. For example, if the current read pointer RPTR is 3'b001 and the predicted read pointer is 3'b000, the slave read deactivation logic 16C_3 generates a slave read activation signal S_RE in response to the compared result. During the clock, it can be disabled. The slave read activation signal S_RE will be described in detail with reference to FIG. 8.

In addition, the slave read interval checker 17C_2 may calculate the predicted read pointer ERPTR based on the current write pointer WPTR and the interval. That is, the predicted read pointer ERPTR may be represented by Equation 2.

Referring to FIGS. 1 to 4B, it is important to maintain the same amount of data input and output in the system-on-chip 1. However, when data is transmitted over a long distance between different clock domains, various uncertainties may exist.

Uncertainty can be caused by asynchronously between the CPU clock and the bus clock. In addition, the uncertainty may be generated by the synchronizers 16A_1, 17B_2, and 17C_1 performing a buffer function. Finally, uncertainty may be generated by accumulation of jitter when different phase locked loops (PLLs) are used. Therefore, if the influence due to uncertainty is not compensated for, the interval between the write pointer WPTR and the read pointer RPTR may change. That is, the master FIFO 17B_1 or the slave FIFO 16B_1 may cause a full/empty state or an overrun/underrun state.

In order to solve this problem, the system-on-chip 1 according to the embodiment of the present invention checks the interval between the write pointer (WPTR) and the read pointer (RPTR) of the master FIFO (17B_1) or slave FIFO (16B_1) at regular intervals. Determine whether to compensate. For example, when the depth of the master FIFO 17B_1 or the slave FIFO 16B_1 is 8, the check period may be set to 8, 16, 24, or 32 cycles. In addition, the compensation method may deactivate the write activation signal WE or the read activation signal RE in order to continue maintaining the initially set interval.

The period for compensating the write pointer WPTR may be determined using the most significant bit (MSB) of the write pointer WPTR or the read pointer RPTR. For example, when the write pointer WPTR or the read pointer RPTR is composed of 3 bits, the period of the rising edge of the MSB of the write pointer WPTR or the read pointer RPTR is 8 cycles. When the MSB of the write pointer WPTR or the read pointer RPTR is used, the compensation period of the write pointer WPTR may be 8 cycles. Likewise, a period for compensating the read pointer RPTR may be determined using the write pointer WPTR or the MSB of the read pointer RPTR.

If compensation is required, the system-on-chip 1 generates a master write activation signal (M_WE), a slave read activation signal (S_RE), a slave write activation signal (S_WE), and a master read generated using the clock ratio between different clocks. At least one of the activation signals M_RE may be deactivated.

As the data transmission distance between the slave interface 5 and the master interface 6 increases, it takes a lot of time to compensate. Accordingly, a compensation check period and a compensation method may be determined in consideration of the data transmission distance. For example, if the difference between the predicted pointer and the current pointer is 1, the first policy is to execute the compensation method. The second policy is to execute the compensation method if the difference between the predicted pointer and the current pointer is 2. The third policy is to execute the compensation method when the state in which the difference between the predicted pointer and the current pointer is 1 appears twice in succession, or when the difference between the predicted pointer and the current pointer is 3.

FIG. 5 is a timing diagram showing the clocks of the CPU and the main bus shown in FIG. 3, and a method of generating a gated clock using the clocks of the CPU and the main bus.

3 to 5, the slave sender 16A and the master CDC block 17B are in the same clock domain. In contrast, the master CDC block 17B and the master receiver 17C are in different clock domains.

The slave sender 16A and the master CDC block 17B may operate in synchronization with the CPU clock CCLK. For example, when the slave sender 16A transmits data to the master CDC block 17B, it transmits the data and the CPU clock CCLK to the master CDC block 17B together. In addition, the master sender 17A transmits the bus clock BCLK to the slave CDC block 16B.

However, when the CPU 10 operates in synchronization with the CPU clock CCLK, and the main bus 20 operates in synchronization with the BUS clock BCLK, the master CDC block 17B is a gated clock; It can operate in synchronization with GCLK).

At this time, the CPU clock CCLK is faster than the BUS clock BCLK. For example, when the CPU clock CCLK is toggled 7 times, the BUS clock BCLK may be toggled 5 times.

Since the clocks of the CPU 10 and the main bus 20 are different from each other, the CPU 10 uses a gated clock (GCLK) similar to the clock of the main bus 20 to transfer data to the main bus 20. do.

The gated clock GCLK is generated using the ratio of the CPU clock CCLK and the BUS clock BCLK. The gated clock generation method according to the present invention continuously accumulates a slow clock gear ratio (e.g. 5) to generate a clock once when it is accumulated by a fast clock ratio (e.g. 7). to be. The first start always starts with the slow clock ratio set to the gear thumb.

For example, the gear ratio is 7:5. The gear sum (GS) is a value obtained by dividing the gear sum (GS) by the ratio of the CPU clock (CCLK) (i.e., 7) and adding the ratio (i.e., 5) of the BUS clock (BCLK) to the remainder. The gated clock GCLK may be generated based on a result of dividing the gear thumb GS by the CPU clock CCLK.

The method of making a gated clock (GCLK) is as follows. The first gear thumb is 5, which is the ratio of the BUS clock (BCLK). Divide 5 by 7, which is the ratio of the CPU clock (CCLK). The quotient is 0, and the remainder is 5.

The second gear thumb is generated by adding 5, which is the ratio of the BUS clock (BCLK), to the remaining 5. That is, the second gear thumb is 10. Divide 10 by 7, which is the ratio of the CPU clock (CCLK). The quotient is 1, and the remainder is 3.

The third gear thumb is generated by adding 5, which is the ratio of the BUS clock (BCLK), to the remaining 3. That is, the third gear thumb is 8. Divide 8 by 7, which is the ratio of the CPU clock (CCLK). The quotient is 1, and the remainder is 1.

The fourth gear thumb is generated by adding 5, which is the ratio of the BUS clock (BCLK), to the remainder of 1. That is, the fourth gear thumb is 6. Divide 6 by 7, which is the ratio of the CPU clock (CCLK). The quotient is 0, and the remainder is 6.

The fifth gear thumb is generated by adding 5, which is the ratio of the BUS clock (BCLK), to the remaining 6. That is, the fifth gear thumb is 11. Divide 11 by 7, which is the ratio of the CPU clock (CCLK). The quotient is 1, and the remainder is 4.

The sixth gear thumb is generated by adding 5, which is the ratio of the BUS clock (BCLK), to the remaining 4. That is, the sixth gear thumb is 9. Divide 9 by 7, which is the ratio of the CPU clock (CCLK). The quotient is 1, and the remainder is 2.

The seventh gear thumb is generated by adding 5, which is the ratio of the BUS clock (BCLK), to the remaining 2. That is, the third gear thumb is 7. Divide 7 by 7, which is the ratio of the CPU clock (CCLK). The quotient is 1, and the remainder is 0. When the remainder becomes 0, one cycle of making the gated clock GCLK ends.

When the quotient is 1, the gated clock GCLK may be toggled. In FIG. 5, an embodiment in which the gated clock (GCLK) is used when stored in the FIFO is described, but the present invention is not limited thereto, and a structure in which the clock of a sender that inputs data into the FIFO is used as it is.

6 is a block diagram showing in detail the master FIFO shown in FIG. 4A or the slave FIFO shown in FIG. 4B.

4A, 4B, and 6, the slave FIFO 16B_1 or the master FIFO 17B_1 includes a read pointer RPTR and a write pointer WPTR. The write pointer WPTR indicates a location to store the data transmitted from the CPU 10. The read pointer RPTR indicates a position for reading data stored in the slave FIFO 16B_1 or the master FIFO 17B_1.

When data is input, the write pointer WPTR is increased. That is, the write pointer WPTR points to an address for the next write operation. When data is output, the read pointer RPTR is increased. In other words, the read pointer RPTR indicates an address to perform the next read operation. The slave FIFO (16B_1) or the master FIFO (17B_1) can input data until the full state is reached. In addition, the slave FIFO (16B_1) or the master FIFO (17B_1) can output data until the empty state. For example, the read pointer RPTR and the write pointer WPTR may continue to use the FIFO in a round robin manner.

The slave FIFO 16B_1 or the master FIFO 17B_1 may store data received from the slave sender 16A. For example, if the main bus 20 includes an ARM Advanced eXtensible Interface (AXI), AXI is a write address channel, a write data channel, and a write response channel. ), a read address channel, and a read data channel. Data may be transmitted or received through each of the channels. Bundling and transmitting data of each channel is called a payload. Data stored in the slave FIFO 16B_1 or the master FIFO 17B_1 may include a payload that combines information of all channels into one. For example, the CPU 10 may transmit a payload to the main bus 20, and the CPU 10 may receive the payload from the main bus 20. Likewise, the main bus 20 may transmit a payload to the CPU 10, and the main bus 20 may receive the payload from the CPU 10.

The slave FIFO 16B_1 or the master FIFO 17B_1 may store the first data D1 at address 000. The slave FIFO 16B_1 or the master FIFO 17B_1 may store the second data D2 at address 001. The slave FIFO 16B_1 or the master FIFO 17B_1 may store the third data D3 at address 010. The slave FIFO 16B_1 or the master FIFO 17B_1 may store the fourth data D4 at address 011. The current read pointer (RPTR) indicates address 000. The current write pointer WPTR indicates address 100. The interval between the read pointer RPTR and the write pointer WPTR is 4.

7 is a timing diagram illustrating a write activation signal shown in FIG. 4A or 4B.

4A, 4B, and 7, the first write activation signal WE1 is one of the slave write activation signal S_WE shown in FIG. 4A and the master write activation signal M_WE shown in FIG. 4B. Can include.

When the compensation policy for the write pointer WPTR is executed, the slave write activation signal S_WE shown in FIG. 4A or the master write activation signal M_WE shown in FIG. 4B may be deactivated by one cycle.

For example, the first write activation signal WE1 is in a state before the compensation policy is executed. The second write activation signal WE2 is a result after the compensation policy is executed. That is, from time t1 to time t2, the second write activation signal WE2 is deactivated.

8 is a timing diagram illustrating a read activation signal shown in FIG. 4A or 4B.

4A, 4B, and 8, the first read activation signal RE1 is one of the slave read activation signal S_RE shown in FIG. 4A and the master read activation signal M_RE shown in FIG. 4B. Can include.

When the compensation policy for the read pointer RPTR is executed, the slave read activation signal S_RE shown in FIG. 4A or the master read activation signal M_RE shown in FIG. 4B may be deactivated by one cycle. For example, the first read activation signal RE1 is in a state before the compensation policy is executed. The second read activation signal RE2 is a result after the compensation policy is executed. That is, from time t1 to time t2, the second read activation signal RE2 is deactivated.

9 shows an embodiment of a computer system 210 including a system-on-chip shown in FIG. 1.

Referring to FIG. 9, the computer system 210 includes a memory device 211, an application processor 212, a wireless transceiver 213, an antenna 214, an input device 215, and a display device 216. The application processor 212 may include a memory device and a memory controller that controls the memory device.

The wireless transceiver 213 may transmit or receive a wireless signal through the antenna 214. The wireless transceiver 213 may convert a wireless signal received through the antenna 214 into a signal that can be processed by the application processor 212.

Accordingly, the application processor 212 may process the signal output from the wireless transceiver 213 and transmit the processed signal to the display device 216. In addition, the wireless transceiver 213 may convert a signal output from the application processor 212 into a wireless signal and output the changed wireless signal to an external device through the antenna 214.

The input device 215 is a device capable of inputting a control signal for controlling the operation of the application processor 212 or data to be processed by the application processor 212, and includes a touch pad and a computer mouse. ), such as a pointing device, a keypad, or a keyboard.

In one embodiment, the application processor 212 may include the system-on-chip 1 shown in FIG. 1.

10 shows another embodiment of a computer system 220 including a system-on-chip shown in FIG. 1.

Referring to FIG. 10, the computer system 220 includes a personal computer (PC), a network server, a tablet PC (personal computer), a net-book, and an e-reader (e- reader), a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The computer system 220 includes a memory device 221, an application processor 222, an input device 223, and a display device 224. The application processor 222 may include a memory device and a memory controller that controls the memory device.

The application processor 222 may transmit data stored in the memory device 221 to the display device 224 according to data input through the input device 223. The input device 223 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The application processor 222 may control the overall operation of the computer system 220 and may control the operation of the memory device 221.

In one embodiment, the application processor 222 may include the system-on-chip 1 shown in FIG. 1.

FIG. 11 shows a digital camera device 300 including a system-on-chip shown in FIG. 1.

Referring to FIG. 11, the digital camera device 300 is a digital camera operating with an Android operating system. In one embodiment, the digital camera device 300 may include a Galaxy Camera ^TM or a Galaxy Camera 2 ^TM .

The digital camera device 300 may include an image sensor for capturing an image or video and an application processor (not shown) for controlling the digital camera device 300. In one embodiment, the application processor may include the system-on-chip 1 shown in FIG. 1.

12A and 12B illustrate a wearable device including a system-on-chip shown in FIG. 1.

12A and 12B, the first and second wearable devices 410 to 420 are wearable devices that operate with an Android operating system or a Tizen operating system.

In one embodiment, the first wearable device 410 may include a Galaxy Gear 2. In addition, the second wearable device 420 may include a Galaxy Gear fit.

Each of the first and second wearable devices 410-420 is an application processor for driving an Android operating system or a Tizen operating system, and an image sensor for capturing an image or a video. And a display device for displaying an image or moving picture to be photographed.

In one embodiment, the first and second wearable devices 410 to 420 may include the system-on-chip 1 shown in FIG. 1.

13 shows a wearable device 500 including the system-on-chip shown in FIG. 1.

Referring to FIG. 13, the wearable device 500 may operate as an Android operating system or a Tizen operating system. In one embodiment, the wearable device 500 may include a Galaxy Gearblink ^TM .

The wearable device 500 includes an image sensor 510 for capturing an image or video, a display device 520 for displaying an image, an earphone 530 for listening to a sound, and a wearable device. It may include an application processor (not shown) for controlling 500. In one embodiment, the wearable device 500 may include the system-on-chip 1 shown in FIG. 1.

Although the present invention has been described with reference to an embodiment illustrated in the drawings, this is only exemplary, and those of ordinary skill in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the attached registration claims.

The present invention can be applied to a mobile device or a wearable device including a system-on-chip.

Although described above with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it

1: SYSTEM-ON-CHIP
2: MASTER
3: SLAVE
4: SLAVE INTERFACE
5: MASTER INTERFACE
10: CPU
15: ASYNCHRONOUS INTERFACE1
16: SLAVE INTERFACE1
17: MASTER INTERFACE1
18: CLOCK MANAGEMENT UNIT
20: BUS DEVICE
25: ASYNCHRONOUS INTERFACE2
26: SLAVE INTERFACE2
27: MASTER INTERFACE2
28: MASTER INTERFACE3
29: MASTER INTERFACE4
31: BLOCK1
32: BLOCK2
33: BLOCK3
210: First embodiment of the computer system
220: computer system second embodiment
300: digital camera device
410: Wearable device 1st embodiment
420: Second embodiment of the wearable device
500: third embodiment of the wearable device
510: IMAGE SENSOR
520: DISPLAY DEVICE
530: EAR PHONE

Claims (10)

Master;
Slave; And
It includes a first-in first-out (FIFO) connected to the master and the slave, and controls the write operation of the FIFO by comparing a write pointer of the FIFO with an expected write pointer, and And a system-on-chip including an asynchronous interface for controlling a read operation of the FIFO by comparing a read pointer of the FIFO with an expected read pointer. The method of claim 1,
The FIFO includes a first FIFO and a second FIFO,
The asynchronous interface includes a slave interface and a master interface,
The slave interface includes a slave sender, a slave clock domain crossing (CDC) block including the first FIFO, and a slave receiver, and the master interface includes a master sender, a master CDC block including the second FIFO, and a master receiver. System-on-chip containing. The method of claim 2,
The asynchronous interface generates a write enable signal for controlling a write operation of the FIFO according to a comparison result of the write pointer and the predicted write pointer. The method of claim 3,
The FIFO stores data at an address indicated by the write pointer while the write activation signal is activated. The method of claim 2,
The asynchronous interface generates a read enable signal for controlling a read operation of the FIFO according to a result of comparing the read pointer and the predicted read pointer. The method of claim 5,
The FIFO transmits data stored at an address indicated by the read pointer to the master receiver or the slave receiver while the read activation signal is activated. The method of claim 1,
The asynchronous interface compensates for maintaining a constant interval between the read pointer and the write pointer. The method of claim 7,
The predicted read pointer is calculated based on the write pointer and the interval,
The predicted write pointer is calculated based on the read pointer and the interval. Of a system-on-chip including a master, a slave, and an asynchronous interface including a first-in first-out (FIFO) for connecting the master and the slave In the driving method,
Comparing a write pointer of the FIFO with an expected write pointer; And
And controlling the write operation of the FIFO based on the compared result. The method of claim 9,
The FIFO includes a first FIFO and a second FIFO,
The asynchronous interface includes a slave interface and a master interface,
The slave interface includes a slave sender, a slave clock domain crossing (CDC) block including the first FIFO, and a slave receiver, and the master interface includes a master sender, a master CDC block including the second FIFO, and a master receiver. System-on-chip driving method including.

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