KR102223488B1 - Ddr compatible memory circuit architecture for resistive change element arrays - Google Patents

Abstract

A high speed memory circuit architecture for arrays of resistive change elements is disclosed. The array of resistive change elements is organized into rows and columns, each column being serviced by a word line and each row being serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sensing amplifier. The reference elements are resistive components having electrical resistance values between a resistance corresponding to a set condition in resistive change elements used in the array and a resistance corresponding to a reset condition. The high-speed read operation discharges one of the bit lines of the rows through the resistive change element selected by the word line while simultaneously discharging the other of the bit lines of the rows through the reference elements, and uses the sensing amplifier of the rows to discharge two This is done by comparing the rate of discharge on the lines. Stored status data is transmitted to the output data bus as synchronized high-speed data pulses. High-speed data is received from a synchronized external data bus and stored in resistive change elements within the memory array configuration by programming operations.

Description

DDR COMPATIBLE MEMORY CIRCUIT ARCHITECTURE FOR RESISTIVE CHANGE ELEMENT ARRAYS}

The present disclosure relates generally to resistive change element memory arrays, and more particularly, to such architectures with digital chip interfaces similar to double data rate (DDR) memory interfaces.

Cross-reference to related applications

This application is related to the following U.S. patents, which have been assigned to the assignees of this application and are incorporated herein by reference in their entirety:

US Patent No. 6,835,591, filed April 23, 2002 under the name "Nanotube Films and Articles";

US Patent No. 7,335,395, filed Jan. 13, 2003 under the name "Methods of Using Pre-Formed Nanotubes to Make Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements, and Articles";

US Patent No. 6,706,402, filed March 16, 2004 under the name "Nanotube Films and Articles";

US Patent No. 7,115,901, filed June 9, 2004 under the designation "Non-Volatile Electromechanical Field Effect Devices and Circuits Using Same and Methods of Forming Same"; And

US Patent No. 7,365,632, filed September 20, 2005 under the designation "Resistive Elements Using Carbon Nanotubes".

US Patent No. 7,781,862, filed Nov. 15, 2005 under the designation “Two-Terminal Nanotube Devices and Systems and Methods of Making Same”;

US Patent No. 7,479,654, filed Nov. 15, 2005 under the designation “Memory Arrays Using Nanotube Articles with Reprogrammable Resistance”;

US Patent No. 8,217,490, filed on Aug. 8, 2008 under the name “Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same”;

US Patent No. 8,351,239 filed Oct. 23, 2009 under the name "Dynamic Sense Current Supply Circuit and Associated Method for Reading and Characterizing a Resistive Memory Array"; And

US Patent No. 8,000,127 filed on November 13, 2009 under the name "Method for Resetting a Resistive Change Memory Element".

This application is related to the following U.S. patent applications, which have been assigned to the assignees of this application and are incorporated herein by reference in their entirety:

US Patent Application No. 12/536,803, filed August 6, 2009 under the designation "Nonvolatile Nanotube Programmable Logic Devices and a Nonvolatile Nanotube Field Programmable Gate Array Using Same"; And

US Patent Application No. 12/873,946 filed September 1, 2010 under the designation "A Method for Adjusting a Resistive Change Element Using a Reference".

Technology behind the invention

Any discussion of related technology throughout this specification should not in any way be regarded as an admission that such technology forms part of common common sense in the art or is widely known.

Resistive change devices and arrays, often referred to by those skilled in the art as resistive RAMs, are well known in the semiconductor and electronics industry. Such devices and arrays include, for example, but are not limited to, phase change memory, solid electrolyte memory, metal oxide resistive memory, and carbon nanotube memory such as NRAM™.

Resistive change devices and arrays typically comprise some material that can be adjusted between a plurality of non-volatile resistive states in response to certain stimuli applied within each individual array cell between two or more resistive states. It stores information by adjusting the resistive change element. For example, each resistive state within a resistive change element cell may correspond to a data value that may be programmed and read back by support circuitry within the device or array.

For example, the resistive change element may be arranged to switch between the following two resistive states: a high resistive state (which may correspond to logic "0") and a low resistivity (which may correspond to logic "1"). state. In this way, the resistive change element can be used to store one binary digit (bit) of data.

Or, as another example, the resistive change element may be arranged to switch between four resistive states to store two bits of data. Further, the resistive change element can be arranged to switch between eight resistive states to store four bits of data. Alternatively, the resistive change element may be arranged to switch between ^{2 n} resistive states, in order to store n bits of data.

Within the current state of the art, there is an increasing need to implement resistive change memory arrays in architectures compatible with existing technology. In this way, the benefits of resistive change memory can be realized in circuits and systems using conventional silicon-based microprocessors, microcontrollers, FPGAs, and the like. For example, multiple circuit architectures (e.g., but not limited to, circuit architectures taught by the included references) that provide resistive change memory arrays and architectures compatible with existing non-volatile flash memory architectures. ) Was introduced. Providing faster speed and lower power circuit architectures for resistive change memory arrays to further increase the versatility of resistive change memory technology as the cost and design advantages and popularity of resistive change element memories increase. The need for it is increasing. For this purpose, it would be advantageous to provide a DDR compatible architecture for resistive change element memory arrays.

The present disclosure relates generally to a circuit architecture for arrays of resistive change elements, and more specifically, to those architectures with digital chip interfaces similar to the speed and power requirements of conventional double data rate (DDR) architectures. will be.

In particular, the present disclosure provides a resistive change element memory array. The resistive change element array includes a plurality of word lines, a plurality of bit lines, a plurality of selection lines, and a plurality of memory cells.

The memory cells in the resistive change array each include a resistive change element having a first terminal and a second terminal. The first terminal of the resistive change element is in electrical communication with the selection line, the resistive change element can be switched between at least two non-volatile resistance values, wherein the first resistance value corresponds to a first information state and The second resistance value corresponds to the second information state. Each of the memory cells in the array also includes a selection device. Each of these select devices responds to a control signal on a word line, and each select device selectively provides a conductive path between the bit line and the second terminal of the resistive change element in its memory cell.

The resistive change element array also includes a plurality of reference elements. Each of these reference elements comprises a resistive reference element having a first terminal and a second terminal. The first terminal of each resistive reference element is in electrical communication with the bit line, wherein each resistive reference element is in a resistance corresponding to the first information state of the resistive change elements and a second information state in the resistive change elements. It has an electrical resistance selected to fall between the corresponding resistance values. The resistive change element array may also include a selection device responsive to a control signal on the word line. These select devices selectively provide a conductive path between the bit line and the second terminal of the resistive reference element in its memory cell.

The resistive change element array also includes a plurality of sensing amplifiers. Each of these sensing amplifiers responds to at least one bit line electrically coupled to the resistive change element and to at least one bit line electrically coupled to the resistive reference element. At least one of the plurality of sensing amplifiers may include a rate of discharge on a bit line electrically coupled to a resistive change element selected by a word line and a rate of discharge on a bit line electrically coupled to a resistive reference element selected by a word line. Can be used to compare, and the comparison can be used to read (READ) the information state of the selected memory cell.

The present disclosure also provides a method for reading the information state of a resistive change element. The method includes providing a resistive change element, wherein the resistive change element has a first resistance value corresponding to a first information state and a second resistance value corresponding to a second information state, and at least two non- It can be switched between volatile resistance values. The method further comprises providing a resistive reference element, wherein the resistive reference element is between a resistance corresponding to a first information state of the resistive change elements and a resistance value corresponding to a second information state in the resistive change elements. It has an electrical resistance selected to belong to. The method further includes discharging the voltage through both the resistive change element and the resistive reference element. The method further includes comparing a rate of discharge through the resistive reference element with a rate of discharge through the resistive change element. Within this method, a greater rate of discharge through the resistive change element corresponds to a first information state stored in the resistive change element, and a greater rate of discharge through the resistive reference element is stored within the resistive change element. Corresponds to the second information state.

According to an aspect of the present disclosure, the resistive change element is a two-terminal nanotube switching element including a nanotube fabric.

According to another aspect of the present disclosure, the resistive change element is a metal oxide memory element.

According to another aspect of the present disclosure, the resistive change element is a phase change memory element.

According to another aspect of the present disclosure, a resistive change memory array compatible with a double data rate (DDR) memory architecture is provided.

Other features and advantages of the invention will become apparent from the following description of the invention provided below in connection with the accompanying drawings.

1 illustrates an exemplary layout of a vertically oriented resistive change cell.
2 illustrates an exemplary layout of a horizontally oriented resistive change cell.
3A is a simplified schematic diagram illustrating an exemplary and typical architecture for an array of resistive change elements in an open array architecture.
3B is a table detailing the read and programming voltages required to probe or adjust the CELL00 of the array architecture illustrated in FIG. 3A.
4A is a table listing different sections of a first DDR compatible NRAM architecture (detailed in FIG. 4B) according to the methods of the present disclosure.
4B is a simplified diagram of a first DDR compatible NRAM architecture illustrating a bit line pair (row “x”) of a DDR compatible folded bit line resistive change memory array architecture according to the methods of the present disclosure. Schematic diagram (note that the bit line columns are drawn horizontally to accommodate the bit line pairs, isolation devices, and sensing amplifier circuit details).
5A is a waveform timing diagram illustrating an exemplary read operation performed on a cell in the first DDR compatible NRAM array architecture detailed in FIG. 4B (as the read operations in both architectures are the same, the waveform diagram of FIG. 5A ). It should be noted that may also be applied to the second DDR compatible NRAM array architecture detailed in FIG. 6B).
5B is a waveform timing diagram illustrating an exemplary WRITE operation performed on a cell in the first DDR compatible NRAM array architecture detailed in FIG. 4B.
6A is a table listing different sections of a second DDR compatible NRAM architecture (detailed in FIG. 6B) according to the methods of the present disclosure.
6B is a simplified schematic diagram of a second DDR compatible NRAM architecture illustrating a bit line pair (row “x”) of a DDR compatible folding type bit line resistive change memory array architecture according to the methods of the present disclosure. (It should be noted that the bit line columns are drawn horizontally to accommodate the bit line pairs, isolation devices, voltage shift write circuit, and sensing amplifier circuit details).
7 is a waveform timing diagram illustrating an exemplary write operation performed on a cell in the second DDR compatible NRAM array architecture detailed in FIG. 6B.
8A-8C are a series of annotated schematic diagrams detailing the operation of a voltage shifter element in the second DDR compatible NRAM array architecture detailed in FIG. 6B.
9 is a broken block diagram illustrating an array structure of DDR compatible NRAM architectures of the present disclosure.
10 is a system level block diagram illustrating an exemplary 1Gb x 4 DDR compatible architecture for a resistive change memory array in accordance with the methods of the present disclosure.

The present disclosure relates to advanced circuit architectures for arrays of resistive change elements. More specifically, the present disclosure teaches memory array architectures for resistive change elements with digital chip interfaces similar to a double data rate (DDR) interface. DDR interfaces can be used in DRAMs, SRAMs, NRAM™ and other volatile and nonvolatile types of memories. Memory cells built using resistive change memory elements have a number of advantages over memory cells including conventional silicon-based memory devices, while the timing and power requirements for programming and reading resistive change memory elements are application specific. Can indicate limitations within the fields. The circuit architecture of the present disclosure provides a memory array that can be quickly accessed (read), requires relatively lower power for read and program operations, thereby overcoming these limitations.

Within the circuit architecture of the present disclosure, a plurality of resistive change elements are arranged in an array of rows and columns. Each column of resistive change elements is accessed through a word line, and each row of resistive change elements responds to a select line and a pair of bit lines. It should be noted that in some schematic diagrams the word lines and bit lines are shown in columns (in a vertical "y" orientation) and rows (in a horizontal "x" orientation), respectively, for illustrative convenience purposes. . However, word and bit lines may also be shown with horizontal row “x” and vertical column “y” orientations, respectively. The resistive change elements in each row are common capacitive coupled by a differential sensing amplifier/latch connected to the bit line pairs (described in more detail below with respect to FIGS. 4B and 5B). It is arranged in a folding type bit line arrangement for the purpose of noise rejection). During a read operation, this folding bit line arrangement allows the first bit line to discharge through the resistive change element in the selected cell while simultaneously allowing the second bit line to discharge through the reference element. The sensing amplifier/latch compares the discharge rates of both the bit lines (ie, the bit line of the selected cell and the bit line of the reference element), and temporarily stores the data value of the selected cell. These data values can then be read out of the array through the decoding and buffering elements in the desired clock cycle. While the resistive change elements are non-volatile, so the read operations are typically non-destructive (i.e., the reading or sensing of the information state of the resistive change element does not change or disturb the state stored within that element), whereas the present disclosure The circuit architecture of also provides a way to reset (RESET WRITE operation) resistive change elements in the selected sub-array during a READ out cycle for higher speed and lower power operation. do. This reset operation can be used, as desired, to provide additional flexibility in achieving compatibility with typical DDR read cycles. This reset operation at the end of the read cycle is mainly used in page mode operation in which a page of memory data is read, followed by a page of new data being written to that location. The terms programming and writing (WRITE) are used interchangeably herein.

Resistive change cells store information through the use of resistive change elements within the cell. In response to electrical stimuli, the resistive change element can be adjusted between at least two non-volatile resistive states. Typically, two resistive states are used: a low resistive state (corresponding to the SET state, which is typically a logic '1') and a reset state (representing a RESET state, which is typically logic '0'). ) High resistance state. In this way, the resistance values of the resistive change element in the resistive change element cell can be used to store a bit of information (eg, can function as a 1-bit memory element). According to other aspects of the present disclosure, more than two resistive states may be used, which allows a single cell to store more than 1 bit of information. For example, a resistive change memory cell can adjust its resistive change element between four non-volatile resistive states, which allows storage of two bits of information within a single cell.

Within this disclosure, the term “programming” is used to describe the operation in which the resistive change element is adjusted from the initial resistive state to a new desired resistive state. These programming operations include set operations in which the resistive change element is adjusted from a relatively high resistance state (eg, about 2 MΩ) to a relatively low resistance state (eg, about 100 kΩ). These programming operations also include a reset operation in which the resistive change element is adjusted from a relatively low resistance state (eg, about 100 kΩ) to a relatively high resistance state (eg, about 2 MΩ). Additionally, a "read" operation as defined by the present disclosure is used to describe an operation in which the resistive state of the resistive change element is determined without significantly changing the stored resistive state. Within certain embodiments of the present disclosure, these resistive states (ie, both the initial resistive states and the new desired resistive states) are non-volatile.

Resistive change elements include, but are not limited to, two-terminal nanotube switching elements, phase change memory cells, and metal oxide memory cells. For example, US Pat. Nos. 7,781,862 and US Pat. No. 8,013,363 teach non-volatile two-terminal nanotube switches comprising nanotube fabric layers. As described in these patents, in response to electrical stimuli, the nanotube fabric layer can be adjusted or switched between a plurality of non-volatile resistive states, and these non-volatile resistive states are informed (logical). Can be used to reference states. In this way, resistive change elements (and their arrays) are logically (as resistive states) within electronic devices (such as, but not limited to, cell phones, digital cameras, solid state hard drives, and computers). It is suitable for use as a non-volatile memory device for storing digital data (which stores values). However, the use of resistive memory elements is not limited to memory applications. Rather, arrays of resistive change elements as well as the advanced architectures taught by this disclosure may also be used in logic devices or in analog circuitry.

1 illustrates the layout of an exemplary resistive change cell including a vertically oriented resistive change element (such a structure is sometimes referred to as a 3D cell by those skilled in the art). A typical FET device 130 comprising a drain D, a source S, and a gate structure 130c is formed in the first device layer. The structure and fabrication of such FET device 130 will be well known to those skilled in the art.

A resistive change element 110 is formed in the second device layer. The conductive structure 130a electrically couples with the first end of the resistive change element 110 in the source terminal of the FET device 130. The conductive structure 120 is electrically coupled to a second end of the resistive change element 110 in the array source line SL outside the resistive change cell. The conductive structures 130b and 140 electrically couple the array bit line BL outside the resistive change cell and the drain terminal of the FET device 130. The array word line WL is electrically coupled to the gate structure 130c.

2 illustrates the layout of an exemplary resistive change cell including a horizontally oriented resistive change element (such a structure is sometimes referred to as a 2D cell by those skilled in the art). A typical FET device 230 comprising a drain D, a source S, and a gate structure 230c is formed in the first device layer. As with the FET device 130 shown in FIG. 1, the structure and fabrication of such a FET device 230 will be well known to those skilled in the art.

A resistive change element 210 is formed in the second device layer. The conductive structure 230a electrically couples with the first end of the resistive change element 210 in the source terminal of the FET device 230. The conductive structure 220 is electrically coupled to a second end of the resistive change element 210 in the array source line SL outside the resistive change cell. The conductive structures 230b and 240 electrically couple the array bit line BL outside the memory cell and the drain terminal of the FET device 230. The array word line WL is electrically coupled to the gate structure 230c.

In both the resistive change cells shown in FIGS. 1 and 2, by applying electrical stimuli, typically one or more programming pulses of specific voltages and pulse widths between the bit line BL and the source line SL, The resistive change element is adjusted between different resistive states. A voltage is applied to the gate structure (130c in Fig. 1 and 230c in Fig. 2) through the word line WL, which means that an electrical current is applied to the FET device (130 in Fig. 1 and 230 in Fig. 2) and the resistive change element (Fig. 1). 110 in FIG. 2 and 210 in FIG. 2). Depending on the gate voltage applied by the word line WL, the current to the resistive change element 110 may be limited by design, thereby allowing the FET device to behave as a current limiting device. By controlling the magnitude and duration of this electrical current, the resistive change element (110 in Fig. 1 and 210 in Fig. 2) can be adjusted between a plurality of resistive states.

The state of the resistive change element cells shown in FIGS. 1 and 2 is, for example, but not limited to, applying a DC test voltage of 0.5V between the source line SL and the bit line BL, and at the same time, the FET A voltage sufficient to turn on the device (130 in Fig. 1 and 230 in Fig. 2) is applied to the gate structure (130c in Fig. 1 and 230c in Fig. 2), and the resistive change element (110 in Fig. 1 and 210 in Fig. 2) is applied. ) Can be determined by measuring the current flowing through it. In some applications, this current can be measured using a power supply with a current feedback output, for example a programmable power supply or sensing amplifier. In other applications, this current can be measured by inserting a current measuring device in series with a resistive changing element (110 in Fig. 1 and 210 in Fig. 2).

Alternatively, the state of the resistive change element cells shown in FIGS. 1 and 2 may also be, for example, but not limited to, a FET device (130 in FIG. 1 and 230 in FIG. 2) and a resistive change element (in FIG. 1 ). 110 and 210 in Fig. 2) drive a fixed DC current of 1 μA through the series combination, while at the same time supplying a voltage sufficient to turn on the FET device (130 in Fig. 1 and 230 in Fig. 2). 130c in Fig. 1 and 230c in Fig. 2), and can be determined by measuring the voltage across the resistive change element (110 in Fig. 1 and 210 in Fig. 2).

The resistive change element (such as, but not limited to, those shown in Figs. 1 and 2) may comprise a plurality of materials, such as, but not limited to, a metal oxide, a solid electrolyte, a phase change material, such as a chalcogenide glass. glass), grapheme fabrics, and carbon nanotube fabrics.

For example, U.S. Patent No. 7,781,862, issued to Bertin et al., which is incorporated herein by reference in its entirety, includes first and second conductive terminals and a nanotube fabric article. Disclosed is a terminal nanotube switching device. Bertin teaches methods for adjusting the resistivity of a nanotube fabric article between a plurality of non-volatile resistive states. In at least one embodiment, electrical stimuli are applied to at least one of the first and second conductive elements, for example to pass an electrical current through the nanotube fabric layer. By carefully controlling this electrical stimulation within a specific set of predetermined parameters (as described by Bertin in U.S. Patent Application No. 11/280,786), the resistivity of the nanotube article is It can be repeatedly switched between low resistive states. In certain embodiments, such a high resistive state and a low resistive state may be used to store a bit of information.

As explained by the included references, the nanotube fabrics referenced herein for the present disclosure comprise a plurality of interconnected layers of carbon nanotubes. In the present disclosure, a fabric (or nanofabric) of nanotubes, for example a nonwoven carbon nanotube (CNT), is, for example, a plurality of relatively irregularly arranged relative to each other. It has a structure of entangled nanotubes. Alternatively, or additionally, for example, the fabric of nanotubes of the present disclosure may possess some degree of positional regularity of the nanotubes, for example some degree of parallelism along their long axes. . This positional regularity can be found, for example, on a relatively small scale, in which flat arrays of nanotubes are rafted on a length of about one nanotube and a width of 10 to 20 nanotubes. (raft) are arranged together along their long axes. In other examples, this positional regularity can be found on a large scale with regions of aligned nanotubes extending substantially over the entire fabric layer, in some cases. This large-scale positional regularity is of particular interest in this disclosure. Nanotube fabrics are described in more detail in US Pat. No. 6,706,402, which is incorporated by reference in its entirety.

While some examples of resistive change cells and elements within the present disclosure specifically refer to carbon nanotube based resistive change cells and elements, the methods of the present disclosure are not limited in this regard. Rather, it will be apparent to those skilled in the art that the methods of the present disclosure can be applied to any type of resistive change cell or element (eg, without limitation, phase change and metal oxide).

Referring now to FIG. 3A, an exemplary architecture for a typical resistive change element memory array 300 is illustrated in a schematic diagram. The array 300 includes a plurality of cells CELL00-CELLxy, and each cell includes a resistive change element SW00-SWxy and a selection device Q00-Qxy. Individual array cells CELL00-CELLxy in the resistive change array 300 are source lines SL[0]-SL[x], word lines WL[0]-WL[ y]), and arrays of bit lines BL[0]-BL[x] are selected for read and program operations.

Within the exemplary architecture of FIG. 3A, the selection devices Q00-Qxy used with individual array cells CELL00-CELLxy are conventional silicon based FETs. However, such arrays are not limited in this regard. Rather, other circuit elements (e.g., without limitation, diodes or relays) have similar architectural structures (e.g., select devices such as bipolar devices, And FET devices such as SiGe FETs, FinFETs, and FD SOI).

3B is a table describing exemplary programming and read operations for the resistive change element array shown in FIG. 3A. The table lists the word line, bit line, and source line states required to perform a reset operation, a set operation, and a read operation on CELL00 of the resistive change element array 300. These operations as well as the functionality of the resistive change element array 300 shown in FIG. 3A within these operations will be described in detail below.

The first column of the table in FIG. 3B describes the reset operation of CELL00 (ie, a programming operation that adjusts the resistive state of the resistive change element SW00 from a relatively low resistance to a relatively high resistance). WL[0] is _{driven by V PP} (the logic level voltage required to enable the select device (Q00)), while the remaining word lines (WL[1:y]) are (substantially grounded). ) Drive to 0V. In this way, only selected devices (ie, Q00-Qx0) in the first row of the array are enabled (or "turned on"). BL[0] is _{driven to V RST} (the level of programming voltage required to drive SW00 to a relatively high resistance state), and SL[0] is driven to 0V (substantially grounded). The remaining bit lines BL[1:x] and the remaining source lines SL[1:x] are maintained in high impedance states. In this way V _RST is driven across only cells (CELL00-CELL0y) in the first column of the array. As a result of these conditions, the programming voltage V _RST is only driven across SW00 (via the enabled select device Q00), while the other select devices in the array remain isolated from the programming voltage (and therefore their Retains the original programmed resistive state).

The second column of the table in FIG. 3B describes the set operation of CELL00 (ie, a programming operation that adjusts the resistive state of the resistive change element SW00 from a relatively high resistance to a relatively low resistance). Like the reset operation, WL[0] is _{driven to V PP} (the logic level voltage required to enable the select device Q00), while the remaining word lines (WL[1:y]) are (substantially It is driven to 0V (grounded). In this way, only selected devices (ie, Q00-Qx0) in the first row of the array are enabled (or "turned on"). SL[0] is _{driven to V SET} (the level of programming voltage required to drive SW00 to a relatively low resistance state), and BL[0] is driven to 0V (substantially grounded). The remaining source lines SL[1:x] and the remaining bit lines BL[1:x] are maintained in high impedance states. In this way V _SET is driven across only cells (CELL00-CELL0y) in the first column of the array. As a result of these conditions, the programming voltage V _SET is only driven across SW00 (via the enabled select device Q00), while the other select devices in the array remain isolated from the programming voltage (and therefore their Retains the original programmed resistive state).

Finally, the third column of the table in FIG. 3B describes the read operation of CELL00 (ie, the operation of determining (measurement) the resistive state of the resistive change element SW00). Like the set and reset operations, WL[0] is _{driven to V PP} (the logic level voltage required to enable the select device Q00), while the remaining word lines (WL[1:y]) are , Kept low (at approximately 0V in this example) so that only select devices (ie, Q00-Qx0) in the first row of the array are enabled (or "turned on"). SL[0] is _{driven to V RD} (the programming voltage level required to read the resistive state of SW00), and BL[0] is driven to 0V (substantially grounded). The remaining source lines SL[1:x] and the remaining bit lines BL[1:x] are maintained in high impedance states. In this way, V _RD is driven across only cells (CELL00-CELL0y) in the first column of the array. As a result of these conditions, the read voltage V _RD is only driven across SW00 (via the enabled select device Q00), while the other select devices in the array remain isolated from the read voltage. In this way, the current will flow only through the resistive change element SW00, and the resistive state of SW00 can be determined by measuring the current.

It should be noted that the programming voltages for reset and set operations (V _RST and V _SET , respectively) may be applied with polarities opposite to those described in the preceding paragraphs. However, the methods of the present disclosure are not limited in this regard. Rather, different polarities of reset and set operations can be used to better illustrate the functionality of the array shown in FIG. 3A. In other words, the programming (set and reset) voltages and read voltages are either polarity (i.e., positive on the source line), depending on the specific programming operation being discussed or the specific type of resistive change element required. Voltage or a positive voltage on the bit line). As will be shown in more detail in the following paragraphs, this is also the case for the memory array architectures of the present disclosure. In addition, the programming and read voltages (such as set and reset) can also all be of the same polarity.

As shown through the discussion of FIG. 3B regarding the array architecture of FIG. 3A, resistive change elements are suitable for use within memory arrays. However, within certain applications, arrays of resistive change elements may exhibit certain timing and power requirements, and-in certain applications-these requirements may lead to the use of such arrays within certain memory interfaces and architectures. Limit. For example, within the memory architecture detailed in Fig. 3A, the electrical capacitance of a select line or bit line-within certain applications-depends on how quickly the resistance of an individual cell can be sensed during a read operation. May indicate a timing limit for. In such applications, the relatively large capacitance of the line itself and the resistance of the nonvolatile storage element will introduce a relatively large RC time constant on the line being discussed, and will require a certain amount of time to charge or discharge the line. . Within certain applications, resistive change elements arranged in a memory array structure are suitable between reset and set states within the respective selected resistive change elements during a read operation by circuit elements located at the ends of relatively long bit lines or select lines. It may require relatively high read voltages and/or currents to differentiate below. These types of timing and power requirements -which may limit the use of resistive change memory arrays within certain applications-are overcome by the resistive change element memory array architecture of the present disclosure.

1st DDR Compatible Resistive Change Element Array Architecture

Referring now to FIGS. 4A and 4B, a first DDR compatible memory circuit architecture for an array of resistive change elements according to the present disclosure is disclosed. For ease of explanation, an exemplary schematic diagram 402 showing a single row (row “x”) is divided into a plurality of functional sections 410, 412, 420, 430, and 440. Table 401 of FIG. 4A describes each of these functional sections, and their use within both read and write operations on the array.

4A and 4B, the first section 410 in this first DDR compatible architecture of the present disclosure is the memory array itself. These are individual array cells (CELLx0-CELLx3 in FIG. 4B) themselves, each of which includes a resistive change element (SWx0-SWx3 in FIG. 4B) and a selection element (FETs (Tx0-Tx3) in FIG. 4B). Individual cells in the memory array 410 are an array of word lines (WL[0]-WL[3] in FIG. 4B), and bit lines for each row of the array (BL[x]_D/ It is accessible in response to the pair of R and BL[x]_R/D), and a select line for each row of the array (SL[x] in FIG. 4B). The use of these array lines in both read and write operations will be described in more detail below.

The next section 412 in the first DDR compatible architecture of the present disclosure includes reference resistors. Each row in the array of the first DDR compatible architecture contains a pair of reference elements accessible by dedicated word lines (WL_ODD and WL_EVEN shown in FIG. 4B). As listed in table 401 of FIG. 4A, reference resistors are used during read operations and are inactive during write operations. The use of pairs of bit lines for each row (BL[x]_D/R and BL[x]_R/D, as shown in Fig. 4) allows the read voltages and discharge currents to be applied to the reference resistor R _{REF -ODD} or R _REF-EVEN ) and allow simultaneous application to the selected memory cell. By comparing the discharge rates through the reference element and the selected cell, the resistive state of the selected cell can be determined. The use of these reference resistors within these read operations will be described in more detail below with the discussion of FIG. 5A.

The next section 420 within the first DDR compatible architecture of the present disclosure provides equilibration and isolation devices. These devices isolate the array cells from the sensing amplifier/latch (section 430) and the bi-directional data bus control circuit (section 440) during different stages of a read or write operation. In response to two different isolation control signals (N_ISOLATE1 and N_ISOLATE2, as shown in FIG. 4B), the isolation devices in section 420 have the required signal inversion function with a folding bit line architecture. It also provides. The use of these balancing and isolation devices during read and write operations within the first DDR compatible architecture of the present disclosure will be described in more detail below within the discussion of FIGS. 5A and 5B.

The next section 430 in the first DDR compatible architecture of this disclosure is the sensing amplifier/latch. During a read operation (responsive to control signals PSET and NSET as shown in FIG. 4B), this sensing amplifier/latch is a pair of bit lines between one of the reference elements (section 412) and the selected array cell. Voltage discharges are compared, and a logic value corresponding to a logic value stored in the selected array cell is latched. During a write (or programming) operation, these sensing amplifiers/latches are used to temporarily hold data values to be stored in the selected array line cells prior to application of the programming current. The use of this sensing amplifier/latch 430 during read and write operations within the first DDR compatible architecture of the present disclosure will be described in more detail below within the discussion of FIGS. 5A and 5B.

The bi-directional data bus control circuit 440 in the first DDR compatible architecture of the present disclosure is a bi-directional data bus control circuit. _{The pair of FETs (T BIDI1} and T _BIDI2 , as shown in FIG. 4B) in response to the control signal (CSL, as shown in FIG. 4B), the sensing amplifier/latch and the data I/O in section 430 Enables or disables an on-chip bidirectional data bus electrical connection between the buffer/driver 1067 circuit. In this way, by the data I/O buffer/driver 1067 circuit, the data stored in the sensing amplifier/latch during the read operation can be provided to an off-chip external data bus, and within the selected array cell. Data to be stored can be provided from an external data bus to the sensing amplifier/latch. The use of this bi-directional data bus control circuit 440 during read and write operations within the first DDR compatible architecture of the present disclosure will be described in more detail below within the discussion of FIGS. 5A and 5B. The data I/O buffer/driver 1067 (FIG. 10) circuit is further described in connection with FIG. 10 below.

As described above, the simplified schematic diagram of FIG. 4B illustrates a single row (row “x”) of a resistive change memory array according to the methods of the present disclosure. The simplified schematic diagram of FIG. 4B is a folding type bit line architecture, and the data storage memory cells therein include WL[0], WL[1], WL[2], WL[3], and bit line pairs BL[x ]_D/R and BL[x]_R/D) in a staggered pattern, as illustrated at the intersection of the two word lines and bit line intersections. Each even data storage memory cell (CELLx0, CELLx2, etc.) is connected to BL[x]_D/R and even word lines (WL[0], WL[2], etc.); Each odd data storage memory cell (CELLx1, CELLx3, etc.) is connected to BL[x]_R/D and odd word lines (WL[1], WL[3], etc.); All data storage cells, both even and odd cells are connected to the selection line SL[x]. The array selection line SL[x] is approximately parallel to the array bit line pair BL[x]. In this example, all of the array select lines are approximately parallel to the array bit lines. However, resistive memory arrays may also be formed with array select lines that are approximately parallel to the array word lines, that is, approximately orthogonal to the array bit lines. One pair of reference resistors per bit line pair selectable by WL_EVEN and WL_ODD is included for use during read (sensing) operations, so that when WL_EVEN is activated, the reference resistor R _{REF_E} becomes the bit line BL[x ]_R/D), and whenever WL_ODD is activated, the reference resistor R _{REF_O is} connected to BL[x]_D/R. Whenever an even word line is selected, WL_EVEN is activated, and whenever an odd word line is selected, WL_ODD is activated. Each bit line in the bit line pair may be a data line D or a reference line R so that only one of the bit line pairs can have an active bit along the bit line. This folding type bit line array results in common mode word to bit line capacitive voltage coupling cancellation by the differential sensing amplifier/latch. This common noise cancellation technique enables lower read voltages and less array power. However, folding bit line structures have about half the density of open bit line architectures, such as the exemplary array of resistive change architecture of FIG. 3A. The CNT switching operation is further described above in connection with FIG. 3B. For ease of layout in Fig. 4B, it should be noted that, because of the level of detail along the bit line direction, word lines are drawn on the vertical y-axis and bit lines are drawn on the horizontal x-axis. 3A and block diagram Within the simplified memory array 300 of memory 1000, word lines are drawn in a more conventional horizontal "x" (low) direction, and bit lines are drawn in a more conventional vertical "y". It is drawn in the (column) direction.

Referring back to FIG. 4B, the memory array portion 410 of the memory array row schematic diagram 402 is represented by four resistive change element memory cells CELLx0, CELLx1, CELLx2, and CELLx3. As indicated by the dotted lines along the bit lines BL[x]_D/R and BL[x]_R/D, the memory array section 410 of the array row in the architecture of the present disclosure accommodates more memory cells. Can include. However, for simplicity of illustration, only the first four memory cells CELLx0, CELLx1, CELLx2, and CELLx3 are shown in the simplified schematic diagram of FIG. 4B. However, the exemplary and horizontally laid out bit lines (bit line pair “x”) shown in the simplified schematic diagram 402 of FIG. 4B are as many as required for a particular memory array (or sub-array). It should be noted that it may contain memory cells.

Each individual memory cell (CELLx0, CELLx1, CELLx2, and CELLx3) contains resistive change elements (SWx0, SWx1, SWx2, and SWx3, respectively) and a selection device (Tx0, Tx1, Tx2, and Tx3, respectively). do. When enabled by the associated word line (WL[0], WL[1], WL[2], and WL[3], respectively), the select device in each resistive change memory cell is associated with its associated resistive change memory. An electrically conductive path is provided between one terminal of the element and one of the bit lines BL[x]_D/R or BL[x]_R/D. In response to electrical stimuli provided across the associated bit line and the common selection line SL[x], an individually selected resistive change element is set (as described in detail above in connection with FIGS. 1 and 2). Or it can be programmed into a reset state or can be quickly read using the methods of the present disclosure (as described in more detail below).

According to the methods of the present disclosure, the folding type bit line architecture shown in FIG. 4B has two bit lines BL[x]_D/R and BL[ for each pair of horizontally laid out bit lines in a memory array. x]_R/D) is provided. Depending on the physical location of the memory cell being accessed, each of these two bit lines serves as an active bit line for the selected memory cell and to provide access to one of the two reference cells within the memory array row. Alternate between what is used. Within the exemplary schematic diagram of FIG. 4B, BL[x]_D/R serves as an activation bit line for “even” memory cells CELLx0 and CELLx2, and reference bits for “odd” memory cells CELLx1 and CELLx3. Serves as a line, with BL[x]_R/D serving as an inversion capacity (activation for "odd" cells and criterion for "even" cells).

As explained above, the two reference cells (section 412) provided within the horizontally laid out bit line pair architecture schematic diagram of FIG. 4B allow a quick readout of the state of an individually selected resistive change memory cell. T _REF-ODD and R _REF-ODD contain a reference cell used to read “odd” located memory cells (CELLx1 and CELLx3) _{in an array row, where T REF-EVEN} and R _REF-EVEN are in the array row. It contains a reference cell used to read the "even" located memory cells CELLx0 and CELLx2. T _REF-ODD and T _REF-EVEN are select devices (similar to select devices Tx0-Tx3) and respond to two dedicated word lines (WL_ODD and WL_EVEN, respectively). R _REF-ODD and R _REF-EVEN are reference elements (eg, without limitation, fixed resistors or other resistive change elements programmed to a stable reference state). The electrical resistance of these reference elements is fixed at a value between the threshold “low” resistance value (set resistance) and the threshold “high” resistance value (nominal reset resistance) for the type of resistive change element technology used. The use of these reference elements during read operations will be discussed in detail in the discussion of FIG. 5A below.

_{Although the selection devices (e.g., Tx0-Tx3, T REF-ODD} , and T _REF-EVEN ) shown in the exemplary schematic diagram of FIG. 4B are shown as being field effect transistors (FETs), the present disclosure It should be noted that the methods of are not limited in this regard. Indeed, other types of circuit elements that can regulate or otherwise modify the conductive path between two nodes in an electrical circuit can be used as the selection device in the methods of the present disclosure. These select devices may include, but are not limited to, diodes, relays, and other resistive change memory elements. For example, bipolar transistors can be used. Similarly, FinFET devices can also be used as select devices. However, selection devices that do not require a semiconductor substrate can also be used. For example, fully-depleted silicon-on-insulator (FD-SOI) devices and carbon nanotube FET (CNTFET) devices can also be used, and CNT When combined with resistive storage devices, it enables chips to be fabricated as a whole on an insulator material. This makes it possible to stack memory layers on each other to achieve greater densities. FD-SOI and CNTFET devices also have the added advantage of substantially lower soft error rates (SERs).

Section 430 of the array row schematic diagram shown in FIG. 4B is through the isolation element (transfer device) represented by section 420 of the array row schematic diagram 402, the two bit lines BL[x] of the array row. ]_D/R and BL[x]_R/D). During a read operation, _{either N_ISOLATE1 (enables the FETs (T IOS1} and T _IOS2 )) or N_ISOLATE2 (enables the FETs (T _IOS3 and T _IOS4 )), (one bit line changes the selected resistivity). A sensing amplifier/latch 430 (including _{FETs T SA1} -T _SA6 ) of the two bit lines of the array row discharging through the element, the other bit line discharging through one of the two reference elements. ) Is activated to electrically couple. Two separate isolation controls (N_ISOLATE1 and N_ISOLATE2) are needed to prevent data inversion when "odd" cells are read. Activating N_ISOLATE1 electrically couples BL[x]_D/R to the positive terminal of the sensing amplifier/latch 430 (as required when CELLx0 or CELLx2 is read). And, activating N_ISOLATE2 electrically couples BL[x]_R/D to the positive terminal of the sensing amplifier/latch 430 (as required when CELLx1 or CELLx3 is read).

As will be described in more detail with respect to the read operation timing diagram of FIG. 5A, during the discharging of the two bit lines, the PSET and NSET controls are activated, which means that the sensing amplifier/latch 430 is selected for the programming of the resistive change element. Allows to temporarily store the data value represented by the resistive state. The isolation element 420 can then isolate the memory array portion of the array row from the sensing amplifier 430 (by disabling both N_ISOLATE1 and N_ISOLATE2), and the information state of the selected memory cell is positive in response to the CSL control. Can be read out at any time through the -direction data bus control circuit 440.

It is noted that the EQ control in the isolation stage 420 of the array row schematic of FIG. 4B can be activated immediately prior to the read operation to balance the bit line pair voltages, and then de-activated prior to the word line activation during the read operation. Be careful. The EQ control and its associated circuit element T _EQ are only used for bit line pair balancing during read operations. The EQ control is not active during the write operation. The read operation is further described below in connection with FIGS. 4B and 5A.

During a write operation using the first DDR compatible architecture, data pulses (indicating the data values to be written) are transferred eight bits at a time to the digital interface to the sensing amplifier as described in further detail below with respect to FIG. They enter the array through an on-chip data input/output buffer/driver connected to the data bus that transmits them. These input/output buffers place 8 bits on the data bus during every positive array clock transition, and then this data is passed through a two-way data bus control circuit (440 in Fig. 4b) through a sensing amplifier/latch (in Fig.4b). 430). Isolation devices (420 in Fig. 4b) are activated, and then the data in the sensing amplifier/latch is passed through these isolation devices through the array bit lines (BL[x]_D/R and BL[x]_R/D in Fig. 4b). ). The array cell (or cells) to be written is enabled via its associated word line, and the programming current is selected from its associated bit line to the select line (SL[x] in Fig. 4B) to perform the write function. It is allowed to flow through the element (or elements). As discussed above, the voltage driven onto the bit lines from the sensing amplifier/latch 430 (driven by the input/output buffer) is passed through the resistive change element to adjust the resistive state of the resistive change element. It is chosen to provide sufficient programming current.

Within certain applications such as page mode operation, for example, to enable compatibility with DDR memory functionality, all bits in the array are rendered to a reset state during read operations in the example further described below. )do. However, other methods can be used. For example, all bits in the array can be rendered in a set state. Alternatively, the bits may be in either a set or reset state. In this example, since all bits are in the reset state at the start of the write operation, it can be assumed that all the storage elements in the array are in a high resistance (reset) state corresponding to a logic '0'. As such, a write operation within these specific applications will only have to provide these array cells with the programming set currents required to be reprogrammed to the set state, which is a low resistance state corresponding to a logic '1'. Write operations using the first DDR compatible architecture of the present disclosure will be described in more detail below with respect to FIG. 5B.

Referring now to FIG. 5A, a timing diagram first detailing an exemplary read operation on a single array cell in a DDR compatible resistive change element array using the first architecture of the present disclosure (as shown and described above in 4B). 501) is shown. Within the exemplary timing diagram 501 of FIG. 5A, it is assumed that the resistive change element in the array cell being read is programmed to a low resistance set state (corresponding to logic "1").

Referring to the read timing diagram 501, a clock signal (CLK) 505 is used to synchronize the DDR NRAM timing digital interface with the timing of a microprocessor or other digital external control circuit element that interfaces with the memory array architecture of the present disclosure. Is used. In DDR operation, the data rate on the external bus (I/O) is twice (2-times) the data rate on the internal (on-chip) data bus. That is, the data on the internal data bus changes with each positive (up) transition of the clock signal 505, while the data on the external I/O data bus changes with the positive (up) and Changes with negative (down) transitions, as a result of which both the internal data bus and the external data bus remain synchronized with the clock signal 505. In this example, referring to the timing diagram 501 illustrated in FIG. 5A, the synchronized data transitions on both the internal data bus and the external data bus are a second, which is 180 degrees out of phase with respect to the clock signal 505. This is achieved by generating a clock signal 505'. In this way, for example, 8 data bits can be read into the 8-bit internal data bus with each positive (up) transition of the clock signal 505, and these data bit signals can be read into the data I/O buffer. /Sent to the driver 1067. The data I/O buffer/driver 1067 uses a combination of the clock signal 505 and the second clock signal 505' to receive eight data signals at twice (2-times) the internal data bus data rate. Two sets of four data bit signals are multiplexed onto a 4-bit external data bus. That is, data on the external data bus is switched with each positive (up) transition of the clock signal 505 and each positive (up) transition of the second clock signal 505'. An internal data bus, a data I/O buffer/driver 1067, and an external data bus are illustrated in FIG. 10.

Generating an on-chip out-of-phase clock signal is one way to achieve synchronized data rates at twice the data rate on the external data bus with respect to the internal data bus. Other methods can also be used. While this example describes doubling the external data rate with respect to the internal data rate, similar methods can be used for 3 times the data rate (DDR3 NRAM), 4 times the data rate (DDR4 NRAM), and higher synchronized data rates. Can be used to achieve them.

Referring to the read timing diagram 501, the signal development and sensing 510 waveforms on the selected bit line pair correspond to the stored data values in the selected cell in the memory array (sub-array) 410 illustrated in FIG. 4B. Corresponds. Referring to the signal evolution and sensing waveforms 510, the selected bit line pair (BL[x]_D/R and BL[x]_R/D]) activates the EQ to pre-charge the read cycle. charge) phase equilibrates to the same voltage, approximately V _DD /2 in this example, which is then activated when activating the selected word line and the corresponding reference word line in the memory array (or sub-array) illustrated in Fig. 4b. It is turned off. Although in this example V _DD /2 was chosen as the equilibration voltage, it should be noted that other values such as V _DD , any voltage between _{V DD} /2 and V _{DD , and voltages less than V DD} /2 may also be used. do. Next, the selected word line, in this example WL[0] is _{switched to V DD} +V _TH and turns on the selection device (Tx0) in CELLx0, which turns the resistive change element (SWx0) to the bit line (BL[x]). _D/R) and thereby initiate signal evolution. In this example, it is assumed that CELLx0 is set to a low resistance set state representing a "1" logic state. WL_EVEN is also activated almost simultaneously with WL[0], and also _{switches to V DD} +V _{TH and the reference device (T REF_E} ) connecting the reference resistor (R _{REF_E} ) to the bit line (BL[x]_R/D). Turn on. Both of the pre-charged bit lines have the same bit line capacitance, and both discharge through the resistive elements. However, each BL in the bit line pair is connected to a different resistive element resulting in different RC time constants, and thus different rates of discharge and corresponding voltage reduction rates. The amount of time referred to as signal develop in signal development and sensing waveforms 510 is allowed, and the duration depends on the sensitivity of the sensing amplifier. For example, if the differential sensing amplifier/latch 430 (FIG. 4B) switches to a difference voltage of 50 mV, the signal evolution time is selected to allow a differential signal of 50 mV to be formed. However, if the differential sensing amplifier/latch 430 is much more sensitive, for example switching with a difference voltage of 5 mV, a shorter signal evolution time is used. When a sufficient signal development time is reached, the sensing amplifier/latch 430 is turned on, and after a sufficient set time, the difference voltage between the bit lines B[x]_D/R and B[x]_R/D is Latches the signal based on it. The combined voltage between the word line WL[0] and the reference word line WL_EVEN for the bit lines B[x]_D/R and B[x]_R/D is equal to the differential sensing amplifier/latch 430 Is rejected as common mode noise by

Near the end of the signal evolution of this exemplary read cycle, the sensing amplifier/latch 430 is activated as follows. The PSET is driven to a low voltage, _{turns on the FET T SA5} , thereby connecting the terminals FETs T _SA1 and T _SA2 to the power supply V _SA (in this example, for the read operation , V _SA = V _DD ). NSET is driven with a high voltage, e.g. V _DD , turns on FET T _SA6 , thereby connecting terminals FETs T _SA3 and T _SA4 to ground. At the same time, power is supplied to the sensing amplifier/latch 430, and the sensing amplifier/latch senses/latches the data signal from cellx0. Immediately after activation of the sensing amplifier/latch (with N_ISOLATE2 disabled) N_ISOLATE1 may be enabled, whereas, typically, N_ISOLATE1, for example, at the beginning of the read cycle, will cause the sensing amplifier/latch 430 ) Is enabled faster in the read cycle prior to activation. In this way, the sensing amplifier/latch (section 430 in Fig. 4b) is coupled to the memory array through the non-inverting path of the isolation element (section 420 in Fig. 4b), latching the data value of the selected cell and Be prepared to keep it temporarily.

The selection line SL[x] common to all cells in the array row is kept low. And, the CSL is kept low, which disables the bi-directional data bus control circuit 440 (FIG. 4A) until the array data is latched by the sensing amplifier/latch 430.

Memory arrays, such as memory array 410, are formed using a plurality of sub-arrays within which a memory sub-array line may contain thousands of individual memory cells. The length of these array lines causes a relatively large line capacitance on these bit lines, which can lead to relatively large time constants when combined with the resistance of non-volatile resistive change elements, due to the RC time constants. Thus, the rate at which these bit lines can be charged and discharged can be limited. By using folding bit line pairs such as (BL[x]_D/R and BL[x]_R/D) and differentially sensing the bit line pair signals at small differential signal values, the sensing time will be greatly reduced. May, for example, result in faster data rates and faster read times, such as page mode data rates. This means that the methods of the present disclosure using folding bit line array pairs and differential sensing allow each bit line in the bit line pair to be completely, or even almost completely, to determine the resistance value stored in the selected resistive change element (SWx0). This is because it does not require discharge, thereby reducing the timing delays associated with relatively high capacitance long bit lines. Faster sensing at lower voltages for the folding array architecture illustrated in FIG. 4B may also result in lower operating power as well. In applications with very large memory array sizes (eg, but not limited to 1 Gb or more), low power read operations can be a very important design consideration.

As illustrated by signal evolution and sensing waveforms 510, within the exemplary read operation detailed in FIG. 5A, BL[x]_D/R discharged faster than BL[x]_R/D, which It indicates that the electrical resistance of SWx0 in CELLx0 is at a much lower resistance value (set state) than that of _{R REF-EVEN.} And, since _{the resistance value of R REF-EVEN} was chosen as a value between a nominal "high" resistance value and a nominal "low" resistance value (as determined by the technology and design of the resistive change elements used in the memory array). Therefore, this difference in discharge indicates that a low resistance value (or logic "1") is stored in CELLx0 as further described above, and the sensing amplifier/latching 430 latches the logic "1" state Keep it. However, when the electrical resistance of the SWx0 in CELLx0 the high state (reset state) indicating a logical "0", because it will SWx0 has a higher resistance than that of the reference resistor (R _REF-EVEN) more slowly discharge accordingly, BL [x]_D/R will discharge slower than BL[x]_R/D, and sensing amplifier/latch 430 latches and holds logic "0". The logic value held in the sensing amplifier/latch 430 is transferred to the on-chip data bus by the bi-directional data bus control circuit 440 (Fig. 4B) when the CSL is activated by controlling the circuit outside the memory array. Can be read.

In the final stage of the read operation shown in FIG. 5A (“Output and Reset” stage), N_ISOLATE1 is driven low, which transfers the sensing amplifier/latch 430 (FIG. 4B) from the memory array 410 (FIG. 4B). Isolate. The bi-directional data bus control circuit 440 is activated by the CSL, and the logic value stored in the sensing amplifier/latch 430 (Fig. 4B) corresponding to the data stored in the selected array cell is its inverted value (complementary value). ) Are simultaneously driven onto the inverted data output line nD, and are connected to the input of the data output line D and the data I/O buffer/driver 1067 on the on-chip 8-bit data bus. Then, the data I/O buffer 1067 (FIG. 10) latches the data, and drives the external 4-bit data bus at a data rate twice the internal data bus, as described further above. In this example, data first appears on two clock cycles of the external data bus after the column address is received from the controlling device. While the DDR NRAM can be operated in random access mode, typically a page of data is read as illustrated in FIG. 5A (page mode). When data transfer is complete, the CSL disables the connection between the sensing amplifier 430 and the bi-directional data bus control circuit 440.

While resistive change elements are non-volatile (i.e., they retain their programmed information state during read operations or when power is removed from the device), while certain types of memory architectures (e.g., without limitation, DRAM capacity Sex storage memories) cause destructive read operations. That is, in a typical DRAM DDR memory array, for example, a read operation on a cell will destroy the data stored in the cell itself. Then, this data will have to be written back to the selected cell in the array from the corresponding sensing amplifier/latch in a write-back operation. Thus, the amplifier/latch will remain connected to the corresponding pair of bit lines during the completion of the read operation cycle to restore the cell's original state. However, a resistive change memory such as NRAM, for example, because it performs a non-destructive read operation, the data remains in the array cell and writes data from the sensing amplifier/latch 430, which can be isolated from the array. There are no back requirements. Thus, in this NRAM example, N_ISOL1 is deactivated, and the transmission devices T _IOS1 and T _IOS2 connect the sensing amplifier/latch 430 to the memory array 410 bit lines BL[x]_D/R and BL. [x]_R/D), and further, WL_EVEN isolates the reference resistor R _{REF_E} from the bit line BL[x]_R/D, as shown by the signal evolution and sensing waveforms 510. As such, both of the bit lines are driven to a zero (ground) voltage because the data is latched into the sensing amplifier/latch 430 for transmission to the on-chip data bus. In this example, since no data write-back is required, the programming operation can be performed at the end of the read cycle. The selected word line (WL[0]) remains active, whereby SL[x] switches to the reset voltage, the bit lines are grounded, and SL[x] when the cell was in a low resistance set state. ] Enables the reset operation when driving the selected bit to the high resistance reset state. If the cell was in a high resistance reset state, it remains unchanged in the reset state. This means that while data from the sensing amplifier/latch 430 is transferred via the on-chip data bus to the data I/O buffer/driver 1067 and onto the off-chip output bus, resistive memories such as NRAMs Make it possible to complete the reset cycle. Leveraging the non-volatility of the resistive memory bits by resetting the selected bits to a high resistance state during the completion of the read cycle simplifies the write operation as discussed further below. To illustrate this functionality within the memory array architecture of the present disclosure, an exemplary read operation detailed by timing diagram 501 of FIG. 5A is described (i.e., while CSL is active and read data is provided to an external data bus). A reset operation that occurs simultaneously with the data read operation is shown.

In particular, within this reset operation, SL[x] is driven high to the required reset voltage (as detailed above in connection with set and reset operations on resistive change elements), while the bits of the rows Both lines BL[x]_D/R and BL[x]_R/D] are pulled low. WL_EVEN is also driven low, which prevents any programming current _{from passing through the reference element R REF-EVEN} , and WL[0] remains driven high, which enables access to CELLx0. In this way, the programming current is driven through CELLx0, and SWx0 is driven to the reset state. The remaining word lines WL[1]-WL[3] remain low, and thus the data in the remaining memory cells (CELLx1, CELLx2, and CELLx3 in Fig. 4B) remain unchanged. As discussed above, this reset operation for a read memory cell is not required within the methods of the present disclosure, but it is included to illustrate the benefits and functionality of the DDR NRAM architecture presented in FIGS. 4B and 5A. Be careful.

Referring now to FIG. 5B, a timing diagram 550 for a write (programming) operation for a first DDR compatible memory circuit architecture is shown. The timing diagram 550 details an exemplary write (programming) operation for a single array cell within the DDR compatible resistive change elements in the array of the present disclosure discussed above and shown in FIG. 4B. Within the exemplary timing diagram 550 of FIG. 5B, the resistive change element in the array cell is adjusted from a high resistance reset state (corresponding to logic "0") to a low resistance set state (corresponding to logic "1"). Is assumed to be.

As discussed above with respect to FIG. 5A, a read operation for a selected array cell using the first DDR compatible array architecture of the present disclosure may be read and reset within the same cycle. This read and reset method ensures that at the end of the read cycle the selected array cell is in a reset state (ie, a relatively high resistance state corresponding to a logic '0'). Then, a write operation to this cell would only have to apply the programming set current required to enter the set state (ie, a relatively low resistance state corresponding to logic '1') onto the array cell. In this way, this first architecture (as detailed in Fig. 4b) can be used with a traditional DDR interface. Additionally, within certain applications, this read/reset/write process can provide improved speed and lower power operation of the resistive change element array. For this purpose, the exemplary write operation detailed in FIG. 5B performs a set operation for a selected cell (CELLx0 as shown in FIG. 4B) in the resistive change element array using the first DDR compatible array architecture of the present disclosure. to provide.

Within the read operation detailed in FIG. 5A, the sensing amplifier/latch 430 shown in FIG. 4A may be operated at relatively low voltages (eg, about 1V). As such, the voltage levels used on the bit lines BL[x]_D/R and BL[x]_R/D and within the sensing amplifier/latch 430 are, for certain applications, to the external control circuit. It may be a system level voltage ("V _DD ") used by. In this way, the data pulses transmitted to the external data bus through the bi-directional data bus control circuit (440 in Fig. 4B) are also at V _DD when they are transmitted from the array. However, for certain applications, a write (or programming) operation within the first DDR compliant NRAM architecture of the present disclosure (again, as illustrated in Figure 4B) is to induce sufficient programming current through the selected array cell. It may require significantly higher voltages to do so. _{For example, a write operation may require that a voltage level (V DD} x2) twice the system level voltage is driven on the bit line associated with the selected array cell, which means that this higher voltage, at least temporarily, It also requires being driven onto the on-chip data bus lines (D and nD in Fig. 4B) as well. To illustrate this, it is assumed that the programming voltage required in the exemplary write operation detailed in FIG. 5B is V _{DD x2.}

Referring to the resistive change memory 1000 illustrated in FIG. 10 and the first DDR compatible resistive change element array architecture schematic diagram 402 illustrated in FIG. 4B to be further described below, a DDR programming (write) operation is illustrated in FIG. 5B. Will be described in connection with the resulting timing diagram 550. Referring to table 401 of FIG. 4A, reference resistors 412 in schematic diagram 402 are in an inactive state during a write operation. As described above with respect to FIG. 4B, the memory array 410 uses a folding-type bit line architecture, and the bit line pair BL[x] includes all word lines in the memory array or memory sub-array. Represents any pair of folding bit lines that intersect. During the write operation, only one word line is selected (activated) at a time, which corresponds to the row address in the row address buffer (FIG. 10). As further described above with respect to FIG. 4B, within the folding type bit line architecture, cells contain data that BL[x]_D/R is input to the array 410 when the even word line is activated. , When the odd word line is activated, it is staggered so that BL[x]_R/D contains the data. In this writing example, the even word line WL[0] is selected. Accordingly, CELLx0 illustrated in the memory array 410 is selected, and the write operation stores data in the nonvolatile storage element SWx0. The selection line SL[x] is maintained at a low voltage (eg, ground) during a write operation with respect to one of the even or odd word lines. The column address buffer (FIG. 10) contains column address locations for write operations. The timing diagram 550 for a first DDR compatible resistive change element array architecture illustrates a fast page mode write operation for a pre-selected word line that is WL[0] in this example. An on-chip clock (CLK) signal synchronizes the digital interfaces of the memory to an external controller or processor. Input data from the external (off-chip) 4-bit data bus arrives at the digital interface of the resistive change memory (Figure 10) with each positive and negative transition of the clock, and 8 bits Two groups are latched onto the data I/O buffer/driver 1067 (FIG. 10). Then, at each positive transition of the clock, 8 bits are transferred to the 8-bit on-chip data bus, the bi-directional data bus control circuit 440 (Fig. 4B) is activated and 8 bits are converted to 8 bits. To the sensing amplifiers, which are written into the memory array 410 (FIG. 4B). If there are 2048 bits along the word line, e.g., the word line WL[0] in this example, the write operation of all the bits to be written along the word line WL[0] is performed after 256 clock cycles. It is completed. Then, another word line, for example WL[1], will be selected, and similar write operations will be performed. Similar write operations are performed until the entire page is written and the write operation is completed, and so on. Timing diagram 550 shows only WL[0] and one representative bit line pair BL[x]. However, this represents a write operation for all bits written to the memory array 410 of the schematic diagram 402 illustrated in FIG. 4B.

Referring again to FIG. 5B, the clock signal CLK is used to indicate the external synchronization timing requirements of the DDR NRAM memory. Throughout the first clock cycle (between “clock 0” and “clock 1”), the array voltages (represented by the waveform of “chip voltages”) are all V _DD . The select line (SL[x]) voltage is kept low (eg, to ground) during the entire write cycle. V _DD is typically, but not limited to, a voltage of about 1 V. The row address has been activated, and in this example, the word line WL[0] has been selected prior to the start of the first clock CLK cycle (not shown in Fig. 5B). The column address clock generator (Fig. 10) is activated by the write "command" WRT. The "column address" is received and stored in the column address buffer (Fig. 10). The column address C0 is selected at the start of the write cycle. In this example, there is an on-chip latency (delay) of two CLK cycles before external data is received by the data I/O buffer/driver 1067 (FIG. 10). Sensing amplifiers/latches such as the sensing amplifier/latch 430 (FIG. 4B) are inactive with a high PSET voltage and a low NSET voltage.

At the start of the second clock cycle (between CLK1 and CLK2), the column address clock generator (Fig. 10) is activated by the write "command" WRT, and "column address" (C0) is selected. To support the write operation, on-chip voltage generators provide a set voltage (V _SET ) in _{excess of V DD.} In this example, using known on-chip voltage generation methods, V _SET = V _DD x2 and the set overdrive voltage is V _DD x2 + V _TH . In this example, the selected word line (WL[0]) illustrated in the memory array 410 (Fig. 4B) is _{converted to V DD} x2+V _TH , which is a complete set voltage (V _DD x2) and non-volatile storage. The write current to the element SWx0 is enabled. However, it should be understood that in some cases, it may be desirable to limit the set current flowing into the corresponding non-volatile storage element SWx0 by operating the FET Tx0 in a saturation mode. In these cases, the word line (WL[0]) voltage can be driven to a voltage lower than _{V DD} x2 + V _TH to achieve the desired lower set current flow, which is much more than _{V DD x2.} Can be chosen small.

5B, at the beginning of the third clock cycle (between CLK2 and CLK3), the “command” within this cycle and within each of the subsequent cycles, as described in connection with cycles 1 and 2 above. And "column address" is activated. "Data in" starts with a data input (DI0) from a 4-bit external data bus, which is the data I/O buffer/driver at the end of cycle 3 during the positive transition of the clock ("CLK"). It is latched by (1067) (Fig. 10). Incoming data pulses on the external 4-bit data bus are switched _{between 0 and V DD} voltages for both rising and falling transitions of the clock CLK. These external data pulses are received by the data I/O buffer/driver 1067 in two groups of 4 bits (DI0 and DI0'). The data I/O buffer/driver 1067 (FIG. 10) _{boosts the voltage to a write voltage of V DD} x2, and corresponds to eight bits through the bidirectional internal data bus at each positive transition of the clock CLK. Data waveforms are transmitted to a bi-directional data bus control circuit 440 (Fig. 4B), where the D and nD pulses are in a voltage range of _{0 to V DD x2 as shown in the timing diagram 550 (Fig. 5B).} Is converted within.

A voltage shifter circuit, such as the voltage shifter circuit 801 shown in FIG. 5A, has 8 bits and data I on the on-chip data bus (FIG. 10) to generate pulses in the voltage range of _{0 to V DD x2 for write operations.} /O may be located between the buffer/driver 1067. The voltage shifter circuit 801 is activated during write operations and is inactive (bypassed) during read operations. Alternatively, the voltage shifter circuit 801 (FIG. 5A) can be incorporated as part of the bi-directional data bus control circuit 640 and is only active during write operations.

Continuing with the third clock cycle timing description, the sensing amplifiers/latches are activated by “SA/latch voltages” at the end of cycle 3. PSET _{transitions from V DD} to ground, thereby connecting the FET (T _SA5 ) to the sensing amplifier voltage (V _SA ), where V _SA = V _SET = (e.g., the sensing amplifier/latch in Fig. _{V DD} x2 for the (430) write operation. NSET transitions from 0 to V _SET = V _DD x2 voltage, thereby connecting the FET (T _SA6 ) to the low voltage (ground). “SA/latch voltages” shows one of eight sensing amplifiers that are activated during the first write cycle. In this page mode example, since there are 256 write cycles required to write all bits along the word line (WL[0]), the sensing amplifier/latch will delay the data bits until the completion of the first write cycle. It is called and remains active long enough to hold it temporarily. Then, it is deactivated until another 255 write cycles are completed to save power. It is reactivated when a new word line is selected by the row decoder (Fig. 10) (not shown). The column decoder (Fig. 10) again selects the eight sensing amplifiers, and the next write cycle begins. In this example, since the word line WL[0] is an even word line, "N-ISOLATE1" is activated at the end of cycle 3, and is also activated for any other even word lines selected. N-ISOLATE1 is used to connect the sensing amplifier/latch 430 to the memory array 410 as illustrated in FIG. 4B. However, if selected, instead N_ISOLATE2 (not shown in this example) will be activated for each odd word line. N_ISOLATE1 is shown to be deactivated after completion of the first write cycle to isolate the sensing amplifier/latch from the array until all bits are written along the word line WL[0] and a new word line is selected. Alternatively, the N_ISOLATE1 device can remain active because the corresponding sensing amplifier/latch is deactivated.

5B, at the beginning of the fourth clock cycle (between CLK3 and CLK4), "Data In" continues with a data input (DI0') from the 4-bit external data bus, which is the clock ("CLK Is latched by the data I/O buffer/driver 1067 (FIG. 10) in the middle of cycle 4 during the negative transition of "). At this point in the cycle, the eight bits represented by DI0 and DI0' are available from the data I/O buffer/driver 1067 on an 8-bit bidirectional "data bus". "CSL" is an 8-bit on-chip data bus, each of the eight sensing amplifiers/latches, such as the sensing amplifier/latch 430, which latches and temporarily holds the data and drives the corresponding "bit lines". It activates a two-way data bus control circuit 440 (Fig. 4B) that connects to it. In this example, timing diagram 550 shows one of eight selected sensing amplifiers that are activated and receive a logic "1" state corresponding to data bus input "D" illustrated by timing diagram 550. , This causes a set operation in which the bit line (BL[x]_D/R) is _{driven to V SET} = V _DD x2 and sets the nonvolatile storage element (SWx0) to a low resistance value corresponding to the logical "1" state. do. In this example, the "bit lines" BL[x]_D/R and BL[x]_R/D are connected to opposite terminals of the sensing amplifier/latch 430, which is the bit line BL[x ]_D/R) is _{converted to the set voltage (V DD} x2), while the complementary bit line BL[x]_R/D remains at a low voltage such as ground. In this example, a logical "1" data bit from one of the eight data bit inputs DI0 and DI0' is shown, which is a pair of bit lines BL[x] in memory array 410 (Fig. ) Causes a transition from a reset logic "0" state to a set logic "1" state in the nonvolatile storage element SWx0. A logical “0” data input bit will reset the nonvolatile storage element SWx0, ie leave it in a logical “0” state.

Referring to FIG. 5B, during the fifth clock cycle (between CLK4 and CLK5), the bit line BL[x]_D/R set cycle is completed. "SA/latch voltages" deactivate the corresponding sensing amplifier/latch. "N_ISOLATE1" turns the isolation transistors off to the off state. The word line WL[0] remains active until all bits have been written along the word line, and for this page mode example, this requires a total of 256 cycles. During the positive transition of the clock CLK, the following 4-bit DI1 data inputs are received from the external data bus, and then the 4-bit DDI1' data inputs are received during the negative transition of the clock CLK. Eight bits are temporarily latched by the data I/O buffer/driver 1067 (FIG. 10), which is transmitted on the 8-bit on-chip data bus. CSL is activated, and eight data bits are routed to eight different sensing amplifiers/latches corresponding to different column addresses decoded by the column decoder (FIG. 10). The other eight bits are written along the selected word line WL[0] but in the corresponding storage element locations and other cells in the memory array 410 (FIG. 4B). The activation of these other sensing amplifiers/latches and the turn on of the activation device are similar to those illustrated in timing diagram 550, except that they occur in subsequent clock cycles. Until all bits are written along the selected word line (WL[0]), the 8-bit data write operation is repeated again with input data (DI2 and DI2') in Cycle 6 (Cycle 5 to Cycle 6), etc. to be. In this page mode example, 2048 bits are written along the word line WL[0] in 256 cycles. Then, WL[0] is deactivated, and when another word line selected by the row decoder, for example WL[1], is activated, the DDR page mode write operation continues with the new word line. The waveforms shown in timing diagram 550 (FIG. 5B) are repeated until writing of all bits in the page is complete.

As discussed above, the exemplary write operation detailed in FIG. 5B is initially (logic') by applying a _{required set voltage (V DD x2 in this exemplary write operation) to the data bus line D.} It is used to adjust the selected array cell that was in a high resistance reset state (corresponding to 0') to a low resistance set state (corresponding to logic '1'). However, as this write operation will be consistent with the read/reset operation discussed in connection with Fig. 5A above, for a write operation, simply bring the data bus line D low (e.g., while being driven to 0V). ), it should be noted that by leaving this selected array cell in its initial reset state. Additionally, in other applications, this exemplary write operation also drives the data bus line to the required reset voltage (as discussed above), thereby resetting the resistive change element that was initially in a low resistance set to a high resistance. It could have been used to adjust to the state.

2nd DDR Compatible Resistive Change Element Array Architecture

As discussed in detail with reference to FIGS. 4A, 4B, 5A, and 5B above, in certain applications, the first DDR compatible resistive change element array architecture of the present disclosure is a write (or programming) operation. Voltage data pulses on the internal data bus that are relatively higher compared to the system level voltages used by the digital circuitry controlling the array during the period. In some embodiments, the electrical pulses synchronized to the system level clock may be a transition in amplitude between a high voltage level and a low voltage level corresponding to a preselected logic voltage. Within these applications, these higher voltages (including the sensing amplifier/latch) may require high voltage-compatible transistors along the entire data path. And—again, within a particular application—such larger, high voltage components may exhibit scaling and/or cost limitations within the memory array design. For this reason, a second DDR compatible resistive change element array architecture of the present disclosure is provided. This second architecture includes a voltage shifting element that can be used to reduce or otherwise eliminate the need for components of a large high voltage class within these specific applications.

Referring now to FIGS. 6A and 6B, such a second DDR compatible memory circuit architecture for an array of resistive change elements in accordance with the present disclosure is disclosed. As in FIGS. 4A and 4B, for ease of explanation, an exemplary schematic diagram 602 showing a single row (row “x”) is shown in a plurality of functional sections 610, 612, 615, 620, 625, 630. , And 640). Table 601 of FIG. 6A describes each of these functional sections, and their use within both read and write operations on the array.

Referring now to both Figures 6A and 6B, most of the sections within the second DDR compatible architecture of the present disclosure are shown in Figures 4A and 4B, with the significant exception of the isolation and balance section 620 during a write operation. It is the same in structure and function with the first DDR compatible architecture as discussed in detail above. The operation of the isolating and balancing section 620 (FIG. 6A) and the isolating and balancing section 420 (FIG. 4A) performs essentially the same function during reading. However, during the first DDR compatible architecture write operation, the isolation and balance section 420 is active, and the relatively high set voltage (V _DD x2) from the sensing amplifier/latch 430 is coupled to the memory array 410. do. Conversely, during a second DDR compatible architecture write operation, the isolation and balance section 620 is inactive, isolating the low V _DD voltage of the sensing amplifier/latch 630 from the memory 610, as a result of which the memory array When the bit line in 610 is driven with a relatively high set voltage (V _DD x2) by the voltage shifter 625 and the write select 615 circuit, the sensing amplifier/latch 630 is kept low _{at V DD.} . Thus, unlike the first DDR compatible architecture, the second DDR compatible architecture allows write data pulses from the 4-bit external data bus, switching between _{0 and V DD, during a write operation, to be transferred to a bi-directional data bus control circuit (} 640) on an 8-bit on-chip data bus, through data I/O buffer/driver 1067 (Figure 10), enables switching within the same low voltage range, and also operates between _{0 and V DD.} To enable temporary latching by the sensing amplifier/latch 630, thereby realizing the advantages of the second DDR compatible architecture further described above. The operation of the voltage shifter 625 and the write select 615 is further described below.

The first section 610 in this second DDR compatible architecture of the present disclosure is the memory array itself. Like the first architecture of Fig. 4b, these are individual array cells (CELLx0-CELLx3 in Fig. 6b) themselves, each of which is a resistive change element (SWx0-SWx3 in Fig. 6b) and a selection element (FETs (Tx0 in Fig. 6b) -Tx3)). Each of these cells is an array of word lines, a pair of bit lines (for each row), and a selection line (for each array row), as described in detail above with respect to FIG. 4B. Is addressable in response to

Section 612 in this second DDR compatible architecture includes reference resistors (same as section 412 in FIG. 4B). Section 620 in this second DDR compatible architecture provides balance and isolation devices. Section 630 in this second DDR compatible architecture is a sensing amplifier/latch. And, the bi-directional data bus control circuit 640 in this second DDR compatible architecture is a data bus bi-directional control unit. As with the memory array section 610, the structure and function of these sections is the same as the structure and function of their counterparts detailed in the discussion of Fig. 4B above and detailed in Fig. 4B.

Section 615 (write select controls) and section 625 (voltage shifter) of FIG. 6B provide the voltage shifting function during write operations in the second DDR compatible architecture. This voltage shifting function (described further above) will be described in more detail with reference to Figs. 7 and 8A to 8C, which includes a sensing amplifier/latch 630 and a bi-directional data bus control circuit ( _{Allow 640 to operate at V DD (} relatively lower than the system level voltage, as described above in connection with Figure 5B), and the memory array itself (section 610) is relatively higher programming. Limit exposure to voltages (“V _HI ”as listed in FIG. 6A) and exposure to sections 615 and 625 that provide these relatively high voltages. In this way, the need for larger and higher voltage class components for the entire data path during a write operation, such as would be required within certain applications using the first DDR compatible architecture of Fig. 4b, is greatly reduced. , This allows for more desirable design parameters (eg, with respect to scaling and cost) within these applications.

As shown in Fig. 6A, during a read operation using the second DDR compatible architecture of the present disclosure, section 615 (write select controls) and section 625 (voltage shifter) are disabled. As such, during read operations, the second DDR compatible architecture is essentially the same as the first DDR compatible architecture, and the read operation is the same as that shown in the waveform diagrams of FIG. 5A. As such, the discussion of the read operation detailed in Fig. 5A above is also an illustration of the read operation performed on the second DDR compatible architecture as shown in Fig. 6B. However, as described above, these new sections 615 and 625 provide a voltage shifting function and the memory array 610 voltage by providing a voltage _{V DD} x2 to the bit lines of the memory array 610 during a write operation. And current drive function. This voltage shifting and drive function is illustrated in the exemplary write operation detailed in FIG. 7.

Referring now to the timing diagram 700 illustrated in FIG. 7, a clock (CLK) signal (as described in conjunction with FIG. 5B) synchronizes the digital interfaces of the memory to an external controller or processor. As with the exemplary write operation on the first DDR compatible architecture of FIG. 5B, throughout the first clock cycle (between “clock 0” and “clock 1”) in FIG. 7, by the waveform of the “chip voltages” The array voltages (represented) are all held at _{V DD.} The select line SL voltage is kept low (eg, to ground) during the entire write cycle. V _DD is typically, but not limited to, a voltage of about 1 volt. The row address has been activated, and in this example, the word line WL[0] has been selected prior to the start of the first clock CLK cycle (not shown in Fig. 7). The column address clock generator (Fig. 10) is activated by the write "command" WRT. The "column address" is received and stored in the column address buffer (Fig. 10). The column address C0 is selected at the start of the write cycle. In this example, there is an on-chip latency (delay) of two CLK cycles before external data is received by the data I/O buffer/driver 1067 (FIG. 10). Sensing amplifiers/latches such as the sensing amplifier/latch 630 (FIG. 6B) are inactive with the PSET voltage being high and the NSET voltage being low. However, unlike the timing diagram 550 illustrated in FIG. 5B, in the timing diagram 700 (FIG. 6B ), N_ISOLATE1 is, as further described above, the sensing amplifier/latch 630 and the memory array 610. ) Is kept low for the entire write cycle to isolate from the relatively high voltages applied to the bit lines of.

Referring to the timing diagram 700 (Fig. 7), at the beginning of the second clock cycle (between CLK1 and CLK2), the column address clock generator (Fig. 10) is activated by the write "command" WRT, and the "column address &Quot;(C1) is selected, which is essentially the same timing as described above with respect to the timing diagram 550 shown in Fig. 5B. To support the write operation, on-chip voltage generators use known on-chip voltage generation methods to set voltage (V _{SET ) in excess of V DD} (in this example, V _SET = V _DD x2), and Provides the set overdrive voltage (V _DD x2 + V _{TH ).} Thus, for example, when V _DD = 1V, V _SET = 2V. In this example, the selected word line WL[0] illustrated in the memory array 610 (Fig. 6B) is _{converted to V DD} x2+V _TH , which is a complete set voltage (V _DD x2) and non-volatile storage. The write current to the element SWx0 is enabled. However, as described above with respect to FIG. 5B, in some cases, it may be desirable to limit the set current flowing into the corresponding nonvolatile storage element SWx0 by operating the FET Tx0 in a saturation mode. It must be understood that there is.

Referring to Fig. 7, at the beginning of the third clock cycle (between CLK2 and CLK3), the "instruction" within this cycle and within each of the subsequent cycles, as described in connection with cycles 1 and 2 above. And "column address" is activated. "Data In" starts with a data input (DI0) from a 4-bit external data bus, which at the end of cycle 3 during a positive transition of the clock ("CLK") data I/O buffer/driver 1067 ( It is latched by Fig. 10). Incoming data pulses on the external 4-bit data bus are switched _{between 0 and V DD} voltages for both rising and falling transitions of the clock CLK. These external data pulses are received by the data I/O buffer/driver 1067 in two groups of four bits and are temporarily latched. Then, the data I/O buffer/driver 1067, at each positive transition of the clock CLK _{, switches between V DD} and 0 volts, the data corresponding to the eight bits via the bidirectional internal data bus. The waveforms are sent to the bi-directional data bus control circuit 640 (Fig. 6B), where D and nD are also switched within the voltage range of _{V DD as shown in the timing diagram 700 (Fig. 7).} .

Continuing with the third clock cycle timing description, the sensing amplifiers/latches are activated by “SA/latch voltages” at the end of cycle 3. PSET is _{switched from V DD} to ground, thereby connecting the FET (T _SA5 ) to the sensing amplifier latch 630 voltage (V _SA = V _DD ) as shown in FIG. 6B. NSET transitions from 0 to V _DD voltage, thereby connecting the FET (T _SA6 ) to a low voltage (ground). “SA/latch voltages” shows one of eight sensing amplifiers that are activated during the first write cycle. In this page mode example, since there are 256 write cycles required to write all bits along the word line (WL[0]), the sensing amplifier/latch will delay the data bits until the completion of the first write cycle. It is called and remains active long enough to hold it temporarily. Then, it is deactivated until another 255 write cycles are completed to save power. It is reactivated when a new word line is selected by the row decoder (Fig. 10) (not shown), the color decoder (Fig. 10) again selects the eight sensing amplifiers, and the next write cycle begins. “N-ISOLATE1” is a timing diagram 700 in order to isolate the sensing amplifier/latch 630 from a relatively high write voltage applied to the bit lines of the memory array 610, as described further above. ) Remains disabled for the entire second DDR compatible architecture.

Referring to Figure 7, at the beginning of the fourth clock cycle (between CLK3 and CLK4), "Data In" continues with a data input (DI0') from the 4-bit external data bus, which is the clock ("CLK Is latched by the data I/O buffer/driver 1067 (FIG. 10) in the middle of cycle 4 during the negative transition of "). At this point in the cycle, the eight bits represented by DI0 and DI0' are available from the data I/O buffer/driver 1067 on an 8-bit bidirectional "data bus". "CSL" is a bi-directional data bus control circuit that connects an 8-bit on-chip data bus to each of the eight sensing amplifiers/latches, such as sensing amplifier/latch 630, which latches and temporarily holds the data. Activate 640 (Fig. 6B). In this example, the data bus input to be written into memory array 610 is shown as "D" in timing diagram 700. In a second DDR compatible architecture, voltage shifter 625 is activated as _{V HI transitions from low voltage to write set voltage (V DD} x2). As further described below with respect to FIGS. 8A to 8C, the voltages of the sensing amplifier/latch 630 terminals x1 and x2 are in the range of _{0 to V DD volts.} The voltage shifter 625 switches the _{output voltage O VS} from 0 to V _{DD x2.} In this example, since the even word line (WL[0]) is selected, WRITE_EVEN is switched to V _DD x2 + V _TH , and the output voltage (O _VS ) is the bit line (BL[x]_D/R). When driving with V _SET = V _DD x2, the write select 615 circuit FET (T _{WR_E} ) is activated, which sets the nonvolatile storage element SWx0 to a low resistance value corresponding to the logic "1" state. If the input data was a logic “0”, the sensing amplifier would have been in the opposite state, and the voltage shifter 625 output voltage (O _VS ) would have been a low voltage, essentially 0 volts, which is a nonvolatile storage element (SWx0) Will leave it in its pre-set high resistance reset state. It should be noted that if an odd word line is selected, WRITE_ODD will be enabled instead of WRITE_EVEN and the programming voltage O _VS will be driven on BL[x]_R/D instead. As described further above, since the low N_ISOLATE1 voltage keeps the isolation and balance circuit 620 in an inactive state, the combination of the voltage shifter 625 and the write selection 615 is isolated and balanced to perform the write operation. (620) Bypass the circuit.

Referring to FIG. 7, during the fifth clock cycle (between CLK4 and CLK5), the bit line BL[x]_D/R set cycle is completed. "SA/latch voltages" deactivate the corresponding sensing amplifier/latch. The voltage shifter 625 is _{turned off by separating V HI} from the chip voltage V _DD x2, and the write select 615 is deactivated by WRITE_EVEN. The word line WL[0] remains active until all bits have been written along the word line, and for this page mode example, this requires a total of 256 cycles. During the positive transition of the clock CLK, the following 4-bit DI1 data inputs are received from the external data bus, and then the 4-bit DDI1' data inputs are received during the negative transition of the clock CLK. Eight bits are temporarily latched by the data I/O buffer/driver 1067 (FIG. 10), which is transmitted on the 8-bit on-chip data bus. CSL is activated, and eight data bits are routed to eight different sensing amplifiers/latches corresponding to different column addresses decoded by the column decoder (FIG. 10). The other eight bits are written along the selected word line WL[0] but in the corresponding storage element locations and other cells in the memory array 610 (FIG. 6B). The activation of these other sensing amplifiers/latches and the turn on of the activation device are similar to those illustrated in the timing diagram 700, except that they occur in subsequent clock cycles. Until all bits are written along the selected word line (WL[0]), the 8-bit data write operation is repeated again with input data (DI2 and DI2') in Cycle 6 (Cycle 5 to Cycle 6), etc. to be. In this page mode example, 2048 bits are written along the word line WL[0] in 256 cycles. Then, WL[0] is deactivated, and when another word line selected by the row decoder, for example WL[1], is activated, the DDR page mode write operation continues with the new word line. The waveforms shown in the timing diagram 700 are repeated until writing of all bits in the page is completed.

The second DDR compatible architecture is essentially the same write function (respectively) as the first DDR compatible architecture (table 401, schematic 402, and timing diagram 550 illustrated in FIGS. 4A, 4B, and 5B). , Table 601, schematic diagram 602, and timing diagram 700 illustrated in FIGS. 6A, 6B, and 7 were performed. However, the second DDR compatible architecture has a relatively low operating voltage (V) within the entire data path including the sensing amplifier/latch, digital data interface, on-chip data bus, and data I/O buffer/driver 1067. _DD ) (in this example, approximately 1V) was used. The higher write voltage of V _DD x2 was used only to drive the bit lines. Since the first DDR compatible architecture used a relatively high V _DD x2 voltage within the entire data path, the second architecture requires much fewer large high voltage class components for the entire data path, which means a lower voltage swing ( swings), which greatly reduces the power dissipation, which leads to more desirable (beneficial) design parameters within these applications, for example with respect to scaling and cost, as further explained above.

8A-8C illustrate the functionality of the voltage shifter 625 shown in FIG. 6B and used within an exemplary write operation on the second DDR compatible resistive change element array detailed in FIG. 7. 8A shows a voltage shifter circuit 801 having input nodes X1 and X2 connected to a sensing amplifier/latch 630, isolated from the array circuit for clarity. 8B shows a first state 802 of node voltages in the voltage shifter circuit 801 when the input node X1 is a voltage V _{DD and the input node X2 is 0 V, which is the output voltage Cause} (O VS) = 0V. In addition, FIG. 8C shows a second state 803 of node voltages in the voltage shifter circuit 801 when the input node X1 is 0V and the input node X2 is a voltage V _{DD, which is} It causes the output voltage (O _VS ) = V _{DD x2.}

Referring now to FIG. 8A, the PFET devices T _VS1 and T _VS2 are connected together and pulled up to _{V HI} representing the required programming voltage (as described above with respect to FIGS. 6B and 7 ). It has up) source terminals. As with the exemplary write operation of FIG. 7, within FIGS. 8B and 8C _{, it is assumed that this programming voltage is V DD} x2, or twice the voltage level of the digital circuit driving the array. The drain of T _VS1 is connected to the drain of the NFET device T _VS4 and the gate of _{T VS2 at node O VS.} The drain of T _VS2 is connected to the drain of the NFET (T _VS3 ) and _{the gate of T VS1.} The source of T _{VS3 is connected to the gate of T VS4} and is connected to the terminal X1 connected to the sensing amplifier/latch 630. The source of T _{VS4 is connected to the gate of T VS3} and is connected to the terminal X2 which is also connected to the sensing amplifier/latch 630.

As shown in Fig. 8B, when V _DD is applied to X1 and 0V is applied to X2 (which represents a logic '0' temporarily stored in the sensing amplifier/latch 630), T _VS2 and T _VS4 are turned On, T _VS1 and T _VS3 are turned off. This results in 0V at node O _VS , which essentially means that there is no programming voltage or current driven onto the bit line. However, as shown in Figure 8c, when 0V is applied to the X1 and V _DD it is applied to the X2 (which represents a logic "1" temporarily stored in the sense amplifier / latch (630)), T _VS1 and T _VS3 this is turn oN, the turn-off T _VS2 and T _VS4. Referring now to FIG. 6B circuits, that is, the bidirectional data bus control 640, the sensing amplifier/latch 630, and the voltage shifter 625, the terminal D is V _DD corresponding to the logic "1" and the terminal When (nD) is 0 volts, the sensing amplifier/latch terminals are X1 = 0 and X2 = V _DD . This causes _{V HI} (programming voltage V _DD x2 required in this example) to be driven out at _{node O VS.}

Referring now to FIG. 9, a simplified block diagram of a resistive change element memory array 900 is used to illustrate how the simplified array row schematics 402 and 602, respectively, are used within the entire memory array. The memory array 900 includes "n+1" rows, and each row includes "m+1" memory cells. Or put another way, resistive change memory array 900 includes an array of resistive change memory elements arranged in a grid of "n+1" rows and "m+1" columns. As described above, each of the simplified schematic diagrams of FIGS. 4B and 6B shows a representative single row (row “x”) of the first and second DDR compatible resistive change element architectures of the present disclosure, respectively.

Each of the rows ROW0, ROW1, ROW3, and ROWn in the resistive change memory array 900 is represented by a block (910, 920, 930, and 940, respectively). Each of these blocks 910-940 represents either the simplified array row schematic 402 illustrated in FIG. 4B or the simplified array row schematic 602 illustrated in FIG. 6B, respectively. It has been described in detail in connection with the waveform diagram 550 and the waveform diagram 700 shown in FIG. 7. Isolation controls (N_ISOLATE1, N_ISOLATE2, and EQ in FIGS. 4B and 6B), sensing amplifier/latch controls (NSET and PSET in FIGS. 4B and 6B), output controls (CSL in FIGS. 4B and 6B), and Write selection controls (WRITE_EVEN and WRITE_ODD in FIGS. 4B and 6B) are not shown in FIG. 9 for clarity. However, all rows 910-940 are considered to be responsive to these control signals.

9, "n+1" pairs of bit lines BL[n:0]_D/R and BL[n:0]_R/D are resistive change memory array 900 It is used to provide a dedicated pair of folding bit lines for each row 910-940 within. BL[n:0]_D/R is similar to BL[x]_D/R of FIGS. 4B and 6B, and BL[n:0]_R/D is BL[x]_R/D of FIGS. 4B and 6B. Is similar to The array of select lines SL[n:0] provides a select line (similar to SL[x] in FIGS. 4B and 6B) to each row 910-940 in the resistive change memory array 900. Is used for An array of "m+1" word lines (WL[m:0]) is common to all rows 910-940 in the array, and "m+1" number of "m+1" word lines in each array row 910-940 Each of the resistive change memory cells responds to one of these word lines. WL[m:0] is similar to WL[3:0] in FIGS. 4B and 6B. WL_ODD and WL_EVEN are control signals also common to all rows 910-940 in memory array 900. As detailed within the discussion of FIGS. 4B, 5A, and 6B, each array row 910-940 in memory array 900 includes two reference elements. Within each array row 910-940, each of these reference elements responds to either WL_ODD or WL_EVEN as detailed in the discussion of FIGS. 4A, 5A, and 6B above.

The buffer/decoder element 950 is connected to each of the data lines (D and nD in FIGS. 4B and 6B) of the array rows 910-940, and transmits these data signals to data input/output (I/O). Used to arrange into an interface. In this way, data lines from each row can be selected and processed to suit the needs of the interface to a particular application using a particular external control circuit element (eg, but not limited to a microprocessor or FPGA).

Referring now to FIG. 10, a system level block diagram illustrating an exemplary 1Gb x 4 resistive change memory 1000 suitable for use within the first and second DDR compatible resistive change array architectures of the present disclosure is shown.

In the core of the resistive change memory 1000 (FIG. 10), a 4 gigabit memory array element 1010 is architected in a 32,768 x 32,768 x 4 configuration. The memory array element 1010 is coupled to an array of sensing amplifiers 1030 through an array of isolation devices 1020. The isolation/write selection circuits 1020 respond to a pair of isolation control signals N_ISOLATE1 and N_ISOLATE2 or a pair of write selection control signals WRITE_EVEN and WRITE_ODD. For the first DDR architecture, an isolation circuit control signal (N_ISOLATE) is used. However, for the second DDR architecture, the isolation circuit control signal N_ISOLATE is used for read, and the write select control signal WRITE is used during the write operation. The sensing amplifiers 1030 respond to the control signals NSET and PSET, temporarily store array data, and provide this to the I/O gate block 1040. Referring again to the simplified array row schematics (402 in FIG. 4B and 602 in FIG. 6B), the memory array element 1010 is similar to elements 410 and 610; Isolation/write selection circuits 1020 are similar to elements 420, 620, and 615; The sensing amplifier/latch circuits 1030 are similar to elements 430 and 630; And I/O gate block 1040 is similar to element bi-directional data bus control circuits 440 and 640. The data out buffer/decoder 1060 including the data I/O buffer/driver 1067 and the data in buffer/decoder 1065 are similar to the element 950 of FIG. 9, and the memory 1000 and the external control circuit Provides interface control between elements (eg, but not limited to a microprocessor, microcontroller, or FPGA).

In response to the row address strobe control signal, the RAS clock generator 1045 provides timing signals to the row address buffer 1005 and the row decoder 1015, which are routed to the address bus A[14:0]. In response, it generates row array lines required to address memory array 1010. In response to the column address strobe control signal, the CAS clock generator 1050 provides a timing signal to the column address buffer 1025, which addresses the memory array 1010 in response to the address bus A[14:0]. To create the column array lines required to do so. The write enable control signal is a column address strobe control signal to provide timing control to the data in buffer/decoder 1065 and the data out buffer/decoder 1060 including the data I/O buffer/driver 1067. And are ANDed.

Although not shown in FIG. 7 (for clarity), external control circuit elements (e.g., but not limited to a microprocessor, microcontroller, or FPGA) are shown in FIGS. 4A and 4B with respect to the resistive change memory architecture of the present disclosure. 5A, 5B, 6A, 6B, and 7 are used to apply different control signals and manage the timing of these control signals, as described in FIGS. 5A, 5B, 6A, 6B, and 7 above. For example, the read operations detailed (and described above) in FIG. 5A, and the write operations detailed (and described above) in FIGS. 5B and 7 can accommodate various structures while optimally meeting the needs of a particular application. It can be implemented through. For example, FPGAs, PLDs, microcontrollers, logic circuits, or a software program running on a computer all execute the algorithms of the programming operations detailed in Figs. It can be used to provide control and selection signals. In this way, the individual resistive change memory cells in the memory array element 1010 of FIG. 10 are independently selected and programmed (as described above) or read back, e.g., as required for a particular application. Can be.

Although the resistive change memory array architecture of the present disclosure has been presented using the exemplary simplified schematic diagrams in FIGS. 4B and 6B and the block diagrams of FIGS. 9 and 10, the methods of the present disclosure are limited to these specific electrical circuits shown It should be noted that it should not be. Rather, it will be apparent to those skilled in the art that the electrical circuits shown in FIGS. 4B, 6B, 9 and 10 can be modified in various ways to optimize the circuit to implement the advanced architectures described within a particular application. something to do.

And, it is preferable that the foregoing description of resistive change memory array architectures is representative, includes such variations, and is not otherwise limited to the specific exemplary parameters detailed.

While the present invention has been described with respect to specific embodiments of the invention, many other variations and modifications and other applications will become apparent to those skilled in the art. Accordingly, it is preferred that the present invention is not limited by the specific disclosure herein.

Claims (28)

As a resistive change element memory array,
A plurality of word lines;
A plurality of bit lines;
A plurality of selection lines;
Isolation and equilibration module;
A plurality of memory cells;
A plurality of reference elements; And
A plurality of sensing amplifiers
Including,
The isolation and balance module includes an isolation portion and a balance portion,
The memory cells,
A resistive change element having a first terminal and a second terminal, wherein the first terminal is in electrical communication with a selection line, and the resistive change element is configured to correspond to a first resistance value and a second information state corresponding to the first information state. Said resistive change element having a corresponding second resistance value and being capable of being switched between at least two non-volatile resistance values; And
A selection device responsive to a control signal on a word line, the selection device selectively providing a conductive path between the bit line and the second terminal of the resistive change element
Including,
The reference elements,
A resistive reference element having a first terminal and a second terminal, wherein the first terminal is in electrical communication with a selection line, and the resistive reference element is an electrical resistance selected to fall between the first resistance value and the second resistance value. Having, the resistive reference element; And
A selection device responsive to a control signal on a word line, the selection device selectively providing a conductive path between the bit line and the second terminal of the resistive reference element
Including,
Each of the sensing amplifiers responds to at least one bit line electrically coupled to the resistive change element and at least one bit line electrically coupled to the resistive reference element,
The one sensing amplifier among the plurality of sensing amplifiers is electrically connected to the rate of discharge on the bit line electrically coupled to the resistive change element selected by the word line and the resistive reference element selected by the word line. The rate of discharge on the combined bit line can be compared,
The comparison is used to read the information state of the selected memory cell,
The isolation portion of the isolation and balance module includes a set of isolation circuit elements controlled by a pair of control signals, the isolation portion being configured to prevent data reversal during a read cycle, and wherein the balance portion is a read operation. Previously configured to balance the bit line pair voltages. The method of claim 1,
The memory cells are arranged in a plurality of rows and columns, each row is arranged in a folded bit line structure using two bit lines, the memory cell having a row Each of which is electrically coupled to one of the two bit lines. The method of claim 2,
Each row includes two reference elements, a first reference element is coupled to one of the two bit lines, and a second reference element is electrically connected to the other of the two bit lines. A resistive change element memory array. The method of claim 3,
Wherein each row includes a sensing amplifier, the sensing amplifier responsive to both bit lines in its own row. The method of claim 1,
Wherein the resistive change elements are selected from the group consisting of two-terminal nanotube switching elements, metal oxide memory elements, and phase change memory elements. The method of claim 1,
Wherein the sensing amplifiers are coupled to at least one of the bit lines by the isolation and balance module. The method of claim 1,
The sensing amplifiers are capable of transmitting the information state of a plurality of bit lines to the on-chip data bus in the memory array through bi-directional data bus control circuits coupled to the on-chip data bus. Change element memory array. The method of claim 7,
Wherein the information state of a plurality of bit lines is transmitted to the on-chip data bus as electrical pulses synchronized to a system level clock. The method of claim 8,
Wherein the synchronized electrical pulses are provided from the external data bus to the on-chip data bus at a data rate of less than half the data rate of the external data bus. The method of claim 9,
Wherein the on-chip data bus has a number of data bus lines that is at least twice the number of data lines in the external data bus. The method of claim 8,
Wherein the synchronized electrical pulses transition in amplitude between a high voltage level and a low voltage level corresponding to a preselected logic voltage. The method of claim 1,
Wherein the resistive change element memory array is compatible with a double data rate (DDR) memory architecture. As a resistive change element memory array,
A plurality of word lines;
A plurality of bit lines;
A plurality of selection lines;
Isolation and balance modules;
A plurality of memory cells; And
Multiple sensing amplifiers
Including,
The isolation and balance module includes an isolation portion and a balance portion,
The memory cells,
A resistive change element having a first terminal and a second terminal, wherein the first terminal is in electrical communication with a selection line, and the resistive change element is configured to correspond to a first resistance value and a second information state corresponding to the first information state. Said resistive change element having a corresponding second resistance value and being capable of being switched between at least two non-volatile resistance values; And
A selection device responsive to a control signal on a word line, the selection device selectively providing a conductive path between the bit line and the second terminal of the resistive change element
Including,
Each of the sensing amplifiers is coupled to at least one bit line and responds to at least one data line electrically coupled to the on-chip data bus by a bi-directional data bus control circuit,
The one sensing amplifier among the plurality of sensing amplifiers may be used to apply a voltage on a bit line electrically coupled to a resistive change element by a cell selection device selected by a word line,
The applied voltage is used to program the information state of the selected memory cell,
The isolation portion of the isolation and balance module includes a set of isolation circuit elements controlled by a pair of control signals, the isolation portion configured to prevent data reversal during a read cycle, the balanced portion being a bit prior to a read operation. Wherein the resistive change element memory array is configured to balance line pair voltages. The method of claim 13,
Wherein the sensing amplifiers are coupled to a voltage source to program the resistive change element. The method of claim 13,
Wherein the sensing amplifiers are capable of transmitting data values provided by the on-chip data bus to these resistive change elements in the resistive change element memory array that were selected for non-volatile storage of the data values. Change element memory array. The method of claim 15,
Wherein the data values are provided to the on-chip data bus from an external data bus as electrical pulses synchronized to a system level clock. The method of claim 16,
Wherein the electrical pulses are provided from the external data bus to the on-chip data bus at a data rate of less than half the data rate of the external data bus. The method of claim 17,
Wherein the on-chip data bus has a number of data bus lines at least twice that of the external data bus. The method of claim 16,
Wherein the synchronized electrical pulses are switched in amplitude between a high voltage level and a low voltage level corresponding to a preselected logic voltage, the preselected logic voltage being sufficient to program the resistive change elements in the array. Element memory array. As a resistive change element memory array,
A plurality of word lines;
A plurality of bit lines;
A plurality of selection lines;
An isolating and balancing module, comprising: an isolating and balancing module;
A plurality of memory cells;
As a plurality of sensing amplifiers, each of the sensing amplifiers is electrically coupled to an on-chip data bus by a bi-directional data bus control circuit, a voltage shifting element-the voltage shifting element is at least one The plurality of sensing amplifiers being electrically coupled to at least one input of-comprising an input terminal and at least one output terminal; And
Interconnect circuit capable of providing a selectively conductive path between at least one output terminal of the voltage shifting element and at least one of the bit lines
Including,
The memory cells,
A resistive change element having a first terminal and a second terminal, wherein the first terminal is in electrical communication with a selection line, and the resistive change element is configured to correspond to a first resistance value and a second information state corresponding to the first information state. Said resistive change element having a corresponding second resistance value and being capable of being switched between at least two non-volatile resistance values; And
A selection device responsive to a control signal on a word line, the selection device selectively providing a conductive path between the bit line and the second terminal of the resistive change element
Including,
The voltage shifting element may provide a programming voltage to at least one of its own output terminals in response to a logic level voltage provided to at least one of its own input terminals,
At least one of the plurality of memory cells in the memory array is selected by activating a selection line and a word line associated with the at least one of the plurality of memory cells,
The selected memory cell includes the output terminal of the voltage shifting element providing a desired logic level voltage to the input terminal of the voltage shifting element and providing the programming voltage, the selected memory cell and Associated and programmed by electrically coupling to the bit line electrically coupled to the resistive change element by the selection device via the interconnection circuit,
The isolation portion of the isolation and balance module includes a set of isolation circuit elements controlled by a pair of control signals, the isolation portion configured to prevent data reversal during a read cycle, the balanced portion being a bit prior to a read operation. Wherein the resistive change element memory array is configured to balance line pair voltages. The method of claim 20,
Wherein the resistive change elements are selected from the group consisting of two-terminal nanotube switching elements, metal oxide memory elements, and phase change memory elements. The method of claim 20,
Wherein the sensing amplifiers operate at a preselected logic voltage level. The method of claim 20,
In response to information states being driven onto the on-chip data bus, the sensing amplifiers provide data values to the voltage shifting elements, and in response to the data values, the voltage shifting elements Providing programming voltages to these bit lines electrically coupled to the selected resistive change elements. The method of claim 23,
Wherein the data values are provided to the on-chip data bus by an external data bus as electrical pulses synchronized to a system level clock. The method of claim 24,
Wherein the synchronized electrical pulses are provided from the external data bus to the on-chip data bus at a data rate of less than half the data rate of the external data bus. The method of claim 24,
Wherein the on-chip data bus has a number of data bus lines at least twice that of the external data bus. The method of claim 24,
Wherein the synchronized electrical pulses are switched in amplitude between a high voltage level and a low voltage level corresponding to a preselected logic voltage, the preselected logic voltage being sufficient to program the resistive change elements in the array. Element memory array. The method of claim 20,
Wherein the resistive change element memory array is compatible with a double data rate (DDR) memory architecture.

Images