KR102206323B1 - Signal transmitting circuit using common clock, and storage device therewith - Google Patents

Abstract

The present invention provides a transmission circuit. The transmission circuit includes a plurality of transmitters, each of which outputs data in series, an operational clock generator that generates an operational clock signal, and a clock divider that divides the operational clock signal to generate a symbol clock signal. Each of the plurality of transmitters is provided with a working clock signal and a symbol clock signal in common. According to the present invention, among a plurality of transmitters, a clock signal provided to one transmitter can be synchronized with the clock signal provided to another transmitter.

Description

Transmission circuit using a common clock, and a storage device including the same {SIGNAL TRANSMITTING CIRCUIT USING COMMON CLOCK, AND STORAGE DEVICE THEREWITH}

The present invention relates to an interface technology, and more particularly, to a signal transmitter for interfacing between electronic devices and a storage device including the same.

Today, various types of electronic devices are used. The electronic device can perform its own function by itself. Furthermore, the electronic device may perform its own function while exchanging signals and data with other electronic devices. Interface technology is used to exchange signals and data between two electronic devices. As the types of electronic devices diversify, the types of interface protocols have also diversified.

For example, the MIPI (Mobile Industry Processor Interface) Alliance (Alliace) proposed an interface protocol using "UniPro" as a link layer to unify the interfacing process of mobile devices. UniPro supports a physical layer called "PHY". The physical layer of an interface circuit such as a PHY includes a transmitter and a receiver for exchanging signals with other interface circuits.

The transmitter transmits signals and data to the receiver. According to certain interface protocols, a plurality of transmitters are used to increase the bandwidth for data transmission. If multiple transmitters are used, one transmitter can operate independently regardless of whether the other transmitter is operating. By outputting data through each of the plurality of transmitters, more data can be transmitted.

The transmitter operates in synchronization with a clock signal. Each of the plurality of transmitters is independently provided with a clock signal. However, when each of the plurality of transmitters operates independently, a clock signal provided to one transmitter may not be synchronized with the clock signal provided to another transmitter. Accordingly, when each of the plurality of transmitters operates independently, the timing of data transmission may be skewed between lanes corresponding to each of the plurality of transmitters. As a result, errors may occur in data transmission.

A transmission circuit is provided for making the timing of data transmission not shifted between lanes respectively corresponding to a plurality of transmitters. According to an embodiment of the present invention, each of a plurality of transmitters may receive a common clock signal.

A transmission circuit according to an embodiment of the present invention includes a plurality of transmitters each configured to serially output data; An operational clock generator configured to generate an operational clock signal; And a clock divider configured to divide the working clock signal to generate a symbol clock signal. Each of the plurality of transmitters may be configured to receive a working clock signal and a symbol clock signal in common. Further, each of the plurality of transmitters includes: a serializer configured to receive parallel data in synchronization with a symbol clock signal and serialize the parallel data in synchronization with an operation clock signal to generate serial data; A digital logic configured to receive original data and extract symbol-unit data from the original data based on a symbol clock signal provided through the serializer to generate parallel data to be provided to the serializer; And a driver configured to output serial data.

In an embodiment of the present invention, a lane reset signal used to reset a state of a lane corresponding to each of a plurality of transmitters and a power down signal used to stop an operation of each of the plurality of transmitters are independently Is provided, and each of the plurality of transmitters may be configured to operate independently based on the lane reset signal and the power down signal.

In an embodiment of the present invention, each of the plurality of transmitters includes: a working clock buffer, configured to pass the working clock signal to the serializer when the lane reset signal and the power down signal are not provided; And a symbol clock buffer configured to transfer the symbol clock signal to the serializer when the lane reset signal and the power down signal are not provided.

In an embodiment of the present invention, when at least one of a lane reset signal and a power down signal is provided, the working clock buffer and the symbol clock buffer may be configured not to transmit the working clock signal and the symbol clock buffer to the serializer, respectively.

In an embodiment of the present invention, the operational clock generator may include a PLL circuit.

In an embodiment of the present invention, the serializer comprises: a latch configured to receive parallel data from digital logic; And a multiplexer configured to receive parallel data from the latch and generate serial data. In this embodiment, the latch may be configured to receive parallel data in synchronization with the symbol clock signal. Further, in this embodiment, the multiplexer may be configured to serialize parallel data in synchronization with an operating clock signal to generate serial data.

In an embodiment of the present invention, data in units of symbols has a length of N bits, and a period of a symbol clock signal may be N times a period of an operation clock signal.

The transmission circuit according to an embodiment of the present invention is configured to output an operation clock signal used to serialize parallel data, and a symbol clock signal generated by dividing the operation clock signal and used to extract data in units of symbols. Clock block; And a transmission block including a plurality of transmitters each configured to receive a working clock signal and a symbol clock signal in common. Each of the plurality of transmitters receives original data, extracts symbol-unit data from the original data based on the symbol clock signal to generate parallel data, serializes the parallel data in synchronization with the operating clock signal, and outputs the serialized data. Can be configured to

In an embodiment of the present invention, each of the plurality of transmitters may be configured to operate independently using operating power.

In an embodiment of the present invention, even when the first time when the first transmitter starts operation among the plurality of transmitters is different from the second time when the second transmitter starts operation, the symbol clock signal provided to the first transmitter is the second transmitter. It can be synchronized with the symbol clock signal provided as.

In an embodiment of the present invention, a lane reset signal used to reset a state of a lane corresponding to each of a plurality of transmitters and a power down signal used to stop an operation of each of the plurality of transmitters are independently Can be provided.

In an embodiment of the present invention, a transmitter not provided with a lane reset signal and a power down signal among a plurality of transmitters may operate, and a transmitter receiving at least one of a lane reset signal and a power down signal may stop operating.

In an embodiment of the present invention, the transmission block may be included in a physical layer defined based on the MIPI M-PHY specification.

A storage device according to an embodiment of the present invention includes a memory controller; A nonvolatile memory configured to store data under control of a memory controller; And an interface circuit configured to serially output data according to an interface protocol using a physical layer. The interface circuit includes: a plurality of transmitters included in the physical layer; An operational clock generator configured to generate an operational clock signal; And a clock divider configured to divide the working clock signal to generate a symbol clock signal. The operational clock signal and the symbol clock signal may be provided in common to each of the plurality of transmitters. Furthermore, each of the plurality of transmitters receives data stored in a nonvolatile memory, extracts data in units of symbols based on the symbol clock signal to generate parallel data, and serializes the parallel data in synchronization with the operating clock signal to obtain serial data. It can be configured to generate and output serial data.

In an embodiment of the present invention, each of the plurality of transmitters includes: digital logic configured to receive stored data and extract data in units of symbols based on a symbol clock signal to generate parallel data; A serializer configured to receive parallel data from digital logic in synchronization with a symbol clock signal and serialize the parallel data in synchronization with an operation clock signal to generate serial data; And a driver configured to output serial data.

In an embodiment of the present invention, digital logic may be configured to receive a symbol clock signal through a serializer.

In an embodiment of the present invention, each of the plurality of transmitters is based on a lane reset signal used to reset a state of a lane corresponding to each of the plurality of transmitters and a power down signal used to stop operation of each of the plurality of transmitters. It is configured to operate independently, and even when the first time when the first transmitter starts operation among the plurality of transmitters is different from the second time when the second transmitter starts operation, the symbol clock signal provided to the first transmitter is a second transmitter It can be synchronized with the symbol clock signal provided as.

In an embodiment of the present invention, the physical layer is defined based on the MIPI M-PHY specification, and the memory controller may be configured to exchange data with the nonvolatile memory according to the UFS interface protocol. Further, the memory controller, the nonvolatile memory, and the interface circuit may be implemented in an embedded storage configured to be embedded in a mobile electronic system or a card storage configured to be connected to a mobile electronic system.

According to an embodiment of the present invention, among a plurality of transmitters, a clock signal provided to one transmitter may be synchronized with a clock signal provided to another transmitter. Accordingly, timing of data transmission may not be shifted between lanes corresponding to each of the plurality of transmitters. As a result, data can be stably transmitted through a plurality of transmitters.

1 is a block diagram showing the configuration of an electronic system including two electronic devices connected to each other.
FIG. 2 is a conceptual diagram illustrating a connection between interface circuits included in each of two electronic devices of FIG. 1.
3 is a block diagram showing the configuration of a transmission circuit according to an embodiment of the present invention.
4 is a block diagram showing a plurality of transmitters according to an embodiment of the present invention.
5 is a block diagram showing the configuration of a transmission circuit according to an embodiment of the present invention.
6 is a conceptual diagram showing the configuration of a plurality of transmitters according to an embodiment of the present invention.
7 is a block diagram showing the configuration of a transmitter according to an embodiment of the present invention.
8 is a timing diagram showing a case where the timing of data transmission is shifted between lanes corresponding to a plurality of transmitters, respectively.
9 is a timing diagram showing an effect obtained by an embodiment of the present invention.
10 is a block diagram showing the configuration of a storage system according to an embodiment of the present invention.
11 is a block diagram showing the configuration of an embedded storage according to an embodiment of the present invention.
12 is a block diagram showing the configuration of a storage system including a card storage according to an embodiment of the present invention.
13 is a block diagram illustrating a configuration of an electronic system including a transmission circuit according to an embodiment of the present invention and interfaces operating according to an embodiment of the present invention.

The above-described characteristics and the detailed description below are all exemplary matters to aid in the description and understanding of the present invention. That is, the present invention is not limited to this embodiment and may be embodied in other forms. The following embodiments are merely examples for completely disclosing the present invention, and are descriptions for delivering the present invention to those skilled in the art to which the present invention pertains. Accordingly, when there are multiple methods for implementing the constituent elements of the present invention, it is necessary to clarify that the present invention can be implemented in any of the specific ones or equivalents thereof.

In the present specification, when there is a mention that a certain component includes specific elements, or when there is a mention that a certain process includes specific steps, it means that other elements or other steps may be further included. That is, terms used in the present specification are only for describing specific embodiments, and are not intended to limit the concept of the present invention. Furthermore, examples described to aid in understanding the invention also include complementary embodiments thereof.

Terms used in the present specification have the meanings generally understood by those of ordinary skill in the art to which the present invention belongs. Terms commonly used should be interpreted in a consistent sense according to the context of the present specification. In addition, terms used in the present specification should not be interpreted as excessively ideal or formal meanings unless the meaning is clearly defined. Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing the configuration of an electronic system including two electronic devices connected to each other. The electronic system 100 may include a first electronic device 110 and a second electronic device 120. The first electronic device 110 may include a first interface circuit 113 and a first controller 115. The second electronic device 120 may include a second interface circuit 123 and a second controller 125. However, each of the first electronic device 110 and the second electronic device 120 may further include other components not shown in FIG. 1. The configuration shown in FIG. 1 is only an example to aid understanding of the present invention.

As an embodiment, the first electronic device 110 may be a host. For example, when the electronic system 100 is a mobile electronic system, the first electronic device 110 may include an application processor. As an embodiment, the second electronic device 110 may be a storage device.

However, the present invention is not limited to the above embodiments. For example, the function and configuration of the first electronic device 110 may be interchanged with the function and configuration of the second electronic device 120. Furthermore, the first electronic device 110 and the second electronic device 120 may be different types of electronic devices. For example, each of the first electronic device 110 and the second electronic device 120 may be one of a display device, an image sensor, and a wireless communication chip. The above embodiments are only examples to aid understanding of the present invention.

The first electronic device 110 may be connected to the second electronic device 120 through the first interface circuit 113. The first electronic device 110 may exchange signals and data with the second electronic device 120 through the first interface circuit 113. The first interface circuit 113 may include a first physical layer (PL1).

The first physical layer PL1 may include physical components for exchanging data with the second electronic device 120. For example, the first physical layer PL1 may include a transmitting circuit and a receiving circuit for exchanging data with the second electronic device 120. In particular, in order to increase the bandwidth for data transmission, the transmission circuit of the first physical layer PL1 may include a plurality of transmitters.

As an embodiment, when the electronic system 100 is a mobile electronic system, the first physical layer PL1 may be defined by the “M-PHY” specification. M-PHY is an interface protocol proposed by the MIPI (Mobile Industry Processor Interface) Alliance (Alliace). In this embodiment, the first interface circuit 113 may further include a link layer (not shown) that manages data composition, integrity, and error. Furthermore, in this embodiment, the link layer of the first interface circuit 113 may further include a Physical Adapted Layer (not shown). The physical adaptation layer may control the first physical layer PL1, such as managing a symbol of data or managing power.

However, the present invention is not limited to the above embodiments. As will be described later, the present invention can be employed in any interface circuit including a plurality of transmitters. The above embodiments are only examples to aid understanding of the present invention.

The first controller 115 may manage and control the overall operation of the first electronic device 110. In particular, the first controller 115 may process and manage signals and data exchanged through the first interface circuit 113. Under the control of the first controller 115, the first electronic device 110 may perform a unique function.

The second electronic device 120 may be connected to the first electronic device 110 through the second interface circuit 123. The second electronic device 120 may exchange signals and data with the first electronic device 110 through the second interface circuit 123. The second interface circuit 123 may include a second physical layer PL2.

The second physical layer PL2 may include physical components for exchanging data with the first electronic device 110. For example, the second physical layer PL2 may include a transmission circuit and a reception circuit for exchanging data with the first electronic device 110. In particular, in order to increase the bandwidth for data transmission, the transmission circuit of the second physical layer PL2 may include a plurality of transmitters.

As an embodiment, when the electronic system 100 is a mobile electronic system, the second physical layer PL2 may be defined by the M-PHY specification. In this embodiment, the second interface circuit 123 may further include a link layer (not shown) and a physical adaptation layer (not shown).

The second controller 125 may manage and control the overall operation of the second electronic device 120. In particular, the second controller 125 may process and manage signals and data exchanged through the second interface circuit 123. Under the control of the second controller 125, the second electronic device 120 may perform its own function.

As an embodiment, when the second electronic device 120 is a storage device including a flash memory, the second controller 125 may operate according to an interface protocol defined in the Universal Flash Storage (UFS) specification. In this embodiment, when the first electronic device 110 is a host, the first controller 115 may operate according to an interface protocol defined in the UFSHCI (UFS Host Controller Interface) specification. However, the present invention is not limited to the above embodiments. As another embodiment, when the second electronic device 120 is an image sensor, the second controller 125 may operate according to an interface protocol called a camera serial interface (CSI). The present invention can be employed in all interface circuits including a plurality of transmitters, and embodiments of the present invention can be changed or modified in various forms according to an interfacing method.

FIG. 2 is a conceptual diagram illustrating a connection between interface circuits included in each of two electronic devices of FIG. 1. As mentioned in the description of FIG. 1, the electronic system 100 may include a first electronic device 110 and a second electronic device 120 connected to each other.

The first electronic device 110 may be connected to the second electronic device 120 through the first physical layer PL1. The second electronic device 120 may be connected to the first electronic device 110 through the second physical layer PL2. Each of the first physical layer PL1 and the second physical layer PL2 may include a transmission circuit and a reception circuit. The transmission circuit may include a plurality of transmitters Tx. The receiving circuit may include one or more receivers Rx.

The number of transmitters Tx and receivers Rx included in the first physical layer PL1 may be variously changed according to the type or type of the first electronic device 110. The number of transmitters Tx and receivers Rx included in the second physical layer PL2 may be variously changed according to the type or type of the second electronic device 120. When the first electronic device 110 and the second electronic device 120 are different types of electronic devices, the number of transmitters Tx and Rx included in the first physical layer PL1 is the second physical device. It may be different from the number of transmitters Tx and receivers Rx included in the layer PL2. However, the configuration shown in FIG. 2 is only an example to aid understanding of the present invention. The present invention is not limited by the configuration shown in FIG. 2.

The transmitter Tx and the receiver Rx connected to each other may form one lane. The transmitter Tx may transmit signals and data to a receiver Rx connected thereto. The receiver Rx may receive signals and data from the transmitter Tx connected thereto. However, the transmitter Tx not connected to the receiver Rx and the receiver Rx not connected to the transmitter Tx may not operate or may not be used. The configuration of the transmission circuit according to the embodiment of the present invention is referred to together with the description of FIGS. 3 to 7.

3 is a block diagram showing the configuration of a transmission circuit according to an embodiment of the present invention. The transmission circuit 200 may include a common clock block 210 and a transmission block 220.

The common clock block 210 may output an operation clock signal opCLK. The operational clock signal opCLK can be used to serialize parallel data. Furthermore, the common clock block 210 may output a symbol clock signal symCLK. The symbol clock signal symCLK may be used to extract data in units of symbols. The symbol clock signal symCLK may be generated by dividing (Divide) the operating clock signal opCLK.

The transmission block 220 may include a plurality of transmitters Tx1 and Tx2. In FIG. 3, the transmission block 220 is shown to include two transmitters Tx1 and Tx2, but the two transmitters Tx1 and Tx2 are for convenience of description and are not intended to limit the present invention. . The number of transmitters included in the transmission block 220 may be changed as necessary.

Each of the plurality of transmitters Tx1 and Tx2 may receive a common operating clock signal opCLK output from the common clock block 210. Furthermore, each of the plurality of transmitters Tx1 and Tx2 may receive a symbol clock signal symCLK output from the common clock block 210 in common. Each of the plurality of transmitters Tx1 and Tx2 may operate based on an operation clock signal opCLK and a symbol clock signal symCLK.

The symbol unit is a unit constituting meaningful or usable data. Symbol units may be configured to have different lengths as needed. For example, when 8b/10b encoding is used to configure meaningful or usable data, each of the plurality of transmitters Tx1 and Tx2 may process and manage 10-bit data. In this example, data in units of symbols may have a length of 10 bits. Further, the symbol clock signal symCLK may be divided to have a period of 10 times the period of the operation clock signal opCLK. However, this example is intended to aid understanding of the present invention and is not intended to limit the present invention. As an embodiment, if data in a symbol unit has a length of N bits, the period of the symbol clock signal symCLK may be N times the period of the operation clock signal opCLK (where, N is a positive integer).

Each of the plurality of transmitters Tx1 and Tx2 may receive original data. For example, the first transmitter Tx1 may receive the first original data, and the second transmitter Tx2 may receive the second original data. Each of the plurality of transmitters Tx1 and Tx2 may extract symbol-unit data from the original data based on the symbol clock signal symCLK. Each of the plurality of transmitters Tx1 and Tx2 may generate parallel data based on the extracted symbol-unit data.

Each of the plurality of transmitters Tx1 and Tx2 may serialize parallel data based on the operation clock signal opCLK. Each of the plurality of transmitters Tx1 and Tx2 may output serialized data. For example, the first transmitter Tx1 may output first serialized data, and the second transmitter Tx2 may output second serialized data. The configuration and operation of each of the plurality of transmitters Tx1 and Tx2 will be further referred to with descriptions of FIGS.

According to an embodiment of the present invention, each of the plurality of transmitters Tx1 and Tx2 may receive a common clock signal. In particular, each of the plurality of transmitters Tx1 and Tx2 may receive a common operation clock signal opCLK as well as a common symbol clock signal symCLK. Thus, for example, a clock signal provided to the first transmitter Tx1 may be synchronized with the clock signal provided to the second transmitter Tx2. That is, according to an embodiment of the present invention, clock signals provided to the plurality of transmitters Tx1 and Tx2, respectively, may be synchronized in the same manner. As a result, timing of data transmission may not be skewed between lanes respectively corresponding to the plurality of transmitters Tx1 and Tx2. The effect obtained by the embodiment of the present invention is further mentioned with the description of FIGS. 8 and 9.

As an embodiment, when the transmission circuit 200 is implemented in a mobile electronic system, the transmission block 220 may be included in a physical layer defined based on the M-PHY specification proposed by the MIPI association. However, the present invention is not limited to this embodiment. As another embodiment, the transmission block 220 may be included in a physical layer defined based on a Peripheral Component Interconnect Express (PCIe) interface protocol. The present invention can be employed in any interface circuit including a plurality of transmitters.

Each of the plurality of transmitters Tx1 and Tx2 may operate independently using an operating power source. For example, the first transmitter Tx1 may operate independently regardless of whether the second transmitter Tx2 operates. Among the plurality of transmitters Tx1 and Tx2, the operation of one transmitter may not affect the operation of the other transmitter. The independent operation of each of the plurality of transmitters Tx1 and Tx2 is further referred to with the description of FIGS. 4 and 6. By outputting data through each of the plurality of transmitters Tx1 and Tx2, more data can be transmitted to the receiving circuit.

4 is a block diagram showing a plurality of transmitters according to an embodiment of the present invention. As mentioned in the description of FIG. 3, the transmission block 220 may include a plurality of transmitters Tx1 and Tx2. In FIG. 4, the transmission block 220 is illustrated as including two transmitters Tx1 and Tx2, but this is for convenience of description and is not intended to limit the present invention. The number of transmitters included in the transmission block 220 may be changed as necessary.

As mentioned above, each of the plurality of transmitters Tx1 and Tx2 can operate independently. For example, the first transmitter Tx1 may operate independently regardless of whether the second transmitter Tx2 operates. Among the plurality of transmitters Tx1 and Tx2, the operation of one transmitter may not affect the operation of the other transmitter.

In an embodiment, the plurality of transmitters Tx1 and Tx2 may receive lane reset signals RST1 and RST2, respectively. For example, the first transmitter Tx1 may receive the first lane reset signal RST1, and the second transmitter Tx2 may receive the second lane reset signal RST2. That is, the lane reset signals RST1 and RST2 may be independently provided to the plurality of transmitters Tx1 and Tx2, respectively.

The first lane reset signal RST1 may be used to reset a state of a lane corresponding to the first transmitter Tx1. The second lane reset signal RST1 may be used to reset a state of a lane corresponding to the second transmitter Tx2. That is, the lane reset signals RST1 and RST2 may be used to reset states of lanes corresponding to the plurality of transmitters Tx1 and Tx2, respectively.

A transmitter that has received a lane reset signal among the plurality of transmitters Tx1 and Tx2 may temporarily stop operation for state initialization. Transmitters that have received a lane reset signal can resume operation after state initialization. As an embodiment, when one of the plurality of transmitters Tx1 and Tx2 generates an error, a state of a lane corresponding to the transmitter that caused the error may be reset based on the lane reset signal. Accordingly, data can be properly transmitted.

As an embodiment, the plurality of transmitters Tx1 and Tx2 may receive power down signals PD1 and PD2, respectively. For example, the first transmitter Tx1 may receive the first power down signal PD1, and the second transmitter Tx2 may receive the second power down signal PD2. That is, the power down signals PD1 and PD2 may be independently provided to the plurality of transmitters Tx1 and Tx2, respectively.

The first power down signal PD1 may be used to stop the operation of the first transmitter Tx1. The second power down signal PD2 may be used to stop the operation of the second transmitter Tx2. That is, the power-down signals PD1 and PD2 may be used to stop the operation of the plurality of transmitters Tx1 and Tx2, respectively.

A transmitter receiving a power down signal among the plurality of transmitters Tx1 and Tx2 may stop operating. The transmitter that has been provided with the power down signal can resume operation after the power down signal is released. As an embodiment, if one of the plurality of transmitters Tx1 and Tx2 is not connected to the receiving circuit, the transmitter not connected to the receiving circuit may stop operating based on the power down signal. As an embodiment, if one of the plurality of transmitters Tx1 and Tx2 does not output data and is in an idle state, the idle transmitter may stop the operation based on a power down signal. Accordingly, power consumed by the plurality of transmitters Tx1 and Tx2 can be minimized.

Each of the plurality of transmitters Tx1 and Tx2 may operate independently based on a lane reset signal and a power down signal. For example, when the first transmitter Tx1 receives the first lane reset signal RST1, the second transmitter Tx2 may or may not receive the second lane reset signal RST2. For example, when the second transmitter Tx2 receives the second power down signal PD2, the first transmitter Tx1 may or may not receive the first power down signal PD1. Whether one of the plurality of transmitters Tx1 and Tx2 receives a lane reset signal or a power down signal may be independent of whether another transmitter receives a lane reset signal or a power down signal. Accordingly, each of the plurality of transmitters Tx1 and Tx2 can operate independently.

Among the plurality of transmitters Tx1 and Tx2, a transmitter not provided with a lane reset signal and a power down signal may operate. On the other hand, a transmitter receiving at least one of a lane reset signal and a power down signal among the plurality of transmitters Tx1 and Tx2 may stop the operation. The transmitter receiving the lane reset signal may temporarily stop the operation to reset the state of the lane, and the transmitter receiving the power down signal may stop the operation to reduce power consumption. However, as mentioned above, each of the plurality of transmitters Tx1 and Tx2 can operate independently. For example, even if the second transmitter Tx2 is provided with the second lane reset signal RST2 or the second power down signal PD2 and stops operation, the first transmitter Tx1 may still operate.

As an embodiment, a transmitter that continues to operate without receiving a lane reset signal and a power-down signal among the plurality of transmitters Tx1 and Tx2 may receive an operation clock signal opCLK and a symbol clock signal symCLK. On the other hand, a transmitter that has stopped operating after receiving at least one of a lane reset signal and a power down signal among the plurality of transmitters Tx1 and Tx2 may not receive the operation clock signal opCLK and the symbol clock signal symCLK. This embodiment is further referred to with the description of FIG. 6.

As each of the plurality of transmitters Tx1 and Tx2 operates independently, times at which the plurality of transmitters Tx1 and Tx2 start operation may be different from each other. However, as mentioned in the description of FIG. 3, each of the plurality of transmitters Tx1 and Tx2 may receive an operation clock signal opCLK and a symbol clock signal symCLK in common.

Accordingly, even if the time when one transmitter starts operation is different from the time when the other transmitter starts operation, the two transmitters can be provided with the same symbol clock signal symCLK. As an example, even if the first time when the first transmitter Tx1 starts operating is different from the second time when the second transmitter Tx2 starts operation, the symbol clock signal symCLK provided to the first transmitter Tx1 is It may be synchronized with the symbol clock signal symCLK provided to the second transmitter Tx2. The identically synchronized symbol clock signals symCLK are further referred to with the description of FIG. 9.

5 is a block diagram showing the configuration of a transmission circuit according to an embodiment of the present invention. The transmission circuit 300 may include a common clock block 310 and a transmission block 320.

The common clock block 310 may include an operational clock generator 312 and a clock divider 314. The transmission block 320 may include a plurality of transmitters Tx1 and Tx2. In FIG. 5, although the transmission block 320 is shown to include two transmitters Tx1 and Tx2, the two transmitters Tx1 and Tx2 are for convenience of description and are not intended to limit the present invention. . The number of transmitters included in the transmission block 320 may be changed as necessary.

The operational clock generator 312 may be configured to generate an operational clock signal opCLK. The operational clock signal opCLK can be used to serialize parallel data. The operation clock signal opCLK may be commonly provided to each of the plurality of transmitters Tx1 and Tx2. As an embodiment, the operational clock generator 312 may include a PLL (Phase Locked Loop) circuit, but the present invention is not limited to this embodiment. The operational clock generator 312 can have any configuration for generating a clock signal having a specific frequency.

The clock divider 314 may receive an operation clock signal opCLK. The clock divider 314 may be configured to generate a symbol clock signal symCLK. The symbol clock signal symCLK may be used to extract data in units of symbols. The symbol clock signal symCLK may be generated by dividing the operating clock signal opCLK. The symbol clock signal symCLK may be commonly provided to each of the plurality of transmitters Tx1 and Tx2.

Each of the plurality of transmitters Tx1 and Tx2 may receive original data. Each of the plurality of transmitters Tx1 and Tx2 may be configured to serially output data. Each of the plurality of transmitters Tx1 and Tx2 may receive a common operating clock signal opCLK generated by the operating clock generator 312. Further, each of the plurality of transmitters Tx1 and Tx2 may receive a symbol clock signal symCLK generated by the clock divider 314 in common. Each of the plurality of transmitters Tx1 and Tx2 may operate based on an operation clock signal opCLK and a symbol clock signal symCLK.

As mentioned above, symbol units are units that make up meaningful or usable data. Symbol units may be configured to have different lengths as needed. For example, the symbol unit may have a bit length of data processed in the transmission block 320. As an embodiment, if data in a symbol unit has a length of N bits, the period of the symbol clock signal symCLK may be N times the period of the operation clock signal opCLK (where, N is a positive integer).

As an embodiment, the first transmitter Tx1 may include a first serializer 321, a first digital logic 323, and a first driver 325. However, the first transmitter Tx1 may further include other components not shown in FIG. 5. 5 is for helping understanding of the present invention, not for limiting the present invention.

The first serializer 321 may receive an operation clock signal opCLK and a symbol clock signal symCLK. The first serializer 321 may receive first parallel data in synchronization with the symbol clock signal symCLK. The first parallel data may be provided from the first digital logic 323. Furthermore, the first serializer 321 may serialize the first parallel data in synchronization with the operation clock signal opCLK. The first serializer 321 may serialize the first parallel data to generate first serial data. The first serializer 321 may provide first serial data to the first driver 325.

The first digital logic 323 may receive the first original data. The original data is data including information to be transmitted from the transmission circuit 300 to a reception circuit (not shown). The original data may be provided from other components of the electronic device including the transmission circuit 300. The first digital logic 323 may extract data in units of symbols from the first original data based on the symbol clock signal symCLK. As an embodiment, the first digital logic 323 may receive a symbol clock signal symCLK through the first serializer 321. The first digital logic 323 may generate first parallel data based on the extracted data in units of symbols. The first digital logic 323 may provide the first parallel data to the first serializer 321.

The first driver 325 may receive first serial data from the first serializer 321. The first driver 325 may output first serial data. The first serial data output from the first driver 325 may be transmitted to a receiving circuit connected to the transmitting circuit 300.

As an embodiment, the second transmitter Tx2 may include a second serializer 322, a second digital logic 324, and a second driver 326. The second serializer 322, the second digital logic 324, and the second driver 326 are similar to the first serializer 321, the first digital logic 323, and the first driver 325, respectively. It is structured and can operate in the same way. When the transmission block 320 includes three or more transmitters, other transmitters included in the transmission block 320 are configured similarly to the first transmitter (Tx1) (or the second transmitter (Tx2)) and in the same manner. Can work. Redundant descriptions are omitted.

According to an embodiment of the present invention, each of the plurality of transmitters Tx1 and Tx2 may receive a common clock signal. In particular, each of the plurality of transmitters Tx1 and Tx2 may receive a common operation clock signal opCLK as well as a common symbol clock signal symCLK. Thus, for example, a clock signal provided to the first transmitter Tx1 may be synchronized with the clock signal provided to the second transmitter Tx2. That is, according to an embodiment of the present invention, clock signals provided to the plurality of transmitters Tx1 and Tx2, respectively, may be synchronized in the same manner. As a result, the timing of data transmission may not be shifted between lanes respectively corresponding to the plurality of transmitters Tx1 and Tx2. The effect obtained by the embodiment of the present invention is further mentioned with the description of FIGS. 8 and 9.

As an embodiment, when the transmission circuit 300 is implemented in a mobile electronic system, the transmission block 320 may be included in a physical layer defined based on the M-PHY specification proposed by the MIPI association. However, the present invention is not limited to this embodiment. As another embodiment, the transmission block 320 may be included in a physical layer defined based on the PCIe interface protocol. The present invention can be employed in any interface circuit including a plurality of transmitters.

Each of the plurality of transmitters Tx1 and Tx2 may operate independently using an operating power source. For example, the first transmitter Tx1 may operate independently regardless of whether the second transmitter Tx2 operates. Among the plurality of transmitters Tx1 and Tx2, the operation of one transmitter may not affect the operation of the other transmitter. The independent operation of each of the plurality of transmitters Tx1 and Tx2 is further referred to with the description of FIG. 6. By outputting data through each of the plurality of transmitters Tx1 and Tx2, more data can be transmitted to the receiving circuit.

6 is a conceptual diagram showing the configuration of a plurality of transmitters according to an embodiment of the present invention. As mentioned in the description of FIG. 5, the transmission block 320 may include a plurality of transmitters Tx1 and Tx2. In FIG. 6, the transmission block 320 is illustrated as including two transmitters Tx1 and Tx2, but this is for convenience of description and is not intended to limit the present invention. The number of transmitters included in the transmission block 320 may be changed as necessary.

A description of the configuration and function of the first serializer 321, the first digital logic 323, and the first driver 325 has been mentioned along with the description of FIG. 5. Redundant descriptions are omitted. Further, a description of the configuration and function of the second serializer 322, the second digital logic 324, and the second driver 326 is omitted.

As mentioned above, each of the plurality of transmitters Tx1 and Tx2 can operate independently. For example, the first transmitter Tx1 may operate independently regardless of whether the second transmitter Tx2 operates. Among the plurality of transmitters Tx1 and Tx2, the operation of one transmitter may not affect the operation of the other transmitter.

As an embodiment, the lane reset signals RST1 and RST2 may be provided to the plurality of transmitters Tx1 and Tx2, respectively. For example, the first lane reset signal RST1 may be provided to the first transmitter Tx1, and the second lane reset signal RST1 may be provided to the second transmitter Tx2. That is, the lane reset signals RST1 and RST2 may be independently provided to the plurality of transmitters Tx1 and Tx2, respectively.

As an embodiment, the lane reset signals RST1 and RST2 may be provided from a controller or processor included in the transmission circuit 300 (refer to FIG. 5) or configured separately from the transmission circuit 300. As another embodiment, the lane reset signals RST1 and RST2 may be provided from an electronic device including the transmission circuit 300 or another electronic device or system connected to the system. As another embodiment, the lane reset signals RST1 and RST2 may be provided from a user of an electronic device or system including the transmission circuit 300. However, the present invention is not limited to the above embodiments.

The first lane reset signal RST1 may be used to reset a state of a lane corresponding to the first transmitter Tx1. The second lane reset signal RST1 may be used to reset a state of a lane corresponding to the second transmitter Tx2. That is, the lane reset signals RST1 and RST2 may be used to reset states of lanes corresponding to the plurality of transmitters Tx1 and Tx2, respectively.

A transmitter that has received a lane reset signal among the plurality of transmitters Tx1 and Tx2 may temporarily stop operating to initialize a state. Transmitters that have received a lane reset signal can resume operation after state initialization. As an embodiment, when one of the plurality of transmitters Tx1 and Tx2 generates an error, a state of a lane corresponding to the transmitter that caused the error may be reset based on the lane reset signal. Accordingly, data can be properly transmitted.

As an embodiment, the power down signals PD1 and PD2 may be provided to a plurality of transmitters Tx1 and Tx2, respectively. For example, the first power down signal PD1 may be provided to the first transmitter Tx1, and the second power down signal PD2 may be provided to the second transmitter Tx2. That is, the power down signals PD1 and PD2 may be independently provided to the plurality of transmitters Tx1 and Tx2, respectively.

As an embodiment, the power down signals PD1 and PD2 may be provided from a controller or a processor included in the transmission circuit 300 or configured separately from the transmission circuit 300. As another embodiment, the power down signals PD1 and PD2 may be provided from an electronic device including the transmission circuit 300 or another electronic device or system connected to the system. As another embodiment, the power down signals PD1 and PD2 may be provided from a user of an electronic device or system including the transmission circuit 300. However, the present invention is not limited to the above embodiments.

The first power down signal PD1 may be used to stop the operation of the first transmitter Tx1. The second power down signal PD2 may be used to stop the operation of the second transmitter Tx2. That is, the power-down signals PD1 and PD2 may be used to stop the operation of the plurality of transmitters Tx1 and Tx2, respectively.

A transmitter receiving a power down signal among the plurality of transmitters Tx1 and Tx2 may stop operating. The transmitter that has been provided with the power down signal can resume operation after the power down signal is released. As an embodiment, if one of the plurality of transmitters Tx1 and Tx2 is not connected to the receiving circuit, the transmitter not connected to the receiving circuit may stop operating based on the power down signal. As an embodiment, if one of the plurality of transmitters Tx1 and Tx2 is in an idle state without outputting data, the idle transmitter may stop the operation based on the power down signal. Accordingly, power consumed by the plurality of transmitters Tx1 and Tx2 can be minimized.

Each of the plurality of transmitters Tx1 and Tx2 may operate independently based on a lane reset signal and a power down signal. For example, when the first transmitter Tx1 receives the first lane reset signal RST1, the second transmitter Tx2 may or may not receive the second lane reset signal RST2. For example, when the second transmitter Tx2 receives the second power down signal PD2, the first transmitter Tx1 may or may not receive the first power down signal PD1. Whether one of the plurality of transmitters Tx1 and Tx2 receives a lane reset signal or a power down signal may be independent of whether another transmitter receives a lane reset signal or a power down signal. Accordingly, each of the plurality of transmitters Tx1 and Tx2 can operate independently.

As an embodiment, the first transmitter Tx1 may include a first signal providing logic 331. The first lane reset signal RST1 and the first power down signal PD1 may be provided to the first signal providing logic 331. As an embodiment, the first signal providing logic 331 may include a NOR gate.

In the above embodiment, when both the logical value corresponding to the first lane reset signal RST1 and the logical value corresponding to the first power down signal PD1 correspond to logic "0", the first signal providing logic 331 The output of the NOR gate of) may correspond to a logic "1". On the other hand, when at least one of a logic value corresponding to the first lane reset signal RST1 and a logic value corresponding to the first power down signal PD1 corresponds to a logic "1", the first signal providing logic 331 The output of the NOR gate of may correspond to a logic "0". However, the first signal providing logic 331 may have a different configuration. The above examples are only examples to aid understanding of the present invention, and are not intended to limit the present invention.

As an embodiment, the first transmitter Tx1 may include a first operating clock buffer 333. The first operating clock buffer 333 may transmit the operating clock signal opCLK to the first serializer 321. The first operating clock buffer 333 may or may not operate according to the output of the first signal providing logic 331. For example, when the output of the first signal providing logic 331 corresponds to the logic "1", the first operating clock buffer 333 operates and the operating clock signal opCLK is transmitted to the first serializer 321 Can be. For example, when the output of the first signal providing logic 331 corresponds to the logic "0", the first operating clock buffer 333 does not operate and the operating clock signal opCLK is transferred to the first serializer 321 May not be delivered.

That is, the first operation clock buffer 333 may or may not operate depending on whether the first lane reset signal RST1 and the first power down signal PD1 are provided. When the first lane reset signal RST1 and the first power down signal PD1 are not provided, the first operation clock buffer 333 may transmit the operation clock signal opCLK to the first serializer 321. . On the other hand, when at least one of the first lane reset signal RST1 and the first power down signal PD1 is provided, the first operation clock buffer 333 transfers the operation clock signal opCLK to the first serializer 321 May not be delivered.

As an embodiment, the first transmitter Tx1 may include a first symbol clock buffer 335. The first symbol clock buffer 335 may transmit the symbol clock signal symCLK to the first serializer 321. The first symbol clock buffer 335 may or may not operate according to the output of the first signal providing logic 331. For example, when the output of the first signal providing logic 331 corresponds to the logic "1", the first symbol clock buffer 335 operates and the symbol clock signal symCLK is transmitted to the first serializer 321 Can be. For example, when the output of the first signal providing logic 331 corresponds to the logic "0", the first symbol clock buffer 335 is not operated and the symbol clock signal symCLK is transferred to the first serializer 321. May not be delivered.

That is, the first symbol clock buffer 335 may or may not operate depending on whether the first lane reset signal RST1 and the first power down signal PD1 are provided. When the first lane reset signal RST1 and the first power down signal PD1 are not provided, the first symbol clock buffer 335 may transmit the symbol clock signal symCLK to the first serializer 321. . On the other hand, when at least one of the first lane reset signal RST1 and the first power down signal PD1 is provided, the first symbol clock buffer 335 converts the symbol clock signal symCLK to the first serializer 321 May not be delivered.

As an embodiment, the second transmitter Tx2 may include a second signal providing logic 332, a second operation clock buffer 334, and a second symbol clock buffer 336. The second signal providing logic 332, the second working clock buffer 334, and the second symbol clock buffer 336 are respectively a first signal providing logic 331, a first working clock buffer 333, and a first It is configured similarly to the symbol clock buffer 335 and can operate in the same manner. Redundant descriptions are omitted.

As mentioned above, each of the plurality of transmitters Tx1 and Tx2 can operate independently. As an embodiment, a transmitter that is not provided with a lane reset signal and a power down signal among the plurality of transmitters Tx1 and Tx2 may receive an operation clock signal opCLK and a symbol clock signal symCLK and continue to operate. On the other hand, a transmitter receiving at least one of a lane reset signal and a power down signal among the plurality of transmitters Tx1 and Tx2 may stop operation without being provided with an operation clock signal opCLK and a symbol clock signal symCLK.

As each of the plurality of transmitters Tx1 and Tx2 operates independently, times at which the plurality of transmitters Tx1 and Tx2 start operation may be different from each other. However, as mentioned in the description of FIG. 5, each of the plurality of transmitters Tx1 and Tx2 may receive an operation clock signal opCLK and a symbol clock signal symCLK in common.

Accordingly, even if the time when one transmitter starts operation is different from the time when the other transmitter starts operation, the two transmitters can be provided with the same symbol clock signal symCLK. As an example, even if the first time when the first transmitter Tx1 starts operating is different from the second time when the second transmitter Tx2 starts operation, the symbol clock signal symCLK provided to the first transmitter Tx1 is It may be synchronized with the symbol clock signal symCLK provided to the second transmitter Tx2. The identically synchronized symbol clock signals symCLK are further referred to with the description of FIG. 9.

7 is a block diagram showing the configuration of a transmitter according to an embodiment of the present invention. The first transmitter Tx1 may include a first serializer 321, a first digital logic 323, and a first driver 325. A description of the configuration and function of the first serializer 321, the first digital logic 323, and the first driver 325 has been mentioned in the description of FIG. 5. Redundant descriptions are omitted.

As an embodiment, the first serializer 321 may include a latch 341 and a multiplexer 343. In this embodiment, the operation clock signal opCLK transmitted to the first serializer 321 may be provided to the multiplexer 343. In this embodiment, the symbol clock signal symCLK transmitted to the first serializer 321 may be provided to the latch 341. Further, as an embodiment, the symbol clock signal symCLK may be provided to the first digital logic 323 through the first serializer 321.

The latch 341 may receive first parallel data from the first digital logic 323. The first digital logic 323 may extract data in symbol units from the first original data based on the symbol clock signal symCLK and output first parallel data. The latch 341 may receive first parallel data in synchronization with the symbol clock signal symCLK.

The multiplexer 343 may receive first parallel data from the latch 341. The multiplexer 343 may serialize the first parallel data to generate first serial data. The multiplexer 343 may serialize the first parallel data in synchronization with the operation clock signal opCLK. The multiplexer 343 may provide first serial data to the first driver 325.

However, the configuration of the first serializer 321 shown in FIG. 7 is only an example to aid understanding of the present invention. The first serializer 321 may have a configuration different from that shown in FIG. 7. The first serializer 321 may have any configuration as long as it is a configuration for serializing parallel data. Furthermore, the first serializer 321 may further include other components not shown in FIG. 7. The invention is not limited by FIG. 7.

The second transmitter Tx2 (see FIG. 5) may be configured similarly to the first transmitter Tx1 and operated in the same manner. When the transmission block 320 (refer to FIG. 5) includes three or more transmitters, other transmitters included in the transmission block 320 are configured similarly to the first transmitter (Tx1) (or the second transmitter (Tx2)). And it can work the same way. Redundant descriptions are omitted.

8 is a timing diagram showing a case where the timing of data transmission is shifted between lanes corresponding to a plurality of transmitters, respectively. FIG. 8 shows a case where the common clock block 210 (see FIG. 3) or the common clock block 310 (see FIG. 5) according to an embodiment of the present invention is not used.

The first symbol clock signal symCLK1 and the second symbol clock signal symCLK2 may be generated by dividing the operation clock signal opCLK. For example, the first symbol clock signal symCLK1 is a first transmitter (Tx1, see FIG. 3) included in the transmission circuit 200 (refer to FIG. 3) or a first transmitter included in the transmission circuit 300 (see FIG. 5). It is a symbol clock signal provided as (Tx1, see Fig. 5). For example, the second symbol clock signal symCLK2 is transmitted to a second transmitter (Tx2, see FIG. 3) included in the transmission circuit 200 or a second transmitter (Tx2, see FIG. 5) included in the transmission circuit 300. It is a symbol clock signal provided.

First parallel data and second parallel data may be generated and transmitted based on the first symbol clock signal symCLK1 and the second symbol clock signal symCLK2, respectively. In FIG. 8, it is shown that the period of each of the first symbol clock signal symCLK1 and the second symbol clock signal symCLK2 is 10 times the period of the operation clock signal opCLK. However, FIG. 8 is intended to aid understanding of the present invention and is not intended to limit the present invention. As an embodiment, when data in units of symbols has a length of N bits, a period of each of the first symbol clock signal symCLK1 and the second symbol clock signal symCLK2 may be N times the period of the operation clock signal opCLK. (However, N is a positive integer).

As mentioned above, each of the plurality of transmitters Tx1 and Tx2 included in the transmission circuit 200 or each of the plurality of transmitters Tx1 and Tx2 included in the transmission circuit 300 may operate independently. For example, a time when the first transmitter Tx1 starts to operate may be different from a time when the second transmitter Tx2 starts to operate. Among the plurality of transmitters Tx1 and Tx2, the operation of one transmitter may not affect the operation of the other transmitter.

For example, from time't1', the first transmitter Tx1 may not receive the first power down signal PD1. The first transmitter Tx1 may start operation from time't1'. For example, from time't2', the second transmitter Tx2 may not receive the second power down signal PD2. The second transmitter Tx2 may start operation from time't2'.

However, if the common clock block 210 or the common clock block 310 according to an embodiment of the present invention is not used, the time at which the first transmitter Tx1 starts to receive the first symbol clock signal symCLK1 (ie , For example, the time't1' may be different from the time when the second transmitter Tx2 starts to receive the second symbol clock signal symCLK2 (ie, for example, the time't2'). In this case, the first symbol clock signal symCLK1 may not be synchronized with the second symbol clock signal symCLK2. As an example, in FIG. 8, a time difference of'ts' occurs between the first symbol clock signal symCLK1 and the second symbol clock signal symCLK2. As a result, a delay of'ts' occurs between the time at which the first parallel data is generated and transmitted and the time at which the second parallel data is generated and transmitted.

If the first symbol clock signal symCLK1 is not synchronized with the second symbol clock signal symCLK2, the time at which the first serial data is generated and output may be different from the time at which the second serial data is generated and output. Accordingly, the timing of data transmission may be shifted between the lane corresponding to the first transmitter Tx1 and the lane corresponding to the second transmitter Tx2. If the timing of data transmission is shifted between lanes respectively corresponding to the plurality of transmitters Tx1 and Tx2, an error may occur in data transmission.

9 is a timing diagram showing an effect obtained by an embodiment of the present invention. Unlike FIG. 8, FIG. 9 shows a case in which a common clock block 210 (see FIG. 3) or a common clock block 310 (see FIG. 5) according to an embodiment of the present invention is used.

As in the example of FIG. 8, from time't1', the first transmitter Tx1 may not receive the first power down signal PD1. The first transmitter Tx1 may start operation from time't1'. Furthermore, from time't2', the second transmitter Tx2 may not receive the second power down signal PD2. The second transmitter Tx2 may start operation from time't2'.

However, when the common clock block 210 or the common clock block 310 according to an embodiment of the present invention is used, the time when the first transmitter Tx1 starts to operate is the second transmitter Tx2 starts to operate. Even if different from the time, the first symbol clock signal symCLK1 provided to the first transmitter Tx1 may be synchronized with the second symbol clock signal symCLK2 provided to the second transmitter Tx2. This is because each of the plurality of transmitters Tx1 and Tx2 receives the common clock block 210 or the symbol clock signal symCLK generated by the common clock block 310 according to an exemplary embodiment of the present invention.

As a result, the time at which the first parallel data is generated and transmitted may be the same as the time at which the second parallel data is generated and transmitted. Accordingly, the time at which the first serial data is generated and output may be the same as the time at which the second serial data is generated and output. Accordingly, the timing of data transmission may not be shifted between the lane corresponding to the first transmitter Tx1 and the lane corresponding to the second transmitter Tx2. According to an embodiment of the present invention, since the timing of data transmission is not shifted between lanes corresponding to the plurality of transmitters (Tx1, Tx2), an error does not occur in data transmission and It can be transmitted stably through.

8 and 9, when the first power down signal PD1 and the second power down signal PD2 have a value corresponding to a logic "0", the first transmitter Tx1 and the second transmitter Tx2 are Was supposed to work. However, the logic values of the first power down signal PD1 and the second power down signal PD2 for operating the first transmitter Tx1 and the second transmitter Tx2 may be changed or modified as necessary. 8 and 9 are only examples to aid understanding of the present invention and are not intended to limit the present invention.

In the description of FIGS. 8 and 9, the first transmitter Tx1 operates based on the first power down signal PD1 and the second transmitter Tx2 operates based on the second power down signal PD2. The case has been described. However, the first transmitter (Tx1) operates based on the first lane reset signal (RST1, see FIG. 5) and the second transmitter (Tx2) operates based on the second lane reset signal (RST2, see FIG. 5). In this case, even when the first transmitter Tx1 operates based on the first lane reset signal RST1 and the second transmitter Tx2 operates based on the second power down signal PD2, FIGS. 8 and 9 A description in a similar context to the description of can be applied.

In the description of FIGS. 8 and 9, two transmitters included in a plurality of transmitters are mentioned. However, as described above, the number of transmitters included in the plurality of transmitters may be changed as necessary. When a plurality of transmitters includes three or more transmitters, a description in a context similar to that of FIGS. 8 and 9 may be applied to each of the three or more transmitters.

10 is a block diagram showing the configuration of a storage system according to an embodiment of the present invention. The storage system 400 may include a host 410 and a storage device 420.

For example, the host 410 may be the first electronic device 110 of FIG. 1. As an embodiment, when the storage system 400 is implemented in a mobile electronic system, the host 410 may include an application processor.

For example, the storage device 420 may be the second electronic device 120 of FIG. 1. The storage device 420 may include a memory controller 421, a nonvolatile memory 423, and an interface circuit 425. The interface circuit 425 may include a physical layer (PL). However, the storage device 420 may further include other components not shown in FIG. 10. The configuration shown in FIG. 10 is only an example to aid understanding of the present invention.

The memory controller 421 may manage and control the overall operation of the storage device 420. In particular, the memory controller 421 may process and manage data exchanged with the host 410 through the interface circuit 425. Under the control of the memory controller 421, the storage device 420 may perform its own function.

As an embodiment, the memory controller 421 may control the storage device 420 according to a power down signal PD, a lane reset signal RST, a reference clock signal rCLK, etc. provided through the interface circuit 425. . As an example, the reference clock signal rCLK may be referenced to generate an operational clock signal opCLK (see FIG. 5). As an embodiment, the memory controller 421 may store the data DAT provided from the host 410 through the interface circuit 425 in the nonvolatile memory 423. Alternatively, the memory controller 421 may provide the data DAT stored in the nonvolatile memory 423 to the host 410 through the interface circuit 425.

As an embodiment, the memory controller 421 may control the storage device 420 according to the UFS interface protocol, but the present invention is not limited to this embodiment. As an example, the memory controller 421 is USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCIe, M-PCIe (Mobile PCIe), ATA (Advanced Technology Attachment), PATA (Parallel ATA), SATA (Serial The storage device 420 may be controlled according to one or more of various interface protocols such as ATA), Serial Attached SCSI (SAS), and Integrated Drive Electronics (IDE).

The nonvolatile memory 423 may store data regardless of whether power is supplied or not. The nonvolatile memory 423 may store data under the control of the memory controller 421. Alternatively, the nonvolatile memory 423 may output data under the control of the memory controller 421.

The interface circuit 425 according to an embodiment of the present invention may include a physical layer (PL). The interface circuit 425 may operate according to an interface protocol using a physical layer (PL). In particular, the interface circuit 425 may be configured to serially output data stored in the nonvolatile memory 423 through the physical layer PL.

As an embodiment, when the storage device 420 is implemented in a mobile electronic system, the physical layer PL may be defined by the M-PHY specification. However, the present invention is not limited to this embodiment. The physical layer PL may include physical components (eg, a plurality of transmitters and one or more receivers) for exchanging data with the host 410. In particular, a plurality of transmitters included in the physical layer PL of the interface circuit 425 may be implemented based on an embodiment of the present invention.

More specifically, the physical layer PL of the interface circuit 425 may include at least one of the configurations illustrated in FIGS. 3 to 7. When transmitters included in the physical layer PL of the interface circuit 425 are used, the effects mentioned in the description of FIG. 9 can be obtained. Description of the overlapping range is omitted.

As an embodiment, the memory controller 421, the nonvolatile memory 423, and the interface circuit 425 may be implemented in an embedded storage configured to be embedded in a mobile electronic system. As another embodiment, the memory controller 421, the nonvolatile memory 423, and the interface circuit 425 may be implemented in a card storage configured to be connected to a mobile electronic system. However, the present invention is not limited to the above embodiments. The storage device 420 may be implemented as a different type of storage.

11 is a block diagram showing the configuration of an embedded storage according to an embodiment of the present invention. The embedded storage 1000 according to an embodiment of the present invention may include a memory controller 1100, a nonvolatile memory 1200, an external input/output block 1300, and a memory input/output block 1400. . However, the configuration shown in FIG. 11 is only an example to aid understanding of the present invention. The embedded storage 1000 may further include other components not shown in FIG. 11. Alternatively, the embedded storage 1000 may not include one or more of the components illustrated in FIG. 11.

The memory controller 1100 may manage and control the overall operation of the embedded storage 1000. In particular, the memory controller 1100 may process and manage data exchanged with the host through the external input/output block 1300.

As an embodiment, the memory controller 1100 may control the embedded storage 1000 according to a power down signal PD, a lane reset signal RST, and a reference clock signal rCLK provided through the external input/output block 1300. have. As an embodiment, the memory controller 1100 may store data DIN provided from the host through the external input/output block 1300 in the nonvolatile memory 1200 through the memory input/output block 1400. Alternatively, the memory controller 1100 may provide the data DOUT stored in the nonvolatile memory 1200 to the host through the external input/output block 1300.

As an embodiment, the memory controller 1100 may control the embedded storage 1000 according to the UFS interface protocol, but the present invention is not limited to this embodiment. For example, the memory controller 1100 may control the embedded storage 1000 according to one or more of various interface protocols such as USB, SCSI, PCIe, M-PCIe, ATA, PATA, SATA, SAS, and IDE.

The nonvolatile memory 1200 is a memory configured to perform a unique function of the embedded storage 1000. The nonvolatile memory 1200 may store data regardless of whether power is supplied or not. For example, the nonvolatile memory 1200 includes a NAND-type flash memory, a NOR-type flash memory, a phase-change random access memory (PRAM), a magneto-resistive RAM (MRAM), and It may be one of ReRAM (Resistive RAM), FRAM (Ferro-electric RAM), or the like. Alternatively, the nonvolatile memory 1200 may include different types of memories together.

The external input/output block 1300 according to an embodiment of the present invention may exchange signals and data with an external device or system. The external input/output block 1300 may include a physical layer PL. The external input/output block 1300 may operate according to an interface protocol using the physical layer PL. As an embodiment, the external input/output block 1300 may be configured to serially output data stored in the nonvolatile memory 1200 through the physical layer PL.

As an embodiment, when the embedded storage 1000 is implemented in a mobile electronic system, the physical layer PL may be defined by the M-PHY specification. However, the present invention is not limited to this embodiment. The physical layer PL may include a plurality of transmitters Tx and one or more receivers Rx for exchanging data with a host. In particular, a plurality of transmitters Tx included in the physical layer PL of the external input/output block 1300 may be implemented based on an embodiment of the present invention.

More specifically, the physical layer PL of the external input/output block 1300 may include at least one of the configurations illustrated in FIGS. 3 to 7. When the transmitters Tx included in the physical layer PL of the external input/output block 1300 are used, the effects mentioned in the description of FIG. 9 may be obtained. Description of the overlapping range is omitted.

The memory input/output block 1400 may process writing of data to the nonvolatile memory 1200 and reading of data from the nonvolatile memory 1200. For example, the memory input/output block 1400 may include a buffer memory 1420 for temporarily buffering data. Although not shown in FIG. 11, the memory input/output block 1400 may further include other components used for input/output of data, such as an address decoder and a sense amplifier.

12 is a block diagram showing the configuration of a storage system including card storage according to an embodiment of the present invention. The storage system 2000 may include a host 2100 and a card storage 2200.

The host 2100 according to an embodiment of the present invention may include a host controller 2110, a host interface 2120, an application 2130, a device driver 2140, and a buffer memory 2150. However, the configuration of the host 2100 shown in FIG. 12 is only an example to aid understanding of the present invention. The host 2100 may further include other components not shown in FIG. 12. Alternatively, the host 2100 may not include one or more of the elements shown in FIG. 12.

The host controller 2110 may manage and control the overall operation of the host 2100. The host controller 2110 may process and manage data exchanged with the card storage 2200 through the host interface 2120. As an embodiment, the host controller 2110 may control the host 2100 according to the UFSHCI interface protocol, but the present invention is not limited to this embodiment.

The host interface 2120 according to an embodiment of the present invention provides various types of signals (eg, a power down signal (PD), a lane reset signal (RST), a reference clock signal (rCLK), etc.) to the card storage 2200. can do. Furthermore, the host interface 2120 may exchange data (eg, input data (DIN), output data (DOUT), etc.) with the card storage 2200. The host interface 2120 may include a physical layer (PLH). The host interface 2120 may communicate with the card storage 2200 according to an interface protocol using a physical layer (PLH). As an embodiment, the host interface 2120 may serially output signals and data through a physical layer (PLH).

As an embodiment, when the storage system 2000 is implemented in a mobile electronic system, the physical layer PLH may be defined by the M-PHY specification. However, the present invention is not limited to this embodiment. The physical layer PLH may include a plurality of transmitters Tx and one or more receivers Rx for exchanging signals and data with the card storage 2200. In particular, a plurality of transmitters Tx included in the physical layer PLH of the host interface 2120 may be implemented based on an embodiment of the present invention.

More specifically, the physical layer (PLH) of the host interface 2120 may include at least one of the configurations illustrated in FIGS. 3 to 7. When the transmitters Tx included in the physical layer PLH of the host interface 2120 are used, the effects mentioned in the description of FIG. 9 may be obtained. Description of the overlapping range is omitted.

The application 2130 may manage various types of application programs executed in the host 2100. The device driver 2140 may manage and drive peripheral devices connected to the host 2100. In the embodiment of FIG. 12, the device driver 2140 may drive the card storage 2200. The application 2130 and the device driver 2140 may be implemented as program commands, for example, firmware.

The buffer memory 2150 may temporarily buffer data processed by the host 2100. For example, the buffer memory 2150 may include volatile memory such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), or nonvolatile memory such as flash memory, PRAM, MRAM, ReRAM, and FRAM. I can.

The card storage 2200 according to an embodiment of the present invention may include a memory controller 2210, a nonvolatile memory 2220, a storage interface 2230, and a memory input/output block 2240. However, the configuration of the card storage 2200 shown in FIG. 12 is only an example to aid understanding of the present invention. The card storage 2200 may further include other components not shown in FIG. 12. Alternatively, the card storage 2200 may not include one or more of the components shown in FIG. 12.

The memory controller 2210 may manage and control the overall operation of the card storage 2200. The memory controller 2210 may process and manage data exchanged with the host 2100 through the storage interface 2230. As an embodiment, the memory controller 2210 may control the card storage 2200 according to the UFS interface protocol, but the present invention is not limited to this embodiment.

For example, the memory controller 2210 controls the card storage 2200 according to the power down signal PD, the lane reset signal RST, the reference clock signal rCLK, etc. provided from the host 2100 through the storage interface 2230. Can be controlled. As another example, the memory controller 2210 may store data DIN provided from the host 2100 through the storage interface 2230 in the nonvolatile memory 2220 through the memory input/output block 2240. Alternatively, the memory controller 2210 may provide data DOUT stored in the nonvolatile memory 2220 to the host 2100 through the storage interface 2230.

The nonvolatile memory 2220 is a memory configured to perform a unique function of the card storage 2200. The nonvolatile memory 2220 may store data regardless of whether power is supplied or not. For example, the nonvolatile memory 2220 may be one of flash memory, PRAM, MRAM, ReRAM, FRAM, or the like. Alternatively, the nonvolatile memory 2220 may include different types of memories together.

The storage interface 2230 according to an embodiment of the present invention receives various types of signals (eg, a power down signal PD, a lane reset signal RST, a reference clock signal rCLK, etc.) from the host 2100. I can. Furthermore, the storage interface 2230 may exchange data (eg, input data (DIN), output data (DOUT), etc.) with the host 2100. The storage interface 2230 may include a physical layer (PLS). The storage interface 2230 may operate according to an interface protocol using a physical layer (PLS). As an embodiment, the storage interface 2230 may serially output data stored in the nonvolatile memory 2220 through the physical layer PLS.

As an embodiment, when the storage system 2000 is implemented in a mobile electronic system, the physical layer (PLS) may be defined by the M-PHY specification. However, the present invention is not limited to this embodiment. The physical layer PLS may include a plurality of transmitters Tx and one or more receivers Rx for exchanging data with the host 2100. In particular, a plurality of transmitters Tx included in the physical layer PLS of the storage interface 2230 may be implemented based on an embodiment of the present invention.

More specifically, the physical layer PLS of the storage interface 2230 may include at least one of the configurations illustrated in FIGS. 3 to 7. When the transmitters Tx included in the physical layer PLS of the storage interface 2230 are used, the effects mentioned in the description of FIG. 9 may be obtained. Description of the overlapping range is omitted.

The memory input/output block 2240 may process writing of data to the nonvolatile memory 2220 and reading of data from the nonvolatile memory 2220. For example, the memory input/output block 2240 may include a buffer memory 2242 for temporarily buffering data. For example, the buffer memory 2242 may include volatile memory such as SRAM, DRAM, SDRAM, or the like, or nonvolatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM, and the like. Although not shown in FIG. 12, the memory input/output block 2240 may further include other components used for input/output of data, such as an address decoder and a sense amplifier.

11 and 12, the configuration of a storage device implemented based on an embodiment of the present invention has been described. However, as mentioned above, the present invention can be employed in any interface circuit including a plurality of transmitters. 11 and 12 are not intended to limit the present invention.

13 is a block diagram illustrating a configuration of an electronic system including a transmission circuit according to an embodiment of the present invention and interfaces operating according to an embodiment of the present invention. The electronic system 3000 may be implemented as a data processing device that can use or support an interface proposed by the MIPI Alliance. For example, the electronic system 3000 may be implemented in the form of a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a smart phone, or a wearable device.

The electronic system 3000 may include an application processor 3100, a display 3220, and an image sensor 3230. The application processor 3100 may include a DigRF master 3110, a display serial interface (DSI) host 3120, a camera serial interface (CSI) host 3130, and a physical layer 3140.

The DSI host 3120 may communicate with the DSI device 3225 of the display 3220 according to the DSI. For example, an optical serializer SER may be implemented in the DSI host 3120. For example, an optical deserializer (DES) may be implemented in the DSI device 3225.

The CSI host 3130 may communicate with the CSI device 3235 of the image sensor 3230 according to the CSI. For example, an optical deserializer (DES) may be implemented in the CSI host 3130. For example, an optical serializer (SER) may be implemented in the CSI device 3235.

DSI and CSI may use the physical layer. The physical layers of DSI and CSI may employ embodiments of the present invention. For example, the physical layer of each of the DSI host 3120 and the DSI device 3225 may include a plurality of transmitters that operate based on a common clock signal. Further, the physical layer of each of the CSI device 3235 and the CSI host 3130 may include a plurality of transmitters operating based on a common clock signal.

The electronic system 3000 may further include a radio frequency (RF) chip 3240 that communicates with the application processor 3100. The RF chip 3240 may include a physical layer 3242, a DigRF slave 3244, and an antenna 3246. For example, the physical layer 3242 of the RF chip 3240 and the physical layer 3140 of the application processor 3100 may exchange data with each other through the DigRF interface proposed by the MIPI Alliance. The physical layers 3140 and 3242 of the DigRF interface may employ embodiments of the present invention. As an example, each of the physical layer 3140 and the physical layer 3242 may include a plurality of transmitters that operate based on a common clock signal.

The electronic system 3000 may further include a working memory 3250 and an embedded/card storage 3255. The working memory 3250 and the embedded/card storage 3255 may store data provided from the application processor 3100. Furthermore, the working memory 3250 and the embedded/card storage 3255 may provide stored data to the application processor 3100.

The working memory 3250 may temporarily store data processed or to be processed by the application processor 3100. The working memory 3250 may include volatile memory such as SRAM, DRAM, SDRAM, or the like, or nonvolatile memory such as flash memory, PRAM, MRAM, ReRAM, and FRAM.

The embedded/card storage 3255 can store data regardless of whether power is supplied or not. As an embodiment, the embedded/card storage 3255 may operate according to the UFS interface protocol, but the present invention is not limited to this embodiment. In this embodiment, as mentioned in the description of FIGS. 11 and 12, the physical layer of the embedded/card storage 3255 may include a plurality of transmitters operating based on a common clock signal.

The electronic system 3000 may communicate with an external system through a World Interoperability for Microwave Access (Wimax) 3260, a Wireless Local Area Network (WLAN) 3262, an Ultra Wideband (UWB) 3264, or the like. As an embodiment, the physical layer of the WLAN 3262 may include a plurality of transmitters that operate based on a common clock signal.

The electronic system 3000 may further include a speaker 3270 and a microphone 3275 for processing voice information. Furthermore, the electronic system 3000 may further include a Global Positioning System (GPS) device 3280 for processing location information.

The electronic system 3000 may further include a bridge chip 3290 for managing connections with peripheral devices. As an embodiment, the physical layer of the bridge chip 3290 may include a plurality of transmitters operating based on a common clock signal.

The configuration shown in each conceptual diagram should be understood only from a conceptual point of view. In order to help understand the present invention, the shape, structure, size, etc. of each of the constituent elements shown in the conceptual diagram are exaggerated or reduced. The configuration actually implemented may have a physical shape different from that shown in each conceptual diagram. Each conceptual diagram is not intended to limit the physical shape of the component.

The device configuration shown in each block diagram is intended to aid understanding of the invention. Each block may be formed of blocks of smaller units depending on the function. Alternatively, a plurality of blocks may form a larger unit block according to a function. That is, the technical idea of the present invention is not limited by the configuration shown in the block diagram.

In the above, the present invention has been described based on the embodiments of the present invention. However, due to the nature of the technical field to which the present invention belongs, the object to be achieved by the present invention may be achieved in a form different from the above embodiments while including the gist of the present invention. Therefore, the above embodiments should be understood in terms of description rather than limitation. That is, the technical idea capable of achieving the same object as the present invention while including the gist of the present invention should be interpreted as being included in the technical idea of the present invention.

Therefore, the technical idea modified or modified within the scope not departing from the essential characteristics of the present invention is to be included in the scope of protection claimed by the present invention. In addition, the scope of protection of the present invention is not limited to the above embodiments.

100: electronic system
110: first electronic device 113: first interface circuit
115: first controller 120: second electronic device
123: second interface circuit 125: second controller
200: transmission circuit
210: common clock block 220: transmission block
300: transmission circuit 310: common clock block
312: working clock generator 314: clock divider
320: transmission block 321, 322: serializer
323, 324: digital logic 325, 326: driver
331, 332: signal providing logic 333, 334: working clock buffer
335, 336: symbol clock buffer
341: latch 343: multiplexer
400: storage system 410: host
420: storage device 421: memory controller
423: nonvolatile memory 425: interface circuit
1000: embedded storage 1100: memory controller
1200: nonvolatile memory 1300: external input/output block
1400: memory input/output block 1420: buffer memory
2000: storage system
2100: host 2110: host controller
2120: host interface 2130: application
2140: device driver 2150: buffer memory
2200: card storage 2210: memory controller
2220: nonvolatile memory 2230: storage interface
2240: memory input/output block 2242: buffer memory
3000: electronic system 3100: application processor
3110: DigRF master 3120: DSI host
3130: CSI host 3140: physical layer
3220: display 3225: DSI device
3230: image sensor 3235: CSI device
3240: RF chip 3242: physical layer
3244: DigRF slave 3246: antenna
3250: working memory 3255: embedded/card storage
3260: Wimax 3262: WLAN
3264: UWB 3270: speaker
3275: microphone 3280: GPS
3290: Bridge chip

Claims (20)

A plurality of transmitters each configured to output data serially;
An operational clock generator configured to generate an operational clock signal; And
And a clock divider configured to divide the working clock signal to generate a symbol clock signal,
Each of the plurality of transmitters is configured to receive the operation clock signal and the symbol clock signal in common,
Each of the plurality of transmitters:
A serializer configured to receive parallel data in synchronization with the symbol clock signal and serialize the received parallel data in synchronization with the operation clock signal to generate serial data;
Digital logic configured to generate the parallel data to be provided to the serializer by receiving original data and extracting symbol-unit data from the original data based on the symbol clock signal provided through the serializer; And
A transmission circuit comprising a driver configured to output the serial data. The method of claim 1,
A lane reset signal used to reset a state of a lane corresponding to each of the plurality of transmitters and a power down signal used to stop an operation of each of the plurality of transmitters are independently provided for each of the plurality of transmitters,
Each of the plurality of transmitters is configured to operate independently based on the lane reset signal and the power down signal. The method of claim 2,
Each of the plurality of transmitters:
A working clock buffer configured to transfer the working clock signal to the serializer when the lane reset signal and the power down signal are not provided; And
And a symbol clock buffer configured to transfer the symbol clock signal to the serializer when the lane reset signal and the power down signal are not provided. The method of claim 3,
When at least one of the lane reset signal and the power down signal is provided, the working clock buffer and the symbol clock buffer are configured to not transfer the working clock signal and the symbol clock buffer to the serializer, respectively. The method of claim 1,
The operational clock generator is a transmission circuit comprising a PLL circuit. The method of claim 1,
The serializer is:
A latch configured to receive the parallel data from the digital logic; And
A transmission circuit comprising a multiplexer configured to receive the parallel data from the latch and generate the serial data. The method of claim 6,
The latch is configured to receive the parallel data in synchronization with the symbol clock signal. The method of claim 6,
The multiplexer is configured to generate the serial data by serializing the received parallel data in synchronization with the operating clock signal. The method of claim 1,
Each of the symbol unit data has a length of N bits,
The transmission circuit in which the period of the symbol clock signal is N times the period of the operating clock signal. A common clock block configured to output an operating clock signal used to serialize parallel data, and a symbol clock signal generated by dividing the operating clock signal and used to extract data in units of symbols; And
A transmission block including a plurality of transmitters each configured to receive the operation clock signal and the symbol clock signal in common,
Each of the plurality of transmitters receives original data, extracts the symbol-unit data from the original data based on the symbol clock signal to generate parallel data, and generates parallel data in synchronization with the operation clock signal. A transmission circuit configured to generate serialized data by serializing and output the serialized data. The method of claim 10,
Each of the plurality of transmitters is a transmission circuit configured to operate independently using an operating power source. The method of claim 11,
When a first time when a first transmitter among the plurality of transmitters starts to operate is different from a second time when a second transmitter among the plurality of transmitters starts operation, the symbol clock signal provided to the first transmitter is the second A transmission circuit synchronized with the symbol clock signal provided to the transmitter. The method of claim 11,
A transmission circuit in which a lane reset signal used to reset a state of a lane corresponding to each of the plurality of transmitters and a power down signal used to stop an operation of each of the plurality of transmitters are independently provided for each of the plurality of transmitters . The method of claim 13,
A transmitter that has not received the lane reset signal and the power down signal among the plurality of transmitters operates,
The transmission circuit for stopping operation of a transmitter receiving at least one of the lane reset signal or the power down signal among the plurality of transmitters. The method of claim 10,
The transmission block is a transmission circuit included in the physical layer defined based on the MIPI M-PHY specification. Memory controller;
A nonvolatile memory configured to store data under control of the memory controller; And
Including an interface circuit configured to serially output the stored data according to an interface protocol using a physical layer,
The interface circuit is:
A plurality of transmitters included in the physical layer;
An operational clock generator configured to generate an operational clock signal; And
A clock divider configured to divide the working clock signal to generate a symbol clock signal,
The operating clock signal and the symbol clock signal are provided in common to each of the plurality of transmitters,
Each of the plurality of transmitters receives the stored data, extracts symbol-unit data from the received data based on the symbol clock signal to generate parallel data, and generates parallel data in synchronization with the operation clock signal. A storage device configured to serialize to generate serial data, and to output the serial data. The method of claim 16,
Each of the plurality of transmitters:
Digital logic configured to generate the parallel data by receiving the stored data and extracting the data in units of symbols from the received data based on the symbol clock signal;
A serializer configured to receive the generated parallel data from the digital logic in synchronization with the symbol clock signal and serialize the received parallel data in synchronization with the operation clock signal to generate the serial data; And
A storage device comprising a driver configured to output the serial data. The method of claim 17,
The digital logic is configured to receive the symbol clock signal through the serializer. The method of claim 16,
Each of the plurality of transmitters may operate independently based on a lane reset signal used to reset a state of a lane corresponding to each of the plurality of transmitters and a power down signal used to stop operation of each of the plurality of transmitters. Composed,
When a first time when a first transmitter among the plurality of transmitters starts to operate is different from a second time when a second transmitter among the plurality of transmitters starts operation, the symbol clock signal provided to the first transmitter is the second Storage device synchronized to the same as the symbol clock signal provided to the transmitter. The method of claim 16,
The physical layer is defined based on the MIPI M-PHY specification,
The memory controller is configured to exchange data with the nonvolatile memory according to the UFS interface protocol,
The memory controller, the nonvolatile memory, and the interface circuit are implemented in an embedded storage configured to be embedded in a mobile electronic system or a card storage configured to be connected to the mobile electronic system.

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