KR102204673B1 - SYSTEM ON CHIP(SoC) FOR PACKETIZING MULTI-BYTES - Google Patents

Abstract

Display serial interface (DSI) In a system-on-chip including a DSI including a PPI (PHY Protocol Interface) used for communication between a host controller and a D-PHY, the DSI host controller is PPI packetized. A register for storing first indication data indicating a method, and a lane distributor determining the size of a symbol to be transmitted to the PPI based on the first indication data and determining an order of first processing units to be included in the symbol. Include.

Description

System on chip that packetizes multi-bytes {SYSTEM ON CHIP(SoC) FOR PACKETIZING MULTI-BYTES}

An embodiment according to the concept of the present invention relates to a system on a chip, and in particular, a symbol including multi-bytes can be packetized using indication data indicating a PPI (PHY Protocol Interface) packetizing method. It relates to a system on a chip and a data processing system including the same.

As the resolution of the display increases, a display controller that transmits data to the display needs to increase the data transmission speed.

The display interface standard MIPI® (Mobile Industry Processor Interface) display serial interface (DSI) includes a DSI host controller and a D-PHY. As the frequency of the clock signal used between the DSI host controller and the D-PHY increases, the power consumption of the DSI increases.

In the process of manufacturing DSI, timing closure is becoming more difficult. Timing closure refers to the process by which a field-programmable gate array (FPGA) or very large-scale integration (VLSI) design is modified to satisfy the FPGA or VLSI timing requirements. Most of the modifications are handled by Electronic Design Automation (EDA) tools according to instructions given by the designer.

For example, when the host controller of the DSI transmits image data to the D-PHY in 1-byte units, the D-PHY serializes the image data and transmits the serialized image data to the display driver IC. As the resolution of the display increases, as the frequency of the clock signal of the D-PHY of the DSI increases to process high-resolution image data, timing closure becomes difficult and the power consumption of the DSI increases.

The technical problem to be achieved by the present invention is a symbol including multi-bytes distributed according to instruction data indicating a PPI (PHY Protocol Interface) packetization method of DSI in order to increase data transmission speed and reduce operating power consumption. It is to provide a system-on-chip capable of packetizing data and a data processing system including the same.

In a system-on-chip including a DSI including a PPI (PHY Protocol Interface) used for communication between a display serial interface (DSI) host controller and a D-PHY according to an embodiment of the present invention, the The DSI host controller determines the size of a symbol to be transmitted to the PPI based on a register for storing first instruction data indicating a PPI packetization method, and the first instruction data, and determines the size of the symbol to be transmitted to the symbol. Includes a lane distributor to determine the order.

The lane distributor receives a data packet including second processing units, a PPI processing unit (J) included in the first indication data, the number of lanes connected to the D-PHY (M), and transmission of the symbol. The first processing units are included by distributing some of the second processing units by using the order (N) and the number of the lane to which the symbol is to be transmitted from among the lanes connected to the D-PHY. The above symbol is generated.

The PPI processing unit represents a PPI data width, the size of each of the second processing units is 1-byte, and the lane distributor packetizes the symbol including the first processing units.

When the number of the first processing units is two, the lane distributor,

The symbols are packetized in the order of {BTYE((J*M)*N+L+M), BYTE((J*M)*N+L)},

Each of BTYE((J*M)*N+L+M) and BYTE((J*M)*N+L) represents an order of each of the first processing units included in the data packet.

When the number of the first processing units is 3, the lane distributor,

{BTYE((J*M)*N+L+2M), BTYE((J*M)*N+L+M), BYTE((J*M)*N+L)} Packetize,

BTYE((J*M)*N+L+2M), BTYE((J*M)*N+L+M), and BYTE((J*M)*N+L) each included in the data packet Indicates the order of each of the first processing units.

When the first processing units are some of the second processing units included in the data packet, the lane distributor is transmitted to the D-PHY in response to second instruction data indicating the number of the second processing units. An activation period of an indication signal indicating that data including the symbol is valid data is controlled.

The lane distributor generates the indication signal having a first activation period when the number of the second processing units is an even number, and the lane distributor generates the indication signal having a second activation period when the number of the second processing units is odd. Generate an indication signal.

The lane distributor sets the first activation period to be longer than the second activation period.

A data processing system according to an embodiment of the present invention includes a first DSP including a first PPI (PHY Protocol Interface) used for communication between a display serial interface (DSI) host controller and a first D-PHY. And a display driver IC including a second DSI including a second PPI used for communication between the DSI device controller and the second D-PHY. The DSI host controller determines a size of a symbol to be transmitted to the first PPI based on a register for storing first instruction data indicating a PPI packetization method and the first instruction data, and a first process to be included in the symbol. It includes a lane distributor that determines the order of units.

The data width of the first PPI and the data width of the second PPI are different from each other. The data width of the first PPI is greater than the data width of the second PPI.

The system-on-chip including a display serial interface (DSI) according to an embodiment of the present invention determines the size of a symbol using indication data indicating a PPI (PHY Protocol Interface) packetization method, and the It is possible to determine an order of processing units to be included in a symbol, and packetize the symbol including processing units distributed according to the determined order.

Since the DSI host controller of the DSI can transmit the packetized multi-processing unit symbol to the D-PHY of the DSI, the data transmission rate of the system-on-chip including the DSI increases, and the power consumption of the system-on-chip is increased. It has a reducing effect.

Even if the data width of the PPI of the DSI implemented in the system-on-chip and the data width of the PP1 of the DSI implemented in the display driver IC connected to the system-on-chip are different from each other, the system-on-chip is a processing unit distributed according to the determined order. Since the symbol including the signals can be transmitted to the display driver IC, the system-on-chip can satisfy backward compatibility with the display driver IC.

In addition, the DSI host controller, based on the indication data indicating the number of processing units included in the data packet, the data transmitted to the D-PHY (e.g., a symbol including processing units distributed according to the determined order) is effective. Since the activation period of the indication signal indicating data is controlled, the system-on-chip including the DSI host controller can satisfy backward compatibility with the display driver IC connected to the system-on-chip.

A detailed description of each drawing is provided in order to more fully understand the drawings cited in the detailed description of the present invention.
1 is a block diagram of a data processing system according to an embodiment of the present invention.
2 is a block diagram of a display serial interface (DSI) host controller according to an embodiment of the present invention shown in FIG. 1.
FIG. 3 is a conceptual diagram illustrating an embodiment of an operation of the first DSI of the controller shown in FIG. 1.
FIG. 4 is a conceptual diagram illustrating an embodiment of an operation of the 2DSI of the display driver IC shown in FIG. 1.
FIG. 5 is a conceptual diagram illustrating an embodiment of the operation of the first DSI of the controller and the second DSI of the display driver IC shown in FIG. 1.
6 is a conceptual diagram illustrating another embodiment of the operation of the first DSI of the controller shown in FIG. 1.
7 is a conceptual diagram illustrating another embodiment of the operation of the 2DSI of the display driver IC shown in FIG. 1.
8 is a flowchart for explaining the operation of the DSI host controller shown in FIG. 2.
9 illustrates signals exchanged between a DSI host controller and a D-PHY of a first DSI of a controller according to another embodiment of the present invention.
FIG. 10 shows an example of operation of a first DSI of a controller processing odd number of processing units and a second DSI of a display driver IC.
11 is a conceptual diagram illustrating a method of processing even number of processing units.
12 is a conceptual diagram illustrating a method of processing an odd number of processing units.
13 is a flowchart for explaining the operation of the host controller shown in FIG. 10.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification are merely illustrative for the purpose of describing the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present invention can apply various changes and have various forms, embodiments are illustrated in the drawings and will be described in detail in the present specification. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of the rights according to the concept of the present invention, the first component may be named as the second component and similarly the second component. The component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it is directly connected to or may be connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

Terms used in the present specification are used only to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprises" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described herein, but one or more other features. It is to be understood that the possibility of addition or presence of elements or numbers, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this specification. Does not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a data processing system according to an embodiment of the present invention. Referring to FIG. 1, the data processing system 100 may include a camera 200, a controller 300, and a display driver IC (DDI) 400.

The data processing system 100 capable of processing image data may be implemented as a mobile computing device. Mobile computing devices include laptop computers, mobile phones, smart phones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDA), digital still cameras, and digital video cameras. , PMP (portable multimedia player), PND (personal navigation device or portable navigation device), handheld game console, mobile internet device (MID), wearable computer, internet of things IoT)) devices, internet of everything (IoE) devices, drones, or e-books.

The camera 200 captures (or photographs) a subject to generate first image data, and transmits the first image data to the controller 300 through a camera serial interface 2 (CSI-2) 210 Can be transferred to. For example, the CSI-2 210 may include a CSI-2 transmitter 230 and a physical interface (PHY) known as the D-PHY 220. The CSI-2 transmitter 230 may communicate with the D-PHY 220 through a PPI (PHY protocol interface) 225. The camera 200 may refer to a camera module that may include a CMOS image sensor chip.

The controller 300 may control the camera 200 and the DDI 400. The controller 300 may be implemented as an integrated circuit (IC), a system on chip (SoC), an application processor (AP), or a mobile AP, but the controller 300 is limited thereto. It is not. For example, the controller 300 may be implemented as a semiconductor package including an IC, SoC, AP, or mobile AP.

The controller 300 includes a CSI-2 310, an image processor 320, a bus 330, a CPU 340, a graphics controller 350, and a first display serial interface (DSI) 360. It may include.

The CSI-2 310 may receive and process the first image data transmitted from the CSI-2 210 of the camera 200 and transmit the processed image data to the image processor 320. The CSI-2 310 may include a D-PHY 316, a PPI 314, and a CSI-2 receiver 312.

For example, the image processor 320 may mean an image signal processor (ISP). For example, the image processor 320 may change the format of the image data processed by the CSI-2 310 and may output second image data having the changed format to the bus 330.

Depending on the embodiment, the first image data (or image data processed by the CSI-2 310) may be image data having a Bayer pattern, and the second image data may be in RGB format, YUV format, or It may be image data having a YCbCr format. According to an embodiment, the first image data (or image data processed by the CSI-2 310) may be image data having an RGB format, and the second image data may be image data having a YUV format or a YCbCr format. However, the format of the first data and the format of the second data are not limited to the above-described examples.

The CPU 340 may overall control the operation of the controller 300. For example, the CPU 340 may control the CSI-2 310, the image processor 320, the graphics controller 350, and the first DSI 360 through the bus 330. For example, the CPU 340 may generate first instruction data capable of controlling the PPI packetization method of the DSI host controller 362 and/or second instruction data indicating the number of processing units included in the data packet. have.

The graphics controller 350 may process the second image data output from the image processor 320 and transmit the third image data generated according to the processing result to the first DSI 360. For example, the graphics controller 350 may refer to a graphics processing unit (GPU) capable of processing 2-dimensional image data or 3-dimensional image data. For example, the third image data may mean a data stream or a data packet.

The 1DSI 360 may mean a DSI defined in the MIPI® (Mobile Industry Processor Interface) standard, but the technical idea of the present invention is not limited to the MIPI® DSI. Accordingly, this specification includes the MIPI Alliance Standard for Display Serial Interface and Camera Serial Interface CSI-2 published by mipi® alliance ( http://mipi.org) as a reference.

The first DSI 360 may include a DSI host controller 362, a first PPI 364, and a first D-PHY 366. The data width of the first PPI 364 may be different from the data width of the second PPI 414 of the 2DSI 410 of the DDI 400. That is, the first PPI 364 and the second PPI 414 have an asymmetric structure.

The DSI host controller 362 receives the data packet including the second processing units, and determines the size of each symbol to be transmitted to the first PPI 364 based on first indication data indicating the PPI packetization method. And determine the order of the first processing units to be included in each symbol.

The first processing units may be part of the second processing units. For example, the size of each of the first processing units and the size of each of the second processing units may be 1-byte, but the size of each of the first processing units and the size of each of the second processing units according to the spirit of the present invention Is not limited to 1-byte.

The first DSI 360 of the controller 300 may communicate with the 2DSI 410 of the DDI 400 through the interface 370. The interface 370 may include a plurality of lanes.

The DDI 400 may include a 2DSI 410, and the 2DSI 410 may include a 2D-PHY 412, a 2PPI 414, and a DSI device controller 416. For example, the DDI 400 may be included in a display device or a display module.

2 is a block diagram of a display serial interface (DSI) host controller according to an embodiment of the present invention shown in FIG. 1. 1 and 2, the DSI host controller 362 may include a register 362-1 and a lane distributor 362-3.

The register 362-1 may store first indication data CDATA indicating a PPI packetization method. For example, the register 362-1 may be implemented as a special function register (SFR), but is not limited thereto. For example, the CPU 340 may set or program the first instruction data CDATA in the register 362-1.

The lane distributor 362-3 may determine the size of each symbol to be transmitted to the first PPI 364 based on the first indication data CDATA, and determine an order of first processing units to be included in each symbol. . The lane distributor 362-3 uses the data packet (PACKET) including the second processing units (0 to 15) and the first instruction data (CDATA) to determine the order of the first processing units to be included in each symbol. You can decide.

FIG. 3 is a conceptual diagram illustrating an embodiment of the operation of the first DSI of the controller shown in FIG. 1, and FIG. 5 shows an embodiment of the operation of the first DSI of the controller and the 2nd DSI of the display driver IC shown in FIG. It is a conceptual diagram to explain.

1 to 3, and 5, the lane distributor 362-3 may receive a data packet (PACKET) including second processing units (BYTE0 to BYPE15) and first instruction data (CDATA). I can. It is assumed that each of the second processing units BYTE0 to BYPE15 is data having a 1-byte size. In this specification, each of the second processing units BYTE0 to BYPE15 may be simply expressed as "0" to "15".

When the first PPI 364 processes (eg, packetizes) symbols in a J-byte PPI data width or a J-byte PPI processing unit, the lane distributor 362-3 uses the processing units distributed according to Equation 1 Can be packetized.

[Equation 1]

{BYTE((J*M)*N+L+M), BYTE((J*M)*N+L)}

Here, J denotes a PPI processing unit, and J may be a natural number of 1 or more.

M may mean the number of lanes connected to the 1D-PHY 366, and M may mean a natural number of 1 or more.

N may mean a transmission order of packetized symbols, and N is 0, 1, 2, ... Can be At this time, it is assumed that N for the first transmitted symbol is "0". L may mean the number of a lane to which a corresponding symbol is to be transmitted among lanes connected to the 1D-PHY 366.

For example, the first instruction data CDATA may include data (or information) for J, M, N, and L. When J is 2 and M is 4, the lane distributor 362-3 may determine the number of bytes to be included in each symbol S1 to S8 by using Equation 1. At this time, it is assumed that N for the symbols S1 to S4 is 0, and N for the symbols S5 to S6 is assumed to be 1.

The lane distributor 362-3, in the 0-th transmission (N=0), includes two bytes (BYTE0 and BYTE4) to be included in the first symbol S1 to be transmitted through the first lane (LANE0, L=0). ) Can be determined (or distributed) through Equation 1. That is, the first symbol S1 may include BYTE0(=BYTE((2*4)*0+0)) and BYTE4(=BYTE((2*4)*0+0+4)). Accordingly, the two bytes BYTE0 and BYTE4 may be packetized as the first symbol S1.

The lane distributor 362-3 includes two bytes (BYTE1 and BYTE5) to be included in the second symbol S2 to be transmitted through the second lane (LANE1, L=1) in the 0-th transmission (N=0). ) Can be determined (or distributed) through Equation 1. That is, the second symbol S2 includes BYTE1(=BYTE((2*4)*0+1)) and BYTE5(=BYTE((2*4)*0+1+4)). Accordingly, the two bytes BYTE1 and BYTE5 may be packetized as the second symbol S2.

The lane distributor 362-3 includes two bytes BYTE2 and BYTE6 to be included in the third symbol S3 to be transmitted through the third lane (LANE2, L=2) in the 0-th transmission (N=0). ) Can be determined (or distributed) through Equation 1. That is, the third symbol S3 includes BYTE2(=BYTE((2*4)*0+2)) and BYTE6(=BYTE((2*4)*0+2+4)). Accordingly, the two bytes BYTE2 and BYTE6 may be packetized with the third symbol S3.

The lane distributor 362-3 includes two bytes (BYTE3 and BYTE7) to be included in the fourth symbol S4 to be transmitted through the fourth lane (LANE3, L=3) in the 0-th transmission (N=0). ) Can be determined (or distributed) through Equation 1. That is, the fourth symbol S4 includes BYTE3(=BYTE((2*4)*0+3)) and BYTE7(=BYTE((2*4)*0+3+4)). Accordingly, the two bytes BYTE3 and BYTE7 may be packetized with the fourth symbol S4.

The lane distributor 362-3 includes two bytes (BYTE8 and BYTE12) to be included in the fifth symbol (S5) to be transmitted through the first lane (LANE1, L=0) in the first transmission (N=1). ) Can be determined through Equation 1. That is, the fifth symbol S5 includes BYTE8(=BYTE((2*4)*1+0)) and BYTE12 (=BYTE((2*4)*1+0+4)). Accordingly, the two bytes BYTE8 and BYTE12 are packetized with the fifth symbol S5.

In the same or similar to the above-described method, the lane distributor 362-3, in the first transmission (N=1), each symbol to be transmitted through each lane (LALE1, LANE2, and LANE3) (S6, S7, And S8), each of two bytes (BYTE9 and BYTE13, BYTE10 and BYTE14, and BYTE11 and BYTE15) may be determined (or distributed). Accordingly, each of the two bytes BYTE9 and BYTE13, BYTE10 and BYTE14, and BYTE11 and BYTE15 are packetized into symbols S6, S7, and S8.

3 and 5, each symbol S1 and S5 is a first serializer/deserializer (SerDes) of a first D-PHY through a first PPI 364 in a 2-byte PPI processing unit; 366-1). The first SerDes 366-1 serializes each symbol S1 and S5, and transmits each serialized symbol to the first lane LANE0. As shown in FIG. 5, serialized bytes 0, 4, 8, and 12 may be transmitted to the 2DSI 410 through the first lane LANE0.

Each symbol S2 and S6 is transmitted to the second SerDes 366-2 of the first D-PHY 366 through the first PPI 364 in a 2-byte PPI processing unit. The second SerDes 366-2 serializes each symbol S2 and S6, and transmits each serialized symbol to the second lane LANE1. As shown in FIG. 5, the serialized bytes 1, 5, 9, and 13 may be transmitted to the 2DSI 410 through the second lane LANE1.

Each of the symbols S3 and S7 is transmitted to the third SerDes 366-3 of the 1D-PHY 366 through the 1PPI 364 in a 2-byte PPI processing unit. The third SerDes 366-3 serializes each symbol S3 and S7, and transmits each serialized symbol to the third lane LANE2. As shown in FIG. 5, the serialized bytes 2, 6, 10, and 14 may be transmitted to the 2DSI 410 through the third lane LANE2.

Each of the symbols S4 and S8 is transmitted to the 4th SerDes 366-4 of the 1D-PHY 366 through the 1PPI 364 in a 2-byte PPI processing unit. The fourth SerDes 366-4 serializes each symbol S4 and S8, and transmits each serialized symbol to the fourth lane LANE3. As shown in FIG. 5, serialized bytes 3, 7, 11, and 15 may be transmitted to the 2DSI 410 through a fourth lane LANE3.

For example, the lane distributor 362-3 may distribute each of the bytes BYTE0 to BYPE15 by 1-byte for each lane (LANE0 to LANE3) in a round-ribin manner.

FIG. 4 is a conceptual diagram illustrating an embodiment of an operation of the 2DSI of the display driver IC shown in FIG. 1.

4 and 5, a fifth SerDes 412-1 deserializes the serialized bytes 0, 4, 8, and 12 received through the first lane LANE0, and deserializes the serialized bytes. Each of the risen symbols S1 and S2 may be output to the lane merger 416-1 through the second PPI 414.

The sixth SerDes 412-2 deserializes the serialized bytes (1, 5, 9, and 13) received through the second lane LANE1, and deserializes each symbol (S2 and S6). May be output to the lane merger 416-1 through the second PPI 414.

The 7th SerDes 412-3 deserializes the serialized bytes 2, 6, 10, and 14 received through the third lane LANE2, and deserializes each symbol (S3 and S7). May be output to the lane merger 416-1 through the second PPI 414.

The eighth SerDes 412-4 deserializes the serialized bytes 3, 7, 11, and 15 received through the fourth lane LANE3, and deserializes each symbol S4 and S8. May be output to the lane merger 416-1 through the second PPI 414.

The lane merger 416-1 may perform a merging operation for each lane (LANE0 to LANE3) by 1-byte. 3 to 5, the order of processing units BYTE0 to BYTE15 included in the data packet PACKET input to the first DSI 360 of the controller 200 is the 2DSI 410 of the DDI 400. It is the same as the order of the processing units (BYTE0 to BYTE15) included in the data packet (PACKET) output from ).

Thus, even if the data width of the first PPI 364 of the first DSP 360 of the controller 200 is different from the data width of the second PPI 414 of the second DSP 410 of the DDI 400, that is, the PPIs ( Although 364 and 414 are asymmetric, the 2DSI 410 of the DDI 400 has an effect of accurately recovering the data packet PACKET transmitted from the 1DSI 360 of the controller 200.

That is, the first DSI 360 of the controller 200 may operate backward compatibile with the second DSI 410 of the DDI 400, for example, a legacy device.

6 is a conceptual diagram illustrating another embodiment of the operation of the first DSI of the controller shown in FIG. 1. 2 and 6, the lane distributor 362-3 may receive a data packet PACKET including the second processing units BYTE0 to BYPE15 and the first instruction data CDATA. It is assumed that each of the second processing units BYTE0 to BYPE15 is data having a 1-byte size.

When the first PPI 364 processes (eg, packetizes) symbols in a J-byte PPI data width or a J-byte PPI processing unit, the lane distributor 362-3 uses the processing units distributed according to Equation 2 Can be packetized.

[Equation 2]

{BYTE((J*M)*N+L+2M), BYTE((J*M)*N+L+M), BYTE((J*M)*N+L)}

For example, the first instruction data CDATA may include data for J, M, N, and L. When J is 3 and M is 4, the lane distributor 362-3 may determine the number of bytes to be included in each symbol S1 to S4 using Equation 2. At this time, it is assumed that N for the symbols S1 to S4 is 0.

The lane distributor 362-3 includes three bytes (BYTE0, BYTE4) to be included in the first symbol (S1) to be transmitted through the first lane (LANE0, L=0) in the 0-th transmission (N=0). , And BYTE8) may be determined (or distributed) through Equation 2. That is, the first symbol (S1) is BYTE0 (=BYTE((3*4)*0+0)), BYTE4(=BYTE((3*4)*0+0+4)), and BYTE8(=BYTE Includes ((3*4)*0+0+2*4)). Accordingly, the three bytes BYTE0, BYTE4, and BYTE4 are packetized as the first symbol S1.

The lane distributor 362-3 includes three bytes (BYTE1, BYTE5) to be included in the second symbol (S2) to be transmitted through the second lane (LANE1, L=1) in the 0-th transmission (N=0). , And BYTE9) may be determined through Equation 2. That is, the second symbol (S2) is BYTE1(=BYTE((3*4)*0+1)), BYTE5(=BYTE((3*4)*0+1+4), and BYTE9(=BYTE( (3*4)*0+1+2*4)) Therefore, the three bytes BYTE1, BYTE5, and BYTE9 are packetized with the third symbol S3.

The lane distributor 362-3 includes 3 bytes (BYTE2, BYTE6) to be included in the third symbol (S3) to be transmitted through the third lane (LANE2, L=2) in the 0-th transmission (N=0). , And BYTE10) may be determined through Equation 2. That is, the third symbol (S3) is BYTE2(=BYTE((2*4)*0+2)), BYTE6(=BYTE((2*4)*0+2+4)), and BYTE10(=BYTE ((2*4)*0+2+2*4)). Accordingly, the three bytes BYTE2, BYTE6, and BYTE10 are packetized with the third symbol S3.

The lane distributor 362-3 includes three bytes (BYTE3, BYTE7) to be included in the fourth symbol (S4) to be transmitted through the fourth lane (LANE3, L=3) in the 0-th transmission (N=0). , And BYTE11) may be determined through Equation 2. That is, the fourth symbol (S4) is BYTE3(=BYTE((2*4)*0+3)), BYTE7(=BYTE((2*4)*0+3+4)), and BYTE11(=BYTE Include ((2*4)*0+3+2*4)). Accordingly, the three bytes BYTE3, BYTE7, and BYTE11 are packetized as the fourth symbol S4.

Referring to FIG. 6, the first symbol S1 is transmitted to the first SerDes 366-1 of the 1D-PHY 366 through the first PPI 364 in a 3-byte PPI processing unit. The first SerDes 366-1 serializes the first symbol S1, and transmits the serialized first symbol to the first lane LANE0. The serialized first symbol may be transmitted to the 2DSI 410 through the first lane LANE0.

The second symbol S2 is transmitted to the second SerDes 366-2 of the 1D-PHY 366 through the 1PPI 364 in a 3-byte PPI processing unit. The second SerDes 366-2 serializes the second symbol S2, and transmits the serialized second symbol to the second lane LANE1. The serialized second symbol may be transmitted to the 2DSI 410 through the second lane LANE1.

The third symbol S3 is transmitted to the third SerDes 366-3 of the 1D-PHY 366 through the 1PPI 364 in a 3-byte PPI processing unit. The third SerDes 366-3 serializes the third symbol S3, and transmits the serialized third symbol to the third lane LANE2. The serialized third symbol may be transmitted to the 2DSI 410 through the third lane LANE2.

The fourth symbol S4 is transmitted to the fourth SerDes 366-4 of the 1D-PHY 366 through the 1PPI 364 in a 3-byte PPI processing unit. The fourth SerDes 366-4 serializes the fourth symbol S4, and transmits the serialized fourth symbol to the fourth lane LANE3. The serialized fourth symbol may be transmitted to the 2DSI 410 through the fourth lane LANE3.

For example, the lane distributor 362-3 may distribute each of the bytes BYTE0 to BYPE15 by 1-byte for each lane (LANE0 to LANE3) in a round-ribin manner.

7 is a conceptual diagram illustrating another embodiment of the operation of the 2DSI of the display driver IC shown in FIG. 1.

Referring to FIG. 7, a 5th SerDes 412-1 deserializes the serialized first symbol received through the first lane LANE0, and deserializes the deserialized first symbol S1 into a second PPI ( Through 414), it may be output to the lane merger 416-1. The first symbol S1 may include three packetized bytes BYTE0, BYTE4, and BYTE8.

The 6th SerDes 412-2 deserializes the serialized second symbol received through the second lane LANE1, and transmits the deserialized second symbol S2 through the second PPI 414. It can be output as (416-1). The second symbol S2 may include three packetized bytes BYTE1, BYTE5, and BYTE9.

The 7th SerDes 412-3 deserializes the serialized third symbol received through the third lane LANE2, and transmits the deserialized third symbol S3 through the second PPI 414. It can be output as (416-1). The third symbol S3 may include three packetized bytes BYTE2, BYTE6, and BYTE10.

The 8th SerDes 412-4 deserializes the serialized fourth symbol received through the fourth lane LANE3, and transfers the deserialized fourth symbol S4 through the second PPI 414. It can be output as (416-1). The fourth symbol S4 may include three packetized bytes BYTE3, BYTE7, and BYTE11.

The lane merger 416-1 may perform a merging operation for each lane (LANE0 to LANE3) by 1-byte. Referring to FIG. 7, the order of processing units BYTE0 to BYTE15 included in the data packet PACKET input to the first DSI 360 of the controller 200 is output from the 2DSI 410 of the DDI 400. It is the same as the order of processing units (BYTE0~BYTE15) included in the data packet (PACKET).

Thus, even if the data width of the first PPI 364 of the first DSP 360 of the controller 200 is different from the data width of the second PPI 414 of the second DSP 410 of the DDI 400, that is, the PPIs ( Although 364 and 414 are asymmetric, the 2DSI 410 of the DDI 400 has an effect of accurately recovering the data packet PACKET transmitted from the 1DSI 360 of the controller 200.

FIG. 8 is a flowchart illustrating the operation of the DSI host controller shown in FIG. 2. 1 to 8, the lane distributor 362-3 receives the first instruction data CDATA output from the register 362-1 (S110). The lane distributor 362-3 determines the size of each symbol to be transmitted to the first PPI 364 based on the first indication data CDATA (S112). The lane distributor 362-3 determines an order of first processing units to be included in each symbol based on the first indication data CDATA (S114). At this time, the lane distributor 362-3 determines the order of the first processing units to be included in each symbol using Equation 1 or Equation 2 (S114).

9 illustrates signals exchanged between a DSI host controller and a D-PHY of a first DSI of a controller according to another embodiment of the present invention. Referring to FIG. 9, the DSI host controller 362 receives the second instruction data NoB indicating the number of processing units included in the data packet, and each data to be transmitted to the 1D-PHY 366 is valid data. Each indication signal (TxWordValid_0 to TxWordValid_3) indicating that it can be generated.

Referring to FIG. 9, a clock signal WordClk means a high-speed transmission byte clock signal, and a clock signal WordClk can be used as a common clock of each lane LANE0 to LANE3.

The DSI host controller 362 transmits the first high-speed transmission data (TxDataHS_0[7:0]) and the second high-speed transmission data (TxDataHS_0[15:8]) in response to the rising edge of the clock signal WordClk. It can be transmitted to the first lane (LANE0).

It is assumed that the first high-speed transmission data TxDataHS_0[7:0] is LSBs (least significient bits), and the second high-speed transmission data TxDataHS_0[15:8] is MSBs (most significient bits). It is assumed that the size of each high-speed transmission data (TxDataHS_0[7:0]) and TxDataHS_0[15:8] is 1-byte.

One symbol may include first high-speed transmission data TxDataHS_0[7:0] and second high-speed transmission data TxDataHS_0[15:8]. At this time, it is assumed that each data (TxDataHS_0[0] and TxDataHS_0[8]) is transmitted first.

When both the LSB and MSB are valid data, the indication signal TxWordValid_0 is activated, and in other cases, the indication signal TxWordValid_0 is deactivated. Here, it is assumed that activation is a low-to-high transition, and deactivation is assumed to be a high-to-low transition.

The transmission request signal (TxRequestHS_0) means a high-speed transmission request. When the transmission request signal TxRequestHS_0 is activated, the 1D-PHY 366 initiates a start-of-transmission sequence (SOT). When the transmission request signal (TxRequestHS_0) is deactivated, the 1D-PHY 366 initiates an end-of-transmission sequence (EOT).

The transmission preparation signal (TxReadyHS_0) means high-speed transmission preparation, and when the transmission preparation signal (TxReadyHS_0) is activated, the 1D-PHY 366 transmits each high-speed transmission data (TxDataHS_0[7:0]) and TxDataHS_0[15:8] ]) can be sent serially.

The fourth lane (LANE3) is each high-speed transmission data (TxDataHS_3[7:0]) and TxDataHS_3[15:8] transmitted from the DSI host controller 362, an indication signal (TxWordValid_3), and a transmission request signal (TxRequestHS_3). Is transmitted to the 1D-PHY 366, and the transmission preparation signal TxReadyHS_3 output from the 1D-PHY 366 is transmitted to the DSI host controller 362.

The first DSI 360 of the controller 200 must transmit only valid data to the 2DSI 410 of the DDI 400. When the DSI device controller 416 of the DDI 400 de-packetizes the received data (or received symbols), the DSI device controller 416 uses the header information of the data packet. Thus, it is determined whether the received data (or received symbols) is valid data, and invalid data is determined as EOT. At this time, if a valid EOT is not input, the DSI device controller 416 may malfunction.

Since the information on the EOT is generated by the 1D-PHY 366 of the 1DSI 360 of the controller 200, the DSI host controller 362 of the 1DSI 360 must ensure that only valid data is the 1D-PHY 366 ).

When the size of the data packet is divided by the PPI data width, or when the number of all processing units included in the data packet is an even number, the DSI host controller 362, during one cycle, the 2DSI 410 of the DDI 400 Each indication signal (TxWordValid_0 to TxWordValid_3) indicating that all data (eg, 2-bytes) transmitted to is valid data may be transmitted to the 2DSI 410 of the DDI 400.

However, when the size of the data packet is not divided by the PPI data width, or when the number of all processing units included in the data packet is an odd number, the DSI host controller 362 performs a second DSI of the DDI 400 during one cycle Dummy data from among the plurality of data transmitted to 410 should not be transmitted to the 1D-PHY 366. When an odd number of processing units are transmitted to the 2DSI 410 of the DDI 400 during one cycle, the DSI host controller 362 transmits the deactivated indication signals TxWordValid_0 to TxWordValid_3 to the 2DSI of the DDI 400 ( 410). Each indication signal TxWordValid_0 to TxWordValid_3 may indicate whether data transmitted to each lane (LANE0 to LANE3) is valid data.

FIG. 10 is a diagram illustrating an exemplary operation of a first DSI of a controller that processes odd number of processing units and a second DSI of a display driver IC, and FIG. 12 is a conceptual diagram illustrating a method of processing odd number of processing units.

When the second instruction data NoB indicating that the number of processing units included in the data packet is odd, for example 15, is input to the DSI host controller 362, the DSI host controller 362 is The same indication signal (TxWordValid_#) can be generated. The indication signal TxWordValid_# collectively represents at least one of the indication signals TxWordValid_0 to TxWordValid_3.

10 and 12, when an even number (eg, two) of processing units are transmitted from the DSI host controller 362 to the 1D-PHY 366 in each cycle, the DSI host controller 362 Generates an activated indication signal (TxWordValid_#). However, when an odd number (eg, 1) of processing units are transmitted from the DSI host controller 362 to the 1D-PHY 366 in a specific cycle, the DSI host controller 362 is a deactivated indication signal (TxWordValid_# ). That is, since the indication signal TxWordValid_# is deactivated at the time point Ta, the 1D-PHY 366 may determine that only the LSB (byte#14) is valid data in response to the deactivated indication signal TxWordValid_#. .

11 is a conceptual diagram illustrating a method of processing an even number of processing units.

5, 9, and 11, when the second instruction data NoB indicating that the number of processing units included in the data packet is an even number, for example 16, is input to the DSI host controller 362, The DSI host controller 362 may generate an indication signal TxWordValid_# as shown in FIG. 11.

Referring to FIG. 11, when an even number (eg, two) of processing units are transmitted from the DSI host controller 362 to the 1D-PHY 366 in each cycle, the DSI host controller 362 indicates an activated Generate a signal (TxWordValid_#).

13 is a flowchart illustrating the operation of the host controller shown in FIG. 10. 9 to 13, the DSI host controller 362, for example, the lane distributor 362-3, receives second instruction data NoB indicating the number of processing units included in the data packet PACKET. (S210). The DSI host controller 362, for example, the lane distributor 362-3, has at least one processing unit included in the symbol to be transmitted to the 1D-PHY 366 in response to the second indication data NoB. Controls the activation period of the indication signal (TxWordValid_#) indicating data.

For example, when the number of processing units included in a symbol to be transmitted during a specific cycle is an even number, the lane distributor 362-3 generates an activated indication signal TxWordValid_#. The lane distributor 362-3 generates an inactivated indication signal TxWordValid_# when the number of processing units included in a symbol to be transmitted during a specific cycle is an odd number.

When the number of processing units included in the data packet (PACKET) is an even number, the lane distributor 362-3 generates an indication signal (TxWordValid_#) having a first activation period as shown in FIG. 11. However, when the number of processing units included in the data packet PACKET is an odd number, the lane distributor 362-3 generates an indication signal TxWordValid_# having a second activation period as shown in FIG. 12. 11 and 12, the first activation period is longer than the second activation period.

The present invention has been described with reference to the embodiments shown in the drawings, but these are only exemplary, and those of ordinary skill in the art will appreciate that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the attached registration claims.

100: data processing system
300: controller, system on chip, or application processor
360: first display serial interface (DSI)
362: DSI host controller
362-1: register, special function register (SFR)
362-3: Lane Distributor
364: PPI (PHY Protocol Interface)
366: D-PHY
400: display driver IC
410: 2DSI
412: D-PHY
414: PPI
416: DSI device controller

Claims (10)

In the data processing system:
A register configured to provide first indication data indicating a packetization scheme; And
Including lane distributor,
The Lane Distributors are:
Packetizing a first symbol and a second symbol to be transmitted through a PHY protocol interface (PPI) based on the first indication data,
A first indication signal and the first symbol are transmitted through a first lane of the PPI, and the first indication signal is related to whether at least one first processing unit included in the first symbol is valid,
A second indication signal and the second symbol are transmitted through a second lane of the PPI, and the second indication signal is related to whether at least one second processing unit included in the second symbol is valid,
The first indication signal is activated while the first processing unit included in the first symbol is transmitted through the first lane,
The second indication signal is activated while the second processing unit included in the second symbol is transmitted through the second lane. The method of claim 1,
The lane distributor is configured to determine the first lane as a lane to which the first symbol is to be transmitted, based on the first indication data. The method of claim 1,
The lane distributor determines the number of lanes included in the PPI based on the first indication data. The method of claim 3,
The lane distributor is configured to determine a transmission order of the at least one first processing unit and the at least one second processing unit based on the first indication data. The method of claim 1,
The lane distributor is configured to additionally packetize the first symbol and the second symbol based on second indication data associated with the number of the at least one first processing unit and the number of the at least one second processing unit. Data processing system. The method of claim 1,
When the number of the at least one first processing unit is an even number, the first indication signal has a first state during a first period,
When the number of the at least one first processing unit is odd, the first indication signal has the first state during a second period, and the first indication signal does not have a second state during a third period after the second period. Is a data processing system. The method of claim 6,
The data processing system in which the first period is longer than the second period. The method of claim 1,
The lane distributor is configured to receive a data packet and second indication data from a display serial interface (DSI) host controller. The method of claim 8,
The data packet is a data processing system including the at least one first processing unit and the at least one second processing unit. The method of claim 8,
The lane distributor is configured to acquire a plurality of processing units included in the data packet based on the second indication data.

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