KR102201662B1 - Sub-sampling receiver - Google Patents

Abstract

A wireless signal receiver according to an embodiment of the present invention includes an analog-to-digital converter for converting an analog wireless signal into a digital baseband signal, and separates and processes the digital baseband signal into a first path signal and a second path signal, And a sub-sampling block for extracting a complex baseband signal by using a relative sample delay difference between the first and second path signals, wherein the first path signal includes a sample delay and a sample rate for the digital baseband signal. It is an adjusted signal, and the second path signal is filtered without adjusting a sample delay or a sample rate for the digital baseband signal.

Description

Sub-sampling receiver {SUB-SAMPLING RECEIVER}

The present invention relates to a communication system, and more specifically, to a sub-sampling receiver.

Along with the trend of miniaturization of wireless communication systems, there is an increasing demand for a next-generation wireless communication receiver with flexibility, adaptability, and cognitivity. To satisfy these requirements, design an analog-to-digital converter (ADC) as close to the antenna as possible, and use a digital signal processor (DSP) to perform frequency conversion and demodulation. There is a need for a receiver design technique to perform. As a next-generation wireless communication receiver that satisfies these conditions, a sub-sampling receiver is in the spotlight. The sub-sampling receiver can provide excellent functions in terms of reconfiguration of a received signal and multiband/multimode reception.

A typical sub-sampling receiver may receive an analog RF signal through an antenna and extract an analog signal of a predetermined band through an analog bandpass filter. The extracted analog signal of a predetermined band may be amplified through a low noise amplifier (LNA) and then converted into a digital baseband signal through an analog-digital converter (ADC). Since the sub-sampling receiver does not use analog elements such as a mixer or a local oscillator, it is possible to provide a flexible low-cost and compact wireless communication receiver. However, the conventional sub-sampling receiver has a limitation in downconverting the received analog RF signal to a digital baseband signal only when the carrier frequency is an integer multiple of the sample rate in receiving a single RF signal. .

Therefore, when a signal located in an arbitrary frequency band is to be received using a conventional sub-sampling receiver, a sample rate must be determined so that elimination does not occur in the baseband after digital conversion. However, it is very complicated to determine a sample rate that prevents elimination from occurring, and there are many cases where there is no solution to the sample rate that prevents elimination from occurring. Therefore, there is a limitation in receiving an RF signal located in an arbitrary frequency band using a conventional sub-sampling receiver.

Meanwhile, the proposed second-order bandpass sampling receiver to solve this problem performs sampling using two ADCs and then eliminates aliasing by using signal processing. Therefore, the sample rate can be selected without consideration of aliasing. However, the conventional second-order bandpass sampling receiver not only increases hardware complexity by using two ADCs, but also has a serious performance degradation problem due to an analog time error between two signal paths and an analog signal size imbalance.

Accordingly, an object of the present invention has been proposed in order to solve the above-described problems, and is to provide a bandpass sampling receiver capable of flexibly applying a sample rate while reducing hardware complexity.

Another object of the present invention is to provide a bandpass sampling receiver capable of receiving all frequency bands and signal bandwidths.

Another object of the present invention is to provide a bandpass sampling receiver capable of effectively removing aliasing generated in a baseband while using a single analog-to-digital converter.

Another object of the present invention is to provide a bandpass sampling receiver capable of preventing a relative delay time error and an analog signal size imbalance between signal paths.

A wireless signal receiver according to an embodiment of the present invention for achieving the above object includes an analog-to-digital converter for converting an analog wireless signal into a digital baseband signal, and a first path signal and a second path signal for the digital baseband signal. And a sub-sampling block for extracting a complex baseband signal using a relative sample delay difference between the first and second path signals, and wherein the first path signal is applied to the digital baseband signal. A signal obtained by adjusting a sample delay and a sample rate, and the second path signal is filtered without adjusting a sample delay or a sample rate for the digital baseband signal.

According to the present invention as described above, a radio frequency signal located in an arbitrary band can be directly down-converted by using a single analog-to-digital converter (ADC) or a sub-sampling receiver using only a single radio frequency (RF) chain. Accordingly, since it is possible to receive signals in an arbitrary frequency band using a single receiver, there is an advantage of being very economical because there is no need to redesign the receiver according to the frequency band.

Further, according to the present invention, since analog elements such as a mixer and a local oscillator are not required, a receiver with low power, miniaturization, and low cost can be provided. In addition, according to the sub-sampling method of the present invention, integration to accommodate multi-mode/multi-band is easy.

In addition, the receiver of the present invention can minimize the performance requirements of an analog-to-digital converter (ADC) and baseband signal processing by using a minimum sampling frequency. Further, the sub-sampling method of the present invention can provide relatively superior performance compared to the conventional sub-sampling method.

1 is a block diagram showing a receiver including a sub-sampling block according to a first embodiment of the present invention.
2 is a diagram illustrating an exemplary spectrum of an analog signal (ARF) located in an arbitrary frequency band.
3A and 3B are diagrams illustrating frequency spectra of signals of a first path and a second path of the sub-sampling block 140 of FIG. 1 by way of example.
4A is a diagram illustrating a frequency spectrum of a complex baseband signal s(t) output from the adder illustrated in FIG. 1 by way of example.
FIG. 4B is a diagram illustrating a spectrum of a signal s'(t) output from the digital up/down converter of FIG. 1 by way of example.
FIG. 5 shows an example in which the second digital filter 146 is replaced with a configuration that performs complex multiplication with a gain C having a predetermined constant value in the sub-sampling block 140 of FIG. 1.
6 is a block diagram showing a receiver according to a second embodiment of the present invention.
7 is a block diagram schematically showing a detailed configuration of the first sample rate converter 343 or the second sample rate converter 345 of FIG. 6.
8A and 8B are views exemplarily showing spectra of signals of a first path and a second path of the sub-sampling block 340 of FIG. 6, respectively.
9 is a block diagram showing a receiver according to a third embodiment of the present invention.
10 is a block diagram showing a receiver according to a fourth embodiment of the present invention.
11 is a block diagram showing a reconfigurable reconfigurable sub-sampling apparatus capable of applying various characteristics of a receiver of the present invention.
12 is a flowchart briefly showing a method of operating the reconfigurable sub-sampling device 600 of FIG. 11.

Both the preceding general description and the following detailed description are illustrative to provide additional description of the claimed invention. Therefore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments introduced herein are provided so that the disclosed contents may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

The terms used in the present application are used only to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements or numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. Does not.

In the present specification, when a part is referred to as including a certain component, it means that other components may be further included. In addition, each embodiment described and illustrated herein also includes its complementary embodiment. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a receiver including a sub-sampling block according to a first embodiment of the present invention. Referring to FIG. 1, the receiver 100 of the present invention may include an antenna 110, a band filter 120, a low noise amplifier 130, and a sub-sampling block 140. The sub-sampling block 140 includes a first path for providing sample delay and sample rate adjustment for the baseband signal, and a second path to which the sample delay and sample rate adjustment are not applied. Through this configuration, the sub-sampling block 140 can effectively remove aliasing that occurs in the baseband. If necessary, a digital up/down converter 150 may be included in the receiver.

The antenna 110 performs a function of receiving a radio frequency signal (ARF) transmitted wirelessly. The band filter 120 passes a signal of a specific frequency band in the received radio frequency signal. The band filter 120 may be designed such that the pass band is limited to a predetermined bandwidth B, and removes noise outside the signal band. In an exemplary embodiment, the pass band and pass bandwidth B set in the band filter 120 may have a fixed value or may be adjusted to different values. To this end, the band filter 120 may be configured as a variable band pass filter (Tunable BPF). The low noise amplifier 130 amplifies the signal selected by the band filter 120 by a predetermined gain. The signal amplified by the low noise amplifier 130 will be delivered to the sub-sampling block 140 including one ADC 141.

The sub-sampling block 140 includes an analog-to-digital converter 141, a sample rate up converter 142, a sample delay 143, a sample rate down converter 144, a first digital filter 145, and a second digital filter. (146), and may include an adder (147). Here, the sub-sampling block 140 includes one analog-to-digital converter 141. Further, the baseband signal sampled by the analog-to-digital converter 142 is provided to the sample rate up converter 142. The signal whose sample rate is increased by the sample rate up converter 142 is a first path through a sample delay 143, a sample rate down converter 144, and a first digital filter 145, and a second digital filter. It is added in the adder 147 via the second route via only (146). The signal s(t) added by the adder 147 will be processed by the digital up/down converter 150 as necessary and provided as an output signal OUT.

The analog-to-digital converter 141 converts the analog signal provided from the low noise amplifier 130 into a digital baseband signal DR. For example, the analog-to-digital converter 141 samples an analog signal provided from the low noise amplifier 130 at a sample rate f _S and outputs a digital baseband signal DR. The spectrum of the digital baseband signal DR converted through the analog-to-digital converter 141 will include a positive spectral component shifted from the positive frequency band and a negative spectral component shifted from the negative frequency band.

The sample rate up converter 142 increases the sample rate of the digital baseband signal DR output from the analog-to-digital converter 141 by N times. The digital baseband signal DR output from the analog-to-digital converter 141 is divided into a first path signal processed along a first path and a second path signal processed along a second path. As the digital baseband signal DR passes through the first path, the sample rate is increased N times, a predetermined sample (eg, 1 sample) is delayed, and then the sample rate is down-converted by N times. And the first path signal is finally processed by the first digital filter 145 and then provided to the adder 147. On the other hand, the digital baseband signal DR is provided to the second digital filter 146 along the second path. The digital baseband signal DR will only pass through the second digital filter 146 without changing the sample delay or sample rate when passing through the second path. And the second path signal is provided to the adder 147 after being processed by the second digital filter 146.

Here, the conversion multiples of the sample rate up converter 142 and the sample rate down converter 144 are the same. That is, the sample rate of the first path signal passing through the sample rate up converter 142 and the sample rate down converter 144 will be the same as the sample rate at the output of the analog-to-digital converter 141. In addition, the first path signal is delay-processed by a sample delay 143 positioned between the sample rate up converter 142 and the sample rate down converter 144. The sample delay 143 delays the first path signal by D samples. Here, the delay size D of the sample delay unit 143 may be an integer greater than 0 and less than the down sample rate (N).

The D sample delayed signal through the sample delay 143 is down-sampled through the sample rate down converter 144 so that the sample rate is 1/N times. The output signal of the sample rate down converter 144 is provided to the first digital filter 145. The digital baseband signal DR output from the analog-to-digital converter 141 is processed by the second digital filter 146 constituting the second path and provided to the adder 147.

Here, the first digital filter 145 and the second digital filter 146 are designed based on a relative sample delay difference or a fractional delay between the first and second paths. The characteristics of the first digital filter 145 and the second digital filter 146 will be described in more detail in FIGS. 3A and 3B to be described later. An image component shifted from a positive frequency band or an image component shifted from a negative frequency band may be removed through the first and second digital filters 145 and 146.

According to the configuration of the sub-sampling block 140 according to the present invention, it is possible to remove aliasing in the baseband generated by the positive frequency image component and the negative frequency image component. Image components can be removed through digital filters 146 and 146 in consideration of the size of the delay between the two paths and the size of the down sample rate. That is, despite using a single analog-to-digital converter 140, a complex baseband signal having a positive spectral component shifted from a positive frequency band or a complex baseband signal having a negative spectral component shifted from a negative frequency band The signal can be removed. Accordingly, compared to the conventional bandpass sub-sampling receiver whose sample rate is limited to a specific sample rate, the sample rate can be selected more flexibly, and reception is possible for all frequency bands and signal bandwidths.

The center frequency of the complex baseband signal extracted from the sub-sampling block 140 is determined by the carrier frequency (f _c ) and the sample rate (f _s ) of the analog RF signal, and may be zero or non-zero. . When the center frequency of the complex baseband signal extracted by the sub-sampling block 140 is not 0, the center frequency of the complex baseband signal may be shifted to 0 through a digital up/down converter (not shown). If the center frequency of the complex baseband signal extracted by the sub-sampling block 140 is 0, the digital up/down converter 150 for shifting the center frequency of the complex baseband signal to 0 may not be provided.

Meanwhile, the complex baseband signal output from the sub-sampling block 140 is a complex baseband signal having a positive spectral component shifted from a positive frequency band, or a negative frequency spectral component shifted from a negative frequency band. It may be a complex baseband signal having. In the present invention, for convenience of explanation, the sub-sampling block 140 removes a negative frequency spectrum component shifted from the negative frequency band, and generates a complex baseband signal having a positive frequency spectrum component shifted from the positive frequency band. It will be described as printing. However, this relates to an example to which the present invention is applied, and the configuration of the complex baseband signal extracted from the sub-sampling block 140 is not limited to a specific shape, and can be variously changed and modified.

FIG. 2 is a diagram illustrating a spectrum of an analog signal ARF located in an arbitrary frequency band. Referring to FIG. 2, it may be assumed that the analog signal ARF has a carrier frequency f _c and a signal bandwidth B.

The spectrum A(f) in the frequency domain of the analog signal ARF is expressed in the frequency domain as a symmetrical component of a positive frequency component and a negative frequency component. The spectral component R _{AR +} (f) represents the positive frequency spectral component of the analog signal (ARF). Spectral components R _{AR -} (f) shows that the frequency spectral components of the analog signal (ARF).

3A and 3B are diagrams illustrating spectrums of signals of a first path and a second path of the sub-sampling block 140 of FIG. 1 by way of example. 3A is generated when the digital baseband signal DR output from the analog-to-digital converter 141 passes through the sample rate up converter 142, the sample delay 143, and the sample rate down converter 144 It shows the characteristics of the first path signal R _A ^δ (f). 3B shows the signal characteristics of the second path signal R _B ^δ (f) through which the digital baseband signal DR output from the analog-to-digital converter 141 is transmitted without delay or sample rate change.

The first path signal R _A ^δ f) represents the spectrum of a signal in which the digital baseband signal DR is processed by the sample rate up converter 142, the sample delay 143, and the sample rate down converter 144. . The first path signal R _A ^δ (f) is a second path signal R _B ^δ (f) corresponding to the spectrum of the digital baseband signal DR, and a group delay effect due to a time delay difference is added. It can be understood as a spectrum. That is, the first path signal R _A ^δ (f) is a signal to which a fractional delay of D/N is applied. As a result, the first path signal R _A ^δ (f) has the same processing effect as including a group delay in the second path signal R _B ^δ (f) due to a time delay difference between paths.

로, 양의 주파수 대역으로부터 천이한 스펙트럼 성분에 대해서

로 주어질 수 있다. 여기서, n은 신호의 주파수 대역 위치 인덱스로 0 이상의 정수값으로 제공될 수 있으며, 신호의 반송파 주파수(f_c)와 아날로그-디지털 변환기(141)의 샘플률(f_s)에 의해서 결정된다. 즉, n=round(f_c/f_s)로 나타낼 수 있다. 여기서, 라운드 함수 round(x)는 x의 반올림을 의미한다. The effect of the group delay due to the time delay of the first path signal R _A ^δ (f) is for the spectral component shifted from the negative frequency band.

As for the spectral component shifted from the positive frequency band,

Can be given as Here, n may be provided as an integer value greater than or equal to 0 as the frequency band position index of the signal, and is determined by the carrier frequency f _c of the signal and the sample rate f _s of the analog-digital converter 141. That is, it can be expressed as n=round(f _c /f _s ). Here, the round function round(x) means rounding of x.

Considering the relationship between the first path signal R _A ^δ (f) and the second path signal R _B ^δ (f) described above, the spectral component shifted from the negative frequency band or the spectral component shifted from the positive frequency band is removed. Thus, the intended complex baseband signal can be obtained. Hereinafter, a method of designing the first digital filter 145 and the second digital filter 146 in consideration of the relationship between the first path signal R _A ^δ (f) and the second path signal R _B ^δ (f) will be described. will be.

The first path signal R _A ^δ (f) and the second path signal R _B ^δ (f) in the first Nyquist zone band may be represented by Equations 1 and 2, respectively.

In addition, the first spectrum S _A ^δ (f) indicating the result of the first path signal R _A ^δ (f) being filtered by the first digital filter 145 and the second path signal R _A ^δ (f) are the second The second spectrum S _B ^δ (f) representing the result filtered by the digital filter 146 may be expressed by Equations 3 and 4 below, respectively.

Wherein, R _- is (f), and R ₊ (f) corresponds to each digital baseband signal (DR) with a negative and positive frequency components of the frequency spectrum of the signal transition frequency base band replication (replica) spectrum.

And when the outputs of each of the first digital filter 145 and the second digital filter 146 are added by the adder 147, the spectrum of the output signal s(t) of the adder 147 can be expressed by Equation 5 below. have.

The filtering result of the first path signal R _A ^δ (f) passing through the first digital filter 145 and the filtering result of the second path signal R _B ^δ (f) passing through the second digital filter 146 are an adder. It can be added through (147). It will be appreciated that in other embodiments, the adder 147 may be replaced by a subtractor.

If the shifted spectral component is removed from the negative frequency band and only the shifted spectral component is left in the positive frequency band, the following equation (6) must be satisfied.

In order to satisfy Equation 6, the system of equations given by Equations 7 and 8 below must be satisfied.

When the simultaneous equations satisfying Equations 7 and 8 are solved, the response function of each of the digital filters is calculated as follows.

H _A (f) and H _B (f) thus obtained can be easily implemented through a digital FIR filter. In addition, as can be seen from Equation 10, H _B (f) is a constant, not a function of frequency. Accordingly, it can be seen that the filter characteristic H _B (f) of the second digital filter 146 can be easily implemented only by complex multiplication.

In addition, as can be seen from Equation 9 and Equation 10, the sample rate (f _s ) of the analog-to-digital converter 141, the sample delay value (D) of the sample delay unit 143, and the upward or downward sample rate The conversion rate (N) must satisfy 2nD/N≠m (here, m = integer). In addition, the sample rate (f _s ), the sample delay value (D), and the vertical sample rate (N) may be adjusted to satisfy 2nD/N≠m (here, m=integer). Here, n represents the position index of the radio frequency band, and m represents an arbitrary integer.

FIG. 4A is a diagram illustrating a frequency spectrum of a complex baseband signal s(t) output from the adder 147 shown in FIG. 1 by way of example. FIG. 4B is a diagram illustrating a spectrum of a signal s'(t) output from the digital up/down converter 150 of FIG. 1 by way of example.

Referring to FIG. 4A, a signal s(t) from which elimination is removed by adding s _A (t) output from the first digital filter 145 and s _B (t) output from the second digital filter 416 ) Can be created. That is, the digital filters 145 and 146 the signals are due to deohaejim by an adder 147, a spectral component (R transition from the negative frequency bands processed by the description in Equation 9 and Equation 10 _- (f )) is removed, and only the spectral component (R ₊ (f)) transitioned from the positive frequency band remains. Therefore, it will be possible to remove the elimination and generate a desired complex baseband signal.

When observing the spectrum of the baseband signal s(t) output through the adder 147, the center frequency of the baseband signal may not have a value of zero. For example, the center frequency of the baseband signal s(t) may be less than 0 or greater than 0. In this case, the center frequency of the baseband signal s(t) may be up-converted/down-converted by the digital up/down converter 150 to be adjusted to zero.

4B, a digital up/down conversion operation performed by the digital up/down converter 150 is illustrated in the frequency domain. According to the digital up/down conversion operation of the digital up/down converter 150, the center frequency of the signal s(t) output through the adder 147 may be adjusted to zero. The baseband signal s(t) will be output as a baseband signal s'(t) whose center frequency is adjusted to 0 by frequency adjustment of the digital up/down converter 150.

If the center frequency of the baseband signal s(t) output through the adder 147 is 0 (that is, the center frequency of the analog RF signal is an integer multiple of the sample rate), the bandpass sampling receiver according to the present invention In the configuration of the digital up/down converter 150 may be omitted.

The function of the receiver capable of removing aliasing through the sub-sampling block of the present invention described above has been described. However, the characteristics of the digital filters are not limited only to the above equations, and it will be well understood that the receiver function of the present invention can be implemented even with various types of modified filter characteristics.

FIG. 5 shows an example in which the second digital filter 146 is replaced with a configuration in which the second digital filter 146 is subjected to complex multiplication of a gain C of a predetermined constant value and the synchronization delay 246 in the sub-sampling block 140 of FIG. 1. Show. Referring to FIG. 5, the receiver 200 may include an antenna 210, a band filter 220, a low noise amplifier 230, a sub-sampling block 240, and a digital up/down converter 250. Here, the configuration and function of the antenna 210, the band filter 220, the low noise amplifier 230, and the digital up/down converter 250 are substantially the same as those of FIG. 1.

The sub-sampling block 240 includes an analog-to-digital converter 241, a sample rate up converter 242, a sample delay 243, a sample rate down converter 244, a first digital filter 245, and a synchronization delay. 246), a complex multiplier 246, and an adder 247. Here, the baseband signal sampled by the analog-to-digital converter 241 is a sample rate up converter 242, a sample delay unit 243, a sample rate down converter 244, and the first digital filter 245. 1 path is formed. In addition, a second path in which the baseband signal sampled by the analog-to-digital converter 241 is multiplied by a constant gain (C) by the synchronous delay unit 246 and the complex multiplier 246 may be formed.

The synchronization delayer 246 times the second path signal by a time delay generated by the first path signal passing through the sample rate up converter 242, the sample rate down converter 244, and the first digital filter 245. Apply delay. Accordingly, time synchronization between the first path signal and the second path signal is possible.

Analog-to-digital converter 241 of sub-sampling block 240, sample rate up converter 242, sample delay 243, sample rate down converter 244, first digital filter 245, adder 248 The configuration of is substantially the same as those of the sub-sampling block 140 of FIG. 1. The complex multiplier 247 is similar in function to the second digital filter 146 of FIG. 1, but may be provided with a simpler configuration. That is, it has been described that the response characteristic of the second digital filter 146 defined in Equation 10 is a constant rather than a function of frequency. Therefore, it is not provided as a digital filter with high complexity, but may be provided as a simple complex multiplier for providing a constant gain.

6 is a block diagram showing a receiver according to a second embodiment of the present invention. Referring to FIG. 6, the receiver 300 according to the second embodiment of the present invention may include an antenna 310, a band filter 320, a low noise amplifier 330, and a sub-sampling block 340. Here, it will be well understood that a digital up/down converter (not shown) positioned at the rear end of the sub-sampling block 340 may be added as necessary. Here, the sub-sampling block 340 includes a first path for providing sample delay and sample rate adjustment for the baseband signal, and a second path for sample rate adjustment without sample delay. Through this configuration, the sub-sampling block 340 can effectively remove aliasing occurring in the baseband.

The antenna 310 receives a radio frequency signal (ARF) transmitted wirelessly and transmits it to the band filter 320. The band filter 320 passes a signal of a specific frequency band in the received radio frequency signal ARF. The band filter 320 may be designed such that the pass band is limited to a predetermined bandwidth (B), and removes noise outside the signal band. In an exemplary embodiment, the pass band and pass bandwidth B set in the band filter 320 may have a fixed value or may be adjusted to different values. The low noise amplifier 330 amplifies the signal selected by the band filter 320 by a predetermined gain. The signal amplified by the low noise amplifier 330 will be transmitted to the sub-sampling block 340 including one ADC 341.

The sub-sampling block 340 includes an analog-to-digital converter 341, a sample delay 342, a first sample rate converter 343, a first digital filter 344, a second sample rate converter 345, and a second sample rate converter 343. A digital filter 346, and an adder 347 are included. Here, the baseband signal DR output from the analog-to-digital converter 341 is divided into a first path for providing sample delay and sample rate adjustment, and a second path for performing sample rate adjustment without sample delay. A first path through which the baseband signal DR is transmitted includes a sample delay 342, a first sample rate converter 343, and a first digital filter 344. The second path includes a second sample rate converter 345 and a second digital filter 346.

The baseband signals DR transmitted through the first path and the second path are processed by the first sample rate converter 343 and the second sample rate converter 343, respectively. Each of the first sample rate converter 343 and the second sample rate converter 343 may be adjusted to have a sample rate of L/M times the sample rate f _s of the baseband signal DR. Therefore, when the baseband signal DR of the sample rate f _s passes through the sample delay 342 and the first sample rate converter 343, a partial delay of (D×L/M) will be obtained. . However, when the baseband signal DR of the sample rate f _s passes through the second sample rate converter 345, only the rate of the sample rate will be changed by L/M times.

The fractional delay effect occurring in the first path according to the asymmetric delay effect by the sample delay unit 342 plays a key role in designing a filter to remove elimination. In addition, sample rate adjustment by the first sample rate converter 343 and the second sample rate converter 343 may provide partial delay effects of various sizes in a system in which the delay is controlled in units of one sample.

7 is a block diagram schematically showing a detailed configuration of the first sample roll converter 343 or the second sample rate converter 345 of FIG. 6. Referring to FIG. 7, the first sample rate converter 343 includes an up-sampler 362, an interpolation/decimation filter 364, and a down-sampler 366.

The up-sampler 362 increases the sample rate of the input signal to a sample rate higher than the sample rate f _s of the analog-to-digital converter 341. That is, the up-sampler 362 may increase the sample rate by L times.

The interpolation/decimation filter 364 performs interpolation and decimation filtering on the up-sampled baseband signal provided from the up-sampler 362.

The down-sampler 366 reduces the sample rate to be lower than the sample rate f _s of the analog-to-digital converter 341. That is, the down-sampler 366 can adjust the sample rate down by M times. Here, values of L representing the up sample rate and M representing the down sample rate may be provided as integers, respectively.

According to the first sample rate converter 343 having the above-described configuration, the sample rate of the D sample-delayed baseband signal may be changed by L/M times.

8A and 8B are diagrams illustrating spectrums of signals of a first path and a second path of the sub-sampling block 340 of FIG. 6 by way of example.

8A is a spectrum R of a first path signal generated when the baseband signal DR output from the analog-to-digital converter 341 passes through the sample delay 442 and the first sample rate converter 443 _It shows the characteristics of _A ^δ (f). Here, only the spectrum in the first Nyquist zone band of the spectrum R _A ^δ (f) of the first path signal will be shown. FIG. 8B shows a spectrum R _B ^δ (f) characteristic of a second path signal generated by processing the baseband signal DR output from the analog-to-digital converter 341 by the second sample rate converter 345. Here, only the spectrum in the first Nyquist zone band of the spectrum R _B ^δ (f) of the second path signal will be shown.

The first path signal with spectrum R _A ^δ (f) of the first path signal is a D sample delayed signal compared to the second path signal with spectrum R _B ^δ (f). Therefore, due to the relative difference in time delay, the spectrum R _A ^δ (f) of the first path signal includes the influence of the group delay compared to the spectrum R _B ^δ (f) of the second path signal. As a result, the spectrum R _A ^δ (f) of the first path signal has the same processing effect as including the group delay in the spectrum R _B ^δ (f) of the second path signal due to the delay difference between paths. .

The effect of the group delay due to the time delay of the spectrum R _A ^δ (f) of the first path signal is represented by the phase shift effect given by Equation 11 below.

The effect of group delay appears as a phase shift of e ^{j θ-(f)} for the spectral component shifted from the negative frequency band. On the other hand, the effect of the group delay appears as a phase shift of e ^{j θ+(f) for} the spectral component shifted from the positive frequency band. Here, n is the frequency band position index of the signal, and 0 or more will be any one of integers. The frequency band position index n is the carrier frequency (f _c ) of the signal and the output sample rate (f' _s ) of the first sample rate converter 343 = L f _s /M), and the frequency band position index n can be given as round(f _c /f' _s ).

Considering the relationship between the spectrum R _A ^δ (f) of the first path signal and the spectrum R _B ^δ (f) of the second path signal described above, the spectral component shifted from the negative frequency band or the spectral component shifted from the positive frequency band By removing the spectral component, the intended complex baseband signal can be obtained. Hereinafter, the first digital filter 344 and the second digital filter 346 are designed in consideration of the relationship between the spectrum R _A ^δ (f) of the first path signal and the spectrum R _B ^δ (f) of the second path signal. The method will be explained.

The spectrum R _A ^δ (f) of the first path signal and the spectrum R _B ^δ (f) of the second path signal in the first Nyquist zone band may be expressed by Equations 12 and 13, respectively.

And the first spectrum of the path signals R _A ^δ (f) and claim 2 When the spectral R _A ^δ (f) of the path signals are processed by the first digital filter 344 and the second digital filter 346 in equation (14) The first spectrum S _A ^δ (f) and the second spectrum S _B ^δ (f) of Equation 15 will be output.

Then, the spectrum of the output signal output from the adder 347 may be expressed by Equation 16 below. The filtering result of the spectrum R _A ^δ (f) of the first path signal passing through the first digital filter 344 and the spectrum R _B ^δ (f) of the second path signal passing through the second digital filter 346 It has been described that the filtering result is processed by the adder 347. However, it will be appreciated that in other embodiments, the adder 347 may be replaced by a subtractor.

If, in order to remove the spectral component shifted from the negative frequency band and extract only the spectral component shifted from the positive frequency band, Equation 17 below must be satisfied.

In order to satisfy Equation 17, the system of equations given by Equations 18 and 19 below must be satisfied.

When the simultaneous equations satisfying Equations 18 and 19 are solved, the response function of each of the digital filters is calculated as follows.

H _A (f) and H _B (f) thus obtained can be easily implemented through a digital FIR filter. In addition, as can be seen from Equation 21, H _B (f) is a constant, not a function of frequency. Therefore, it can be seen that the filter characteristic H _B (f) of the second digital filter 346 can be easily implemented only by complex multiplication.

In addition, as can be seen from Equation 20 and Equation 21, the sample rate f _s of the analog-to-digital converter 341, the sample delay value D of the sample delay 342, the upward sample rate L, The direction sample rate (M) must satisfy the condition 2nLD/M≠m (here, m=integer). In addition, the sample rate (f _s ), the sample delay value (D), the upward sample rate (L), and the downward sample rate (M) may be adjusted to satisfy the condition 2nLD/M≠m (here, m=integer). Here, n represents the position index of the frequency band of the radio signal, and m represents an arbitrary integer.

9 is a block diagram showing a receiver according to a third embodiment of the present invention. Referring to FIG. 9, a receiver 400 according to a third embodiment of the present invention may include an antenna 410, a band filter 420, a low noise amplifier 430, and a sub-sampling block 440. Here, it will be well understood that a digital up/down converter (not shown) positioned at the rear end of the sub-sampling block 440 may be added as necessary. Here, the sub-sampling block 440 includes a first path for providing sample delay and sample rate adjustment for the baseband signal, and a second path for providing only a gain for the baseband signal. Through this configuration, the sub-sampling block 440 can effectively remove aliasing occurring in the baseband.

The antenna 410 receives a radio frequency signal (ARF) transmitted wirelessly and transmits it to the band filter 420. The band filter 420 passes a signal of a specific bandwidth in the received radio frequency signal (ARF). The band filter 420 may be designed such that the pass band is limited to a predetermined bandwidth (B), and removes noise outside the signal band. In an exemplary embodiment, the pass band and pass bandwidth B set in the band filter 420 may have a fixed value or may be adjusted to different values. The low noise amplifier 430 amplifies the signal selected by the band filter 420 by a predetermined gain. The signal amplified by the low noise amplifier 430 will be delivered to the sub-sampling block 440 including one ADC 441.

The sub-sampling block 440 includes an analog-to-digital converter 441, a sample delay 442, a first sample rate converter 443, a first digital filter 444, a second digital filter 446, and a second sample. A rate converter 445 and an adder 447 are included. Here, the baseband signal DR output from the analog-to-digital converter 441 is divided into a first path providing sample delay and sample rate adjustment, and a second path providing a gain of a constant C for the signal. The first path through which the baseband signal DR is transmitted includes a sample delay 442, a first sample rate converter 443, and a first digital filter 444. The second path includes a second sample rate converter 445 and a complex multiplier 445 to provide a gain C.

The first sample rate converter 443 may be adjusted to have a sample rate of L/M times the sample rate f _s of the baseband signal DR. Therefore, when the baseband signal DR of the sample rate f _s passes through the sample delay 442 and the first sample rate converter 443, it has a fractional delay of a multiple of D×L/M. Will be Here, by adjusting the sample rate f _s , the sample delay value D, the upward sample rate L, and the downward sample rate M, the elimination occurring in the first path can be effectively removed. The fractional delay effect occurring in the first path according to the asymmetric delay effect by the sample delay unit 442 plays a key role in designing a filter to remove elimination.

10 is a block diagram showing a receiver according to a fourth embodiment of the present invention. Referring to FIG. 10, the receiver 500 according to the fourth embodiment of the present invention further includes a synchronization delay 545 for synchronizing delays between paths in the sub-sampling block 440 of FIG. 9.

The synchronization delayer 545 delays the second path signal by a time delay due to digital filtering of the first path signal by the first digital filter 544. Accordingly, time synchronization between the first path signal and the second path signal can be achieved.

The receiver 500 may include an antenna 510, a band filter 520, a low noise amplifier 530, and a sub-sampling block 540. Here, the sub-sampling block 540 includes a first path for providing sample delay and sample rate adjustment for the baseband signal, and a synchronization delay 545 provided for time delay and synchronization due to digital filtering of the first path. ) And includes a second path. Through this configuration, the sub-sampling block 540 can effectively remove aliasing occurring in the baseband through a simple structural change of the receiver 400 of FIG. 9.

11 is a block diagram showing a reconfigurable reconfigurable sub-sampling apparatus capable of applying various characteristics of a receiver of the present invention. Referring to FIG. 11, the reconfigurable sub-sampling device 600 includes a variable sample delay 610, a first variable sample rate converter 620, a second variable sample rate converter 640, and a first variable digital filter 630. ), a second variable digital filter 650, an adder 660, and an embedded processor 670.

The embedded processor 670 includes a variable sample delay 610, a first variable sample rate converter 620, a second variable sample rate converter 640, and a first variable digital filter 630 as parameters corresponding to the set operating conditions. , A second variable digital filter 650 may be set. That is, the embedded processor 670 may adjust the sample delay value D of the variable sample delay 610. The embedded processor 670 may adjust the upward or downward sample rates L and M of the first variable sample rate converter 620 and the second variable sample rate converter 640. The embedded processor 670 performs interpolation and decimation filter coefficients (ID Filter Coefficient 1, ID Filter Coefficient 2) of each of the first variable sample rate converter 620 and the second variable sample rate converter 640 according to operating conditions. Can be adjusted. The embedded processor 670 may adjust filter coefficients (Filter Coefficient 1, Filter Coefficient 2) of the first variable digital filter 630 and the second variable digital filter 650 according to operating conditions.

The reconfigurable sub-sampling device 600 may be configured as a digital processor device and may be flexibly applied to receiving devices of various frequencies and various communication methods. Accordingly, the operating characteristics of the sub-sampling blocks described in the first to fourth embodiments described above may be implemented through parameter adjustment of the reconfigurable sub-sampling device 600.

The reconfigurable sub-sampling device 600 according to the present invention may be configured using commercial digital devices such as a field-programmable gate array (FPGA) or a digital signal processor (DSP). First, the embedded processor 670 calculates the frequency band position index n of the radio signal. As described above, the frequency band position index n can be obtained using the relationship n=round(f _c /f' _s ). Next, the embedded processor 670 satisfies 2nLD/M≠m (here, m=integer), or the sample delay value (D), the upward sample rate so that C is 2 or a value close to 2 in Equation 23. (L), the downward sample rate (M) will be calculated and stored.

When the sample rate (f _s ), the sample delay value (D), the upward sample rate (L), and the downward sample rate (M) are determined, the embedded processor 670 refers to the sample delay value (D). We will set a sample delay value of 610. Subsequently, the embedded processor 670 sets the sample rates of the first variable sample rate converter 620 and the second variable sample rate converter 640 based on the calculated upward sample rate (L) and downward sample rate (M). will be.

In addition, the embedded processor 670 uses the calculated sample delay value (D), an upward sample rate (L), a downward sample rate (M), and a frequency band position index (n) to the first variable digital filter 630. , Will reconstruct the characteristics of the second variable digital filter 650. That is, the embedded processor 670 will set the variable digital filters 630 and 650 by calculating filter coefficients (Filter Coefficient 1, Filter Coefficient 2) corresponding to the calculated filter characteristics.

Lastly, the embedded processor 670 includes an interpolation and decimation filter coefficient of the first variable sample rate converter 620 and the second variable sample rate converter 640 operating at the sample rate f _s . Calculate ID Filter Coefficient 2). The first variable sample rate converter 620 and the second variable sample rate converter 640 perform L-1 zero insertions between samples according to an upward sample rate L previously set for the input signal. After that, interpolation filtering is performed. The interpolation filtered signal passes through the decimation filter and then deletes one sample for each M sample according to the preset downlink sample rate (M), thereby converting the sample rate of the input signal into L/M times.

According to the reconfigurable sub-sampling apparatus 600 according to the present invention, it is possible to receive a wideband RF signal located in an arbitrary frequency band without changing hardware. In order to receive a wideband RF signal located in an arbitrary frequency band without hardware change, the signal bandwidth (B), sample rate of ADC (f _s ), sample delay value (D), and sample rate conversion ratio (L/M) Change the filter coefficient value of the digital filter to be designed.

12 is a flowchart briefly showing a method of operating the reconfigurable sub-sampling device 600 of FIG. 11. Referring to FIG. 12, the reconfigurable sub-sampling apparatus 600 may perform the reconfiguration operation of the present invention during initialization or reset operation of a receiver.

In step S110, the embedded processor 670 calculates a sample delay value (D), an upward sample rate (L), and a downward sample rate (M). The embedded processor 670 includes a sample delay value (D), an upward sample rate (L), and a downward sample rate so that C in Equation 23 is 2nLD/M≠m (here, m = integer) Calculate and store (M).

In step S120, the reconfigurable sub-sampling device 600 will calculate the frequency band position index n by referring to the carrier frequency fc and the sample rate f _'s of the sample rate converter output. It can be calculated as the frequency band position index n=round(f _c /f' _s ). This operation may be performed by the embedded processor 670.

In step S130, the embedded processor 670 will set the delay size of the variable sample delay 610 to the previously determined sample delay value D. For example, the embedded processor 670 may set the size of the delay tap of the variable sample delay 610.

In step S140, the embedded processor 670 will set the sample rates of the first variable sample rate converter 620 and the second variable sample rate converter 640 to the determined upward sample rate (L) and downward sample rate (M). . The upward and downward sample rates L and M of the first variable sample rate converter 620 and the second variable sample rate converter 640 may be provided with the same value, respectively.

In step S150, the embedded processor 670 sets characteristics of the first variable digital filter 630 and the second variable digital filter 650. That is, the embedded processor 670 will set the variable digital filters 630 and 650 by calculating filter coefficients (Filter Coefficient 1, Filter Coefficient 2) corresponding to the calculated filter characteristics. The embedded processor 670 uses a sample delay value (D), an upward sample rate (L), a downward sample rate (M), and a frequency band position index (n) to remove the first variable digital filter ( Filter coefficients of 630 and the second variable digital filter 650 will be determined. In addition, the first variable digital filter 630 and the second variable digital filter 650 are set with the determined filter coefficients (Filter coefficient 1 and Filter coefficient 2).

In step S160, the embedded processor 670 performs interpolation and decimation filter coefficients of the first variable sample rate converter 620 and the second variable sample rate converter 640 operating at the sample rate f _s . , ID Filter Coefficient 2) is calculated. The first variable sample rate converter 620 and the second variable sample rate converter 640 perform L-1 zero insertions between samples according to an upward sample rate L previously set for the input signal. Interpolation filtering must be performed later. The interpolation filtered signal passes through the decimation filter and then deletes one sample for every M sample according to the preset downlink sample rate (M), thereby converting the sample rate of the input signal into L/M times. The embedded processor 670 will set the first variable sample rate converter 620 and the second variable sample rate converter 640 with the determined interpolation and decimation filter coefficients (ID Filter Coefficient 1, ID Filter Coefficient 2).

When the setting of all the sub-sampling blocks is completed through the steps described above, the reconfigurable sub-sampling apparatus 600 processes the received signal through the antenna and provides it as a baseband signal.

So far, the present invention has been looked at around its preferred embodiments. Those of ordinary skill in the art to which the present invention pertains will be able to understand that the present invention can be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered from an illustrative point of view rather than a limiting point of view. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

On the other hand, it is obvious to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or technical spirit of the present invention. In view of the foregoing, if modifications and variations of the present invention fall within the scope of the following claims and equivalents, it is believed that the present invention includes variations and modifications of this invention.

Claims (19)

An analog-to-digital converter for converting an analog wireless signal into a digital baseband signal; And
And a sub-sampling block for separating and processing the digital baseband signal into a first path signal and a second path signal, and extracting a complex baseband signal using a relative sample delay difference between the first and second path signals But,
The first path signal is an up-sampled, delayed, and down-sampled signal of the digital baseband signal, and the second path signal is filtered without adjusting a sample rate for the digital baseband signal. The method of claim 1,
The sub-sampling block is:
A first sample rate converter for varying a sample rate of the digital baseband signal;
A sample delay for delaying the output of the first sample rate converter by at least one sample unit;
A second sample rate converter for varying a sample rate of an output from the sample delay and outputting the first path signal;
A first digital filter filtering the first path signal;
A second digital filter filtering the second path signal; And
And an adder configured to add the filtering result of the first digital filter and the filtering result of the second digital filter to output the complex baseband signal. The method of claim 2,
And the adder subtracts the filtering result of the second digital filter from the filtering result of the first digital filter and outputs the complex baseband signal. The method of claim 2,
The relative delay difference between the first path signal and the second path signal is one of a sample rate of the analog-to-digital converter, a delay size of the sample delay, and a sampling conversion rate of the first sample rate converter and the second sample rate converter. A radio signal receiver determined by at least one. The method of claim 2,
The first sample rate converter is a sample rate up converter for increasing the sample rate of the analog-to-digital converter, and the second sample rate converter is a sample rate down converter for lowering the sample rate of the output from the sample delay. Wireless signal receiver. The method of claim 2,
The filter coefficients of each of the first digital filter and the second digital filter are the carrier frequency of the analog radio signal, the frequency band position index of the analog radio signal, the sample rate of the analog-to-digital converter, and the delay of the sample delay A wireless signal receiver determined by at least one of a size and conversion ratios (N) of the second sample rate converter. The method of claim 6,
The sample rate (fs), the delay size (D) of the sample delay, and the sample conversion ratio (N) by the second sample converter are set to satisfy 2nD/N≠m, where n is an analog radio signal Is a frequency band position index of, and m is an integer. The method of claim 2,
The first digital filter and the second digital filter
Equation

, Equation

, Equation

, And the equation

It is determined to satisfy at least one of the equations,
remind

Is the spectrum of the output signal of the adder, the

Is the spectrum of the first digital filter output signal, the

Is the spectrum of the second digital filter output signal, the R _- (f) is a sound frequency spectrum, the R ₊ (f) of the digital baseband signal is a wireless corresponding to the amount of the frequency spectrum of the digital baseband signal Signal receiver. The method of claim 2,
The second digital filter is a wireless signal receiver comprising a complex multiplier that amplifies the digital baseband signal with a gain of a specific magnitude. The method of claim 9,
A wireless signal receiver further comprising a synchronous delay for delaying the digital baseband signal by a specific delay time and providing it to the complex multiplier. An analog-to-digital converter for converting an analog wireless signal into a digital baseband signal; And
And a sub-sampling block for separating and processing the digital baseband signal into a first path signal and a second path signal, and extracting a complex baseband signal using a relative sample delay difference between the first and second path signals But,
The first path signal is an up-sampled, delayed, and down-sampled signal of the digital baseband signal, and the second path signal is a signal obtained by adjusting a sample rate without sample delaying the digital baseband signal. receiving set. The method of claim 11,
The sub-sampling block is:
A sample delay for delaying the digital baseband signal in units of at least one sample;
A first sample rate converter for varying a sample rate of an output from the sample delay and outputting the first path signal;
A first digital filter filtering the first path signal;
A second sample rate converter for varying a sample rate of the digital baseband signal and outputting the second path signal;
A second digital filter filtering the second path signal; And
And an adder configured to add the filtering result of the first digital filter and the filtering result of the second digital filter to output the complex baseband signal. The method of claim 12,
And the adder subtracts the filtering result of the second digital filter from the filtering result of the first digital filter and outputs the complex baseband signal. The method of claim 12,
The relative delay difference between the first path signal and the second path signal is at least one of a sample rate of the analog-to-digital converter, a delay size of the sample delay, and a sampling conversion rate of the first sample rate converter and the second sample rate converter. Radio signal receiver determined by one. The method of claim 12,
The filter coefficients of each of the first digital filter and the second digital filter may include a carrier frequency of the analog radio signal, a frequency band position index of the analog radio signal, a sample rate of the analog-to-digital converter, and a delay of the sample delay. A wireless signal receiver determined by a size and at least one of conversion ratios (L/M) of the first sample rate converter and the second sample rate converter. The method of claim 15,
The sample rate (fs), the delay size (D) of the sample delay, and the conversion ratio (L/M) of the first sample rate converter and the second sample rate converter are set to satisfy 2nLD/M≠m. Wherein n is a frequency band position index of an analog radio signal, and m is an integer. The method of claim 12,
The first digital filter and the second digital filter
Equation

, Equation

, Equation

, And the equation

It is determined to satisfy at least one of the equations,
remind

Is the spectrum of the output signal of the adder, the

Is the spectrum of the first digital filter output signal, the

Is the spectrum of the second digital filter output signal, the R _- (f) is a sound frequency spectrum, the R ₊ (f) of the digital baseband signal is a wireless corresponding to the amount of the frequency spectrum of the digital baseband signal Signal receiver. The method of claim 12,
The second digital filter is a wireless signal receiver comprising a complex multiplier that amplifies the second path signal with a gain of a specific magnitude. The method of claim 18,
A radio signal receiver further comprising a synchronous delay delaying the second path signal by a specific delay time and providing the delayed signal to the complex multiplier.

Images