KR102182718B1 - Memory device, the control method of the memory device and the method for controlling the memory device - Google Patents

Abstract

The present invention is an asynchronous NAND-type memory device, comprising: a circuit that performs an operation based on a signal, a first pin that obtains an operation control signal, a second pin that outputs a data output reference signal, and outputs in synchronization with a data output reference signal. A third pin is included, wherein the circuit acquires an operation control signal that transitions from the first time point to the second time point after the first time point when the memory device enters the ready state from the external device, and the second pin is in advance from the second time point. A memory device is provided to output a data output reference signal that transitions at a third time point after a predetermined time interval, and output data in synchronization with an operation control signal that periodically transitions from the third time point to the third pin.

Description

A memory device, a method of controlling a memory device, and a method of controlling a memory device {MEMORY DEVICE, THE CONTROL METHOD OF THE MEMORY DEVICE AND THE METHOD FOR CONTROLLING THE MEMORY DEVICE}

The present invention relates to a memory device, a method of controlling a memory device, and a method of controlling a memory device, and more particularly, in an asynchronous NAND type memory device, a memory device having a higher data processing speed, a method of controlling a memory device, and a memory It relates to a method of controlling the device.

A semiconductor memory device is used to store data and is a memory device implemented using semiconductors such as silicon, germanium, and gallium arsenide. Semiconductor memory devices are generally classified into volatile memory and nonvolatile memory devices.

Volatile memory is a memory device in which stored data is destroyed when power supply is cut off. Volatile memory includes SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM), etc. Nonvolatile memory includes ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electromically Programmable ROM), Flash memory devices. Among them, flash memory devices are largely classified into a NOR type and a NAND type.

An interface of a control device for reading, writing, and erasing data using such a NAND flash memory device is widely used. However, as the specifications of the processor are gradually improved and the continuous development of software technology, development of a memory device and an interface that enables faster data processing is required.

An object of the present invention is to provide a memory device, a method for controlling the memory device, and a method for controlling the memory device.

Another object of the present invention is to provide an asynchronous NAND type memory device, a method of controlling an asynchronous NAND type memory device, and a method of controlling a memory device.

Another object of the present invention is to provide a memory device having an improved data processing speed, a method for controlling the memory device, and a method for controlling the memory device.

According to an aspect of the present invention, in an asynchronous NAND type memory device, a circuit that performs an operation based on a signal obtained from an external device, a first pin that obtains an operation control signal from an external device, and a data output reference to the external device A memory device including a second pin outputting a signal and a third pin outputting data to an external device in synchronization with a data output reference signal is provided.

In this case, the circuit acquires an operation control signal in which the first pin transitions from the external device to the second time point after the first time point when the memory device enters the ready state, and then periodically transitions with a first cycle, and the second The pin outputs a data output reference signal that transitions at a third time point after a predetermined time interval from the second time point, but the data output reference signal is output in synchronization with an operation control signal that periodically transitions, and the third pin It may be provided to output data in synchronization with an operation control signal that periodically transitions from the time point.

According to another aspect of the present invention, there is provided a method of controlling a NAND type memory device, the step of outputting an operation control signal to the memory device when the memory device enters a ready state at a first time point (the operation control signal is Thereafter, it transitions at a second time point, and then periodically transitions with a first period), obtaining a data output reference signal from the memory device in response to outputting the operation control signal to the memory device (data output reference signal Transitioning from the second time point to a third time point after a predetermined time interval, and outputting in synchronization with an operation control signal that periodically transitions) and obtaining data output in synchronization with the data output reference signal from the third time point A method of controlling a memory device including a is provided.

According to another aspect of the present invention, a method for controlling a NAND type memory device is provided, comprising the steps of: the memory device enters a ready state and obtains an operation control signal from an external device (the operation control signal is the memory device enters the ready state. Transitions from the first point in time to the second point in time), outputting a data output reference signal to the external device in response to acquiring the operation control signal from the external device (the data output reference signal is a predetermined time from the second time point) A method of controlling a memory device comprising the step of outputting data in synchronization with a data output reference signal and a transition at a third time point after the interval is provided.

The solution means of the subject of the present invention is not limited to the above-described solution means, and solutions not mentioned will be clearly understood by those of ordinary skill in the art from the present specification and the accompanying drawings. I will be able to.

According to the present invention, an asynchronous NAND type memory device, a control method of an asynchronous NAND type memory device, and a method of controlling a memory device can be provided.

According to the present invention, a memory device having an improved data processing speed, a method of controlling the memory device, and a method of controlling the memory device can be provided.

According to the present invention, a memory device having enhanced data processing stability, a method of controlling the memory device, and a method of controlling the memory device may be provided.

The effects of the present invention are not limited to the above-described effects, and effects that are not mentioned will be clearly understood by those of ordinary skill in the art from the present specification and the accompanying drawings.

1 illustrates a memory system according to an embodiment of the present invention.
2 is a schematic diagram of a memory device according to an embodiment of the present invention.
3 is a block diagram illustrating a configuration of a memory device according to an embodiment of the present invention.
4 is a diagram for explaining timing of main signals in a memory device according to an embodiment of the present invention.
5 is a diagram for describing timing of main signals in a memory device according to an embodiment of the present invention.
6 is a flowchart illustrating a method of controlling a memory device according to an embodiment of the present invention.
7 is a flowchart illustrating a method of controlling a NAND type memory device according to an embodiment of the present invention.
8 is a diagram for explaining timing of main signals in a memory device according to an embodiment of the present invention.
9 is a diagram illustrating timing of main signals in a memory device according to an embodiment of the present invention.
10 is a diagram for explaining timing of main signals in a memory device according to an embodiment of the present invention.
11 is a block diagram illustrating a system in which a memory device according to an exemplary embodiment is applied to an SSD.

The above objects, features and advantages of the present invention will become more apparent through the following detailed description in conjunction with the accompanying drawings. However, in the present invention, various changes may be made and various embodiments may be provided. Hereinafter, specific embodiments will be illustrated in the drawings and described in detail.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and elements or layers are referred to as "on" or "on" of other elements or layers. This includes not only directly above other components or layers, but also when other layers or other components are interposed in the middle. Throughout the specification, the same reference numerals represent the same elements in principle. In addition, components having the same function within the scope of the same idea shown in the drawings of each embodiment will be described with the same reference numerals.

If it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. In addition, numbers (eg, first, second, etc.) used in the description of the present specification are merely identification symbols for distinguishing one component from another component.

In addition, the suffixes "module" and "unit" for constituent elements used in the following description are given or used interchangeably in consideration of only the ease of preparation of the specification, and do not themselves have distinct meanings or roles.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -A hardware device specially configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of the program instructions include not only machine language codes such as those produced by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.

Hereinafter, a nonvolatile memory device and a control method thereof will be described. Specifically, the nonvolatile memory device and the control method thereof according to the present invention can be applied to a nonvolatile memory device using a double data rate (DDR) method such as a toggle NAND flash memory device.

In toggle-type NAND flash memory devices and systems, it is possible to operate using both rising and falling edges of a signal. In the case of a toggle-type NAND flash memory device, the erase and read are the same as the SDR (Single Data Rate)-type NAND flash memory devices. Three commands are used: write. However, a bidirectional DQS pin port is additionally used as a data strobe (DQS) pin.

First, a system including a memory device and a control device according to an embodiment of the present invention will be described.

1 illustrates a memory system according to an embodiment of the present invention.

Referring to FIG. 1, a memory system according to an embodiment of the present invention may include a memory device 100 and a control device 200.

The control device 200 may perform a control operation on the memory device 100. The control device 200 may include a NAND interface 210. The NAND interface 210 may output a signal to the NAND memory device 100 or receive a signal from the NAND memory device 100 to control the operation of the NAND memory device 100.

The control device 200 may control write (or program), read, and erase operations for the memory device 100 by providing an address, a command, and a control signal to the memory device 100. Specifically, the control device 200 may output a chip enable (CE) signal to the memory device 100, output a command latch enable (CLE) signal, and output an address latch enable (ALE) signal. have. Also, the control device 200 may output a read enable (RE) signal and a write enable (WE) signal to the memory device 100. Also, the control device 200 may obtain a ready/busy (R/B) signal from the memory device 100.

When performing a write or read operation on the memory device 100, the control device 200 transmits data to the memory device 100 or receives data from the memory device 100 through a data pin port DQ. can do. In addition, when performing a write or read operation on the memory device 100, the control device 200 transmits a data strobe (DQS) to the memory device 100 through a data strobe (DQS) port (or DQS pin port). A signal (or a DQS signal) may be transmitted or a data strobe (DQS) signal (or a DQS signal) may be received from the memory device 100.

The memory device 100 may receive a chip enable (CE) signal from the control device 200, a command latch enable (CLE) signal, and an address latch enable (ALE) signal. The memory device 100 may receive a read enable (RE) signal and a write enable (WE) signal from the control device 200. Also, the control device 200 may output a ready/busy (R/B) signal to the memory device 100.

2 is a schematic diagram of a memory device 100 according to an embodiment of the present invention.

Referring to FIG. 2, the memory device 100 according to an embodiment of the present invention may include a plurality of pins. As a specific example, the memory device 100 according to an embodiment of the present invention may include an R/B pin, a CE pin, a CLE pin, an ALE pin, a WE pin, a RE pin, a DQ pin, and a DQS pin. However, this is only an example of the memory device 100, and the memory device 100 disclosed in the present invention is not limited thereto. The memory device 100 may further include additional pins or may be provided by omitting some pins.

The R/B pin may externally output a ready/busy (R/B) signal indicating the state of the memory device 100. The R/B pin may externally output an R/B signal indicating a ready (ie, ready state) or busy state of the memory device 100.

The CE pin may receive a chip enable (CE) signal that activates the memory device 100.

The CLE pin may externally receive a command latch enable (CLE) signal indicating that data input through the data input/output pins DQ0 to DQ7 is a command.

The ALE pin may receive an address latch enable (ALE) signal from an external device indicating that data input through the data input/output pins DQ0 to DQ7 is an address.

The WE pin may receive a write enable (WE) signal. For example, the write enable (WE) signal may control latching of commands and addresses.

The RE pin can receive a read enable (RE) signal. For example, the read enable signal may enable continuous data output.

The DQ pin can either output or receive data. A plurality of DQ pins may be provided. For example, the memory device 100 may include DQ0 to DQ7 as 8-bit ports.

The DQS pin may output or receive a data strobe (DQS) signal indicating an effective window of data.

3 is a block diagram illustrating a configuration of a memory device according to an embodiment of the present invention.

3, a memory device 100 according to an embodiment of the present invention includes a memory cell array 101, an address decoder 103, a read and write circuit 105, a data input/output circuit 107, and a control logic. Circuit 109 may be included.

The memory cell array 101 may be connected to the address decoder 103 through a word line WL, and may be connected to the read and write circuit 105 through a bit line BL. The memory cell array 101 is implemented including a plurality of memory cells. The memory cell array 101 may be configured to store one or more bits per cell.

The address decoder 103 may receive an address ADDR from the outside. The address decoder 103 may be connected to the memory cell array 101 through a word line WL. The address decoder 103 may operate in response to the control of the control logic circuit 109.

The address decoder 103 may decode a row address among the received addresses ADDR and select a word line WL based thereon. The address decoder 103 may decode a column address among the received addresses ADDR. The decoded column address may be transferred to the read and write circuit 105.

The read and write circuit 105 may be connected to the memory cell array 101 through a bit line BL, and may be connected to the data input/output circuit 140 through a data line DL. The read and write circuit 105 may operate under the control of the control logic circuit 109. The read and write circuit 105 may receive the decoded column address from the address decoder 103 and use the decoded column address to select the bit line BL.

According to an embodiment, the read and write circuit 105 may receive data from the data input/output circuit 107 and input the received data to the memory cell array 101. Alternatively, the read and write circuit 105 may acquire data from the memory cell array 101 and transmit the acquired data to the data input/output circuit 107. The read and write circuit 105 may acquire predetermined data from one region of the memory cell array 101 and store the data in another region of the memory cell array 101. For example, the read and write circuit 105 may perform a copy-back operation.

According to another embodiment, the read and write circuit 105 may include detailed components such as a page buffer (or register), a column select circuit, a sense amplifier, and a write driver.

The data input/output circuit 107 may be connected to the read and write circuit 105 through the data line DL. The data input/output circuit 107 may operate under the control of the control logic circuit 109. The data input/output circuit 107 may exchange data DATA with an external device. The data input/output circuit 107 transfers data acquired from the outside to the read and write circuit 105 through the data line DL, or transmits data DATA through the data line DL transmitted from the read and write circuit. Can be output externally. For example, the data input/output circuit 107 may include a data buffer or the like.

The control logic circuit 109 may be connected to the address decoder 120, the read and write circuit 105, and the data input/output circuit 107. The control logic circuit 109 may be configured to control all operations of the memory device 100. The control logic circuit 109 may operate based on the control signal CTRL received from the outside.

The control logic circuit 109 may include a program/erase count counter that counts the number of programs/erases per block of the memory device 100. The program/erase count counter may be implemented in a digital circuit, an analog circuit, or a complex form. The program/erase count counter may be provided by software driven by the control logic circuit 109 or a combination of software and hardware.

4 is a diagram for explaining timing of main signals in the memory device 100 according to an embodiment of the present invention. Specifically, FIG. 4 illustrates a timing relationship between main signals when the memory device 100 receives a command signal and an address signal and performs a data read operation based thereon.

Referring to FIG. 4, in a memory device according to an embodiment of the present invention, in a state in which a chip enable (CE) signal is activated (polled) and a command latch enable (CLE) signal is activated (rised), the memory device is A command (eg, 00h) may be input from the outside (DQ signal). In addition, when the chip enable (CE) signal is activated (polled), the command latch enable (CLE) signal is deactivated (polled), and the address latch enable (ALE) is activated (rising), the memory device is Address can be input (DQ signal). The memory device may receive an address and receive a command (eg, 30h) again. In this case, the write enable (WE) signal may periodically transition between the logic high and the logic low with a period of tWC.

Referring to FIG. 4, when a memory device receives an address and a command, a ready/busy (R/B) signal may enter a busy state (polling). The ready/busy (R/B) signal enters the busy state after tWB from the time when the last command is input, remains in the busy state for tR, and may be changed back to the ready state (rising). In the busy state, the memory device can prepare for an operation according to a command. In a busy state, a chip enable (CE) signal may be in an inactive state, and a command latch enable (CLE) signal and an address latch enable (ALE) signal may be active.

Referring to FIG. 4, after a memory device enters a ready state and after a predetermined time (tCR, tCLR, or tAR), a read enable signal RE may be input. The read enable (RE) signal may be maintained in a transitioned state for a predetermined time (eg, tRPRE). tRPRE may be a read preamble time. When the read primble time elapses, the read signal may periodically transition between logic high and logic low with a period of tRC. The read enable (RE) signal may be maintained for a predetermined time after periodically transitioning for a predetermined time. tRPST may be a read postamble time. tRPSTH may refer to the lead post-imble hold time. The parameter tRR may represent a time from when the memory device enters the ready state until data is output. The read enable (RE) signal may be a differential pair signal (RE, nRE).

Referring to FIG. 4, the memory device may enter a ready state and output a data strobe (DQS) signal after a predetermined time interval tDQSRE from a time when a read enable (RE) signal transitions after a predetermined time. The data strobe DQS signal may be output after being delayed by tDQSRE from the read enable signal RE. That is, the data strobe (DQS) signal is delayed by tDQSRE from the read enable (RE) signal and transitions, and a waveform that is delayed by tDQSRE from the read enable (RE) signal may be formed. The data strobe (DQS) signal may be a differential pair signal.

Referring to FIG. 4, the memory device may output a data input/output (DQ) signal in synchronization with a data strobe (DQS) signal. In synchronization with the data strobe (DQS) signal, the memory device may output the data input/output (DQ) signal by delaying tDQSRE from the read enable (RE) signal. In other words, the data input/output (DQ) signal and/or the data strobe (DQS) signal may be output asynchronously with the read enable (RE) signal.

tCSD may be a hold time from when the chip enable signal is deactivated to a time point at which the command latch enable (CLE) signal, the address latch enable (ALE) signal, and the write enable (WE) signal transition.

5 is a diagram for describing timing of main signals in a memory device according to an embodiment of the present invention. Specifically, in FIG. 4, a case in which the memory device receives a command signal and an address signal and starts a data read operation based on the inputs has been described, but in FIG. 5, a case in which the reading operation is continuously performed will be described.

Hereinafter, the signals shown in FIG. 5 will be described with reference to FIG. 4. Hereinafter, the matters described in FIG. 4 are similarly applied to each signal unless otherwise specified.

Referring to FIG. 5, in a memory device according to an embodiment of the present invention, a chip enable (CE) signal is activated (polled), a command latch enable (CLE) signal is deactivated (polled), and an address latch enable. In a state in which the (ALE) signal is deactivated (polled) and the write enable (WE) signal is deactivated (rised), a read enable (RE) signal may be received.

Referring to FIG. 5, a read enable (RE) signal is maintained in a logic or logic high state for a read primble time, and may transition periodically thereafter with a cycle of tRC. In this case, the data strobe (DQS) signal may be output as a waveform delayed by tDQSRE compared to the read enable (RE) signal. In other words, the data strobe (DQS) signal may be output asynchronously with the read enable (RE) signal.

Referring to FIG. 5, a data input/output (DQ) signal may be output in synchronization with a data strobe (DQS) signal, that is, delayed by tDQSRE from a read enable signal (RE). The data input/output (DQ) signal may sequentially output data (D0 to Dn) from the time when tDQSRE elapses and tRPRE elapses.

tDQSQ may indicate a skew between a data input/output (DQ) signal and a data strobe (DQS) signal. The parameter tQH may be an output hold time of a data strobe (DQS) signal, that is, a hold time of a data strobe (DQS) signal output from a memory device to an external device. The parameter tQHS may indicate a hold skew factor of a data strobe (DQS) signal. The parameter tDVW may represent a valid window of data output as a data input/output (DQ) signal.

Hereinafter, a memory device and a control method thereof according to another embodiment of the present invention will be described. Specifically, in the asynchronous NAND flash memory device, a memory device and a control method thereof in which an operation signal output from the memory device is synchronized with an operation control signal input to the memory device will be described.

Meanwhile, a method of controlling a memory device disclosed in this specification may be performed by a control device (eg, a memory controller).

A memory device according to an embodiment of the present invention is an asynchronous NAND-type memory device, comprising: a circuit that performs an operation based on a signal obtained from an external device, a first pin that receives an operation control signal from an external device, and data to an external device. A second pin for outputting an output reference signal and a third pin for outputting data to an external device in synchronization with the data output reference signal.

At this time, the circuit that performs an operation based on the signal obtained from the external device transitions from the first pin to the second time after the first time point when the memory device enters the ready state from the external device, and has a first cycle thereafter. It may be provided to receive an operation control signal that periodically transitions.

The memory device further includes a fourth pin for outputting a status signal indicating a ready state and a busy state of the memory device, and indicating a state of the memory device, that is, a ready state (ready state) or a busy state through the fourth pin. Status signals can be output. The fourth pin may be an R/B pin that outputs a ready busy signal. Alternatively, the memory device may obtain a command signal input from an external device and output a status signal indicating a state of the memory device in response thereto. In this case, the command signal may be a request for a state of the memory device. The command signal can be received through the DQ pin.

In addition, a circuit that performs an operation based on a signal obtained from an external device outputs a data output reference signal that transitions from a second pin to a third time point after a predetermined time interval from the second time point, but the data output reference signal is It may be provided to be output in synchronization with an operation control signal that periodically transitions.

In addition, a circuit that performs an operation based on a signal obtained from an external device may be provided to output data in synchronization with an operation control signal in which the three pins are periodically transitioned from the third time point.

In the circuit according to the present embodiment, the data output reference signal has a periodic time difference that does not exceed a predetermined reference value at the same time point as the time point at which the periodically transitioning motion control signal transitions or from the time point at which the motion control signal transitions. It can be implemented to transition to. In other words, a latency, which is a difference between a transition point of an operation control signal and a transition point of a data output reference signal, may be defined to have only a maximum value. More specifically, tDQSRE may have a value between 0 and 25 ns as a difference between the transition point of the operation control signal and the transition point of the data output reference signal. In this embodiment, the first pin may be an RE pin that receives a read enable (RE) signal. The second pin may be a DQS pin that outputs a data strobe (DQS) signal. The third pin may be a DQ pin that outputs data.

The circuit according to the present embodiment outputs a ready signal indicating that the memory device has entered a ready state through the R/B pin at a first time point, and in response to outputting the ready signal, the read enable ( RE) When the signal is acquired and the read enable (RE) signal transitions from the first time point to the second time point, the data strobe (DQS) signal is prepared to transition from the second time point to a third time point after a predetermined time interval. Can be.

The circuit may be provided such that the first pin outputs an operation control signal that first transitions from the second point in time to the first point in time, and the second pin outputs a data output reference signal that first transitions from the third point in time after the first point in time.

The predetermined time, which is an interval between the second and third viewpoints, may be predetermined as an integer multiple of the first period.

The data may be output in alignment with the edge of the motion control signal. For example, a rising edge and a falling edge of the data input/output signal may occur when a rising edge and a falling edge signal of the operation control signal occur, respectively.

In the case of using the memory device according to the present embodiment, when data is read, a data strobe (DQS) signal and a data input/output (DQ) signal output from the memory device to the control device are read enable (RE) output from the control device. By synchronizing with the signal, signal management on the control device side is more difficult than when the data strobe (DQS) signal and the data input/output (DQ) signal have a delay waveform of the lead enable (RE) signal and are asynchronous to the read enable (RE) signal. It is easy, and thus the processing speed of data can be improved.

A method of controlling a memory device according to an embodiment of the present invention may include outputting an operation control signal to the memory device, obtaining an operation reference signal from the memory device, and obtaining an operation signal from the memory device. have.

The outputting of the operation control signal may include outputting the operation control signal to the memory device when the memory device enters the ready state at the first time point. In this case, the operation control signal may transition from the first point in time to the second point in time, and then periodically transition between the logic low and the logic high with a first period thereafter. The operation control signal may be a read enable (RE) signal.

Acquiring the operation reference signal may include obtaining the operation reference signal from the memory device in response to outputting the operation control signal to the memory device. The operation reference signal may transition from the second point in time to a third point in time after a predetermined time interval, and may periodically transition between the logic low and the logic high. The operation reference signal may be a data output reference signal. The operation reference signal may be a data strobe (DQS) signal.

Acquiring the operation signal may further include obtaining data output in synchronization with the operation reference signal from the third time point. The operation signal may be a data input/output (DQ) signal.

6 is a flowchart illustrating a method of controlling a memory device according to an embodiment of the present invention. The method of controlling the memory device illustrated in FIG. 6 will be described in more detail below with reference to FIGS. 8 to 10.

6, a method of controlling a NAND type memory device according to an embodiment of the present invention includes outputting a command signal to the memory device (S110), outputting an operation control signal to the memory device (S130), It may include obtaining an output reference signal from the memory device (S150) and obtaining data (S170).

The step of outputting the command signal to the memory device (S110) may include outputting a data output (ie, data read) command signal.

The step of outputting the operation control signal to the memory device (S130) may further include outputting the operation control signal to the memory device when the memory device enters the ready state at the first time point. In this case, the motion control signal may transition from the first point in time to the second point in time, and thereafter, may transition periodically with a first period. The first point in time may be a point in time at which the R/B signal is converted (rised) from the busy state to the ready state.

The outputting of the motion control signal may further include outputting a motion control signal that first transitions from the second point in time to the first point in time.

The operation control signal may be a read enable (RE) signal transmitted to the memory device through the RE pin of the memory device.

The step of obtaining the output reference signal from the memory device (S150) may further include obtaining a data output reference signal from the memory device in response to outputting the operation control signal to the memory device. In this case, the data output reference signal may transition from the second time point to a third time point after a predetermined time interval, and may be output in synchronization with an operation control signal that periodically transitions.

The step of acquiring the data output reference signal (S150) may further include obtaining a data output reference signal that first transitions from the third time point after the first time point.

The predetermined time, which is an interval between the second and third viewpoints, may be predetermined as an integer multiple of the first period. For example, a predetermined interval between the second and third time points may be twice the first period.

The data output reference signal may be a data strobe (DQS) signal received from the memory device through the DQS pin of the memory device.

The step of acquiring data (S170) may include acquiring data output in synchronization with the data output reference signal from the third point in time. It may be a data input/output (DQ) signal output from the memory device through the DQ pin of the memory device.

The data may be output in alignment with the edge of the motion control signal. In other words, the rising edge and the falling edge of the data signal may occur when the rising edge and the falling edge of the operation control signal occur, respectively. Alternatively, the rising edge and the falling edge of the data signal may occur when the falling edge and the rising edge of the operation control signal occur, respectively.

In this way, the operation reference signal (or data strobe (DQS) signal) and the operation signal (or data input/output (DQ) signal) are periodically synchronized with the operation control signal (or read enable signal) or read enable (RE) signal. By making the transition, the data processing speed can be improved.

In other words, unlike the present invention, the operation reference signal (or data strobe (DQS) signal) and the operation signal (or data input/output (DQ) signal) are asynchronous with respect to the operation control signal (or read enable (RE) signal) and operate. When output is delayed by a certain amount of time (e.g., tDQSRE) from the control signal, the transition time of the operation reference signal (or read enable (RE) signal) output from the control device and the operation signal (or data) obtained from the control device Due to the phase difference of the input/output (DQ) signal), the predictability of the signal received from the control device is low, and thus the data processing speed is limited.

In a more specific example, as disclosed in the present invention, when synchronizing a data strobe (DQS) signal and a data input/output (DQ) signal with a read enable (RE) signal, read enable output from the control device As the effective window determined by the (RE) signal and the data strobe (DQS) signal match, the predictability of the data output from the memory device in the control device increases, and the data processing speed in the control device can be significantly increased. have

In addition, in the case of the present invention, unlike the prior art that attempted to increase the speed by using a separate clock (CLK) signal and synchronizing the data output thereto, without a clock (CLK) signal, that is, even with low power, speeding up data processing. May be possible.

A method of controlling a memory device according to an embodiment of the present invention may include obtaining an operation control signal from an external device, outputting an operation reference signal to the external device, and outputting an operation signal to the external device. .

Acquiring the operation control signal may include the memory device entering the ready state and receiving the operation control signal from the external device. The operation control signal may transition from a first point in time to a second point in time after the memory device enters the ready state, and may periodically transition between a logic low and a logic high. The operation control signal may be a read enable (RE) signal.

The outputting of the operation reference signal may include outputting the operation reference signal to the external device in response to obtaining the operation control signal from the external device. The operation reference signal may transition from the second point of time to a third point of time after a predetermined time interval, and may periodically transition between the logic low and the logic high. The operation reference signal may be a data strobe (DQS) signal.

Outputting the operation signal may include outputting data in synchronization with the operation reference signal. The operation signal may be a data input/output (DQ) signal.

7 is a flowchart illustrating a method of controlling a NAND type memory device according to an embodiment of the present invention. The control method of the memory device illustrated in FIG. 7 will be described in more detail below with reference to FIGS. 8 to 10.

Referring to FIG. 7, a method of controlling a NAND type memory device according to an embodiment of the present invention includes acquiring a command signal from an external device (S210), acquiring an operation control signal from an external device (S230), and It may include outputting a data output reference signal to the device (S250) and outputting data (S270).

Acquiring a command signal from an external device (S210) may include acquiring a data output (ie, data read) command signal.

Acquiring the operation control signal from the external device (S230) may include the memory device entering the ready state and receiving the operation control signal from the external device. In this case, the operation control signal may transition from the first point in time to the second point in time when the memory device enters the ready state.

The step of obtaining the motion control signal (S230) may further include outputting a motion control signal that first transitions from the second point in time to the first point in time.

The operation control signal may be a read enable (RE) signal transmitted to the memory device through the RE pin of the memory device.

The step of outputting the data output reference signal to the external device (S250) may further include outputting the data output reference signal to the external device in response to obtaining the operation control signal from the external device. The data output reference signal may transition from the second time point to a third time point after a predetermined time interval. After the data output reference signal transitions at the third time point, it may be output in synchronization with an operation control signal that periodically transitions.

The step of outputting the data output reference signal (S250) may further include outputting a data output reference signal that first transitions from the third time point after the first time point.

The predetermined time, which is an interval between the second and third time points, may be predetermined as an integer multiple (n times) of the first period. For example, a predetermined interval between the second and third time points may be twice the first period.

The data output reference signal may be a data strobe (DQS) signal received from the memory device through the DQS pin of the memory device.

The step of outputting data (S270) may include outputting data in synchronization with a data output reference signal. Data may be output in the form of a data input/output (DQ) signal output from the memory device through the DQ pin of the memory device.

The data may be output in alignment with the edge of the motion control signal. In other words, the rising edge and the falling edge of the data signal may occur when the rising edge and the falling edge of the operation control signal occur, respectively.

In this way, the operation reference signal (or data strobe (DQS) signal) and the operation signal (or data input/output (DQ) signal) are synchronized with the operation control signal (or read enable (RE) signal) or read enable (RE) signal. By controlling the memory device so that it is periodically transitioned, the predictability of data reception in the control device can be improved, and the data processing speed can be improved.

8 is a diagram for explaining timing of main signals in a memory device according to an embodiment of the present invention.

Referring to FIG. 8, the memory device according to an embodiment of the present invention transitions from a state signal to a rising state at a first time point (a) to a second time point (b), and then repeats a logic high at a cycle of tRC. And an operation control signal transitioning between logic rows. In this case, the memory device may output an output reference signal that transitions from the first time point (a) to the third time point (c) and a data input/output (DQ) signal synchronized with the output reference signal.

In this case, a time interval between the second time point (b) and the third time point (c) may be predetermined. The time interval between the second time point (b) and the third time point (c) may be determined as an integer multiple of tRC. Referring to FIG. 8, the time interval tRPREC between the second time point (b) and the third time point (c) may be determined to be twice tRC.

When the data strobe (DQS) signal and the operation signal are synchronized with the read enable (RE) signal output from the control device as in the present invention, the delay time of the data strobe (DQS) signal to the read enable (RE) signal Since tDQSRE, which does not have a minimum value, can be defined as having only a maximum value, design for data processing can be simplified and data processing can be improved.

In addition, according to the present invention, the relationship between the lead enable (RE) signal and the data strobe (DQS) signal is between the time when the read enable (RE) signal transitions (for the first time) and the time when data starts to be output. Since the relationship can be counted in cycles, data handling in the control device can be made easier.

9 is a diagram illustrating timing of main signals in a memory device according to an embodiment of the present invention. Specifically, the main signals are described when the memory device starts to read data.

Unless otherwise specified below, the contents described in FIG. 4 may be similarly applied to each signal.

Referring to FIG. 9, in a memory device according to an embodiment of the present invention, in a state in which a ready/busy (R/B) signal is converted from a busy state to a ready state at a first time point (a), a second time point (b) is ) And periodically transitioning to a lead enable signal (RE). Also, the memory device may output a data strobe (DQS) signal that transitions from a third point in time (c) after the first point in time (a) and a data input/output (DQ) signal in synchronization with the output reference signal.

More specifically, the memory device converts the ready/busy (R/B) signal from the busy state to the ready state at the first time point (a), and then transitions to the second time point (b) after tRR, and repeatedly transitions at a cycle of tRC. A read enable (RE) signal is acquired, and after tRPREC at the second time point (b), it transitions at the third time point (c), and then outputs a data strobe (DQS) signal in synchronization with the read enable (RE) signal. can do.

Compared with FIG. 4, in the embodiment described in FIG. 9, unlike the embodiment described in FIG. 4, the data strobe (DQS) signal and the data input/output (DQ) signal are synchronized with the read enable (RE) signal. I can. In other words, in the embodiment illustrated in FIG. 9, the polling or rising edges of the data strobe (DQS) signal and the data input/output (DQ) signal may be aligned with the falling or rising edge of the lead enable (RE) signal and output. Accordingly, data reception from the control device can be performed more smoothly and quickly.

10 is a diagram for explaining timing of main signals in a memory device according to an embodiment of the present invention. Specifically, this is a diagram for explaining timing of main signals when data is continuously being read from the memory device.

Unless otherwise specified below, the contents described in FIGS. 5 and 9 may be similarly applied to each signal.

Referring to FIG. 10, a memory device according to an embodiment of the present invention acquires a read enable signal RE that transitions at a first point in time a and then periodically transitions between a logic high and a logic low. Outputs a data strobe (DQS) signal that transitions from the first time point (a) to the second time point (b) after a predetermined time interval and then periodically transitions, and synchronizes with the data strobe (DQS) signal at the second time point (b) A data input/output (DQ) signal can be output.

Specifically, the memory device according to an embodiment of the present invention acquires a read enable signal that transitions at a first point in time (a) and then periodically transitions, and after tRL from the first point in time (a). A data strobe (DQS) signal transitioning from the second time point (b) may be output, and a data input/output (DQ) signal synchronized with the data strobe (DQS) signal may be output.

The parameter tRL may represent RE latency. tRL can be given in cycle units. The cycle may mean the period of the RE signal (ie, tRC). tRL may vary depending on the processing speed. For example, when the processing speed is 100 MHz or 133 MHz, tRL may be 3 cycles, when the processing speed is 166 MHz or 200 MHz, tRL may be 4 cycles, and when the processing speed is 266 MHz, tRL may be 5 cycles. tRL may be set differently in the on-die termination (ODT) mode. For example, tRL may be set to be larger in the ODT mode.

Meanwhile, as shown in FIG. 10, in the case of the memory device according to the present invention, a data skew (tDQSQ) is based on a data strobe (DQS) signal synchronized with a read enable (RE) signal that is an output signal of the control device. Therefore, a substantial data skew is guaranteed, and accordingly, high-speed operation can be performed more smoothly.

According to another embodiment of the present invention, a memory device may be provided that selectively performs signal processing of the two aspects described above. Specifically, a memory device in which a signal response system is differently provided based on a control command input from the controller may be provided.

Specifically, the memory device includes a circuit that performs an operation based on a signal obtained from an external device, a first pin that obtains an operation control signal from an external device, a second pin that outputs a data output reference signal from an external device, and an external device. Including a third pin for outputting data to the device, the circuit has a plurality of modes including a first mode and a second mode, based on any one of the plurality of modes based on a mode selection signal input from an external device It can be provided to operate.

The mode selection signal described above may be provided in the form of a command. In other words, the memory device (or the circuit of the memory device) acquires the mode selection command through the DQ pin for acquiring the command signal, and operates based thereon.

The above-described circuit defaults to operating in the second mode, but may be changed to operate in any one of a plurality of modes based on a mode selection signal. Alternatively, the circuit may be provided to operate in the second mode if no other mode selection signal is obtained.

The circuit is provided so that the first pin obtains an operation control signal from an external device, in response thereto, outputs a data output reference signal through the second pin, and outputs data in synchronization with the data output reference signal through the third pin. I can.

For example, in the first mode, the circuit may be provided so that the data output reference signal is delayed for a predetermined time with respect to the operation control signal and is output asynchronously with the operation control signal.

Specifically, in the first mode, the circuit acquires an operation control signal output from the fifth time point after the fourth time point when the memory device enters the ready state from the external device, and the second pin is preset from the second time point. Outputs an output reference signal that is output from the sixth time point after a predetermined time interval, but the data output reference signal is output after a predetermined time (e.g., tDQSRE) is delayed to an operation control signal that periodically transitions, and the third pin is an output reference signal. It may be provided to output data in synchronization with.

In addition, the circuit in the first mode can operate similarly to that described above with respect to FIGS. 4 to 5.

As another example, in the second mode, the circuit may be provided to output a data output reference signal in synchronization with the operation control signal.

Specifically, in the second mode, the circuit is an operation control signal in which the first pin transitions from the external device to the second time point after the first time point when the memory device enters the ready state, and then periodically transitions with a first period. Is obtained, and the second pin outputs a data output reference signal that transitions at a third time point after a predetermined time interval from the second time point, and the data output reference signal is output in synchronization with an operation control signal that periodically transitions, The third pin may be provided to output data in synchronization with an operation control signal periodically transitioning from the third time point.

In an example of a memory device, the first pin is an RE pin that obtains a read enable signal, the second pin is a DQS pin that outputs a data strobe signal, and the third pin is a DQ pin that outputs a data input/output signal. have.

At this time, in the second mode, the circuit outputs a ready signal indicating that the memory device has entered a ready state at a first time point, and in response to outputting the ready signal, obtains a read enable signal through the RE pin. , When the read enable signal transitions from the first point in time to the second point in time, the data strobe signal may be provided to transition from the second point in time to a third point in time after a predetermined time interval.

In addition, a predetermined time, which is an interval between the second and third viewpoints, may be predetermined as an integer multiple of the first period.

The circuit is the data output reference signal that the first pin first transitions from the second point in time to the first point in time, and the second pin first transitions from the third point in time after the first point in time. It may be provided to output.

In addition, although not described in detail with respect to the present embodiment, the circuit in the second mode may operate similarly to that described above with respect to FIGS. 6 to 10.

In the above embodiments, only the first mode and the second mode that the memory device (or its circuit) may have has been described, but such matters do not limit the content of the present invention. In other words, the memory device may further have a third mode in addition to the first mode and the second mode, and may operate in a mode selected based on a command of the control device.

11 is a block diagram illustrating a system in which a memory device according to an exemplary embodiment is applied to an SSD.

Referring to FIG. 11, the SSD system 1000 may include a host 1200 and an SSD 1100. The SSD 1100 may exchange signals with the host 1200 through a signal connector 1111. The SSD 1100 may receive power through a power connector 1121. The SSD 1100 may include an SSD controller 1110, an auxiliary power supply 1120, and a plurality of memory devices 1130, 1140, and 1150. In this case, the SSD controller 1110 may be implemented in the form of a memory controller disclosed herein. Each of the memory devices 1130, 1140, and 1150 may be implemented in the form of a memory device disclosed herein.

As described above, although the embodiments have been described by the limited embodiments and drawings, various modifications and variations are possible from the above description by those of ordinary skill in the art. For example, the described techniques are performed in a different order from the described method, and/or components such as a system, structure, device, circuit, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and claims and equivalents fall within the scope of the claims to be described later.

Claims (21)

In the asynchronous NAND type memory device,
A circuit that performs an operation based on a signal obtained from an external device;
A first pin acquiring an operation control signal from the external device;
A second pin for outputting a data output reference signal to the external device; And
A third pin to output data to the external device in synchronization with the data output reference signal;
Including,
The circuit is
The first pin obtains an operation control signal that transitions from the external device to a second time point after a first point in time when the memory device enters a ready state, and then periodically transitions with a first period,
The second pin outputs the data output reference signal that transitions at a third time point after a predetermined time interval from the second time point, and the data output reference signal is output in synchronization with the operation control signal that periodically transitions. ,
The third pin is provided to output the data in synchronization with the operation control signal and the data output reference signal, which transition at the third time point and periodically transition from the third time point,
The operation control signal is a read enable (RE) signal, the data output reference signal is a data strobe (DQS) signal, and the data is output through a data output (DQ) signal,
The operation control signal is provided longer than the data output reference signal so that the data output signal is output in synchronization with the operation control signal and the data output reference signal from the third time point until the data output is completed. ,
Memory device.
The method of claim 1,
The first pin is an RE pin for obtaining the read enable signal,
The second pin is a DQS pin that outputs the data strobe signal,
The third pin is a DQ pin that outputs the data output signal,
The circuit,
A ready signal indicating that the memory device has entered the ready state is output at the first time point, and in response to outputting the ready signal, the read enable signal is obtained through the RE pin, and the first When the read enable signal transitions at a second point in time after the point in time, the data strobe signal is provided to transition at a third point in time after a predetermined time interval from the second point in time.
Memory device.
The method of claim 1,
The circuit is the data output criterion in which the first pin first transitions from the second point in time to the first point in time after the first point in time, and the second pin first transitions from the third point in time after the first point in time. Arranged to output a signal
Memory device.
The method of claim 1,
The predetermined time, which is an interval between the second time point and the third time point, is predetermined as an integer multiple of the first period,
Memory device.
The method of claim 1,
The circuit has a time difference not exceeding a predetermined reference value at the same time point at which the data output reference signal periodically transitions from the time point at which the operation control signal transitions or from the time point at which the operation control signal transitions. Implemented to transition,
Memory device.
The method of claim 1,
The data is aligned to the edge of the motion control signal and output.
Memory device.
In the method of controlling a NAND type memory device,
When the memory device enters the ready state at a first time point, outputting an operation control signal to the memory device-The operation control signal transitions at a second time point after the first time point, and has a first cycle thereafter. Transition periodically -;
In response to outputting the operation control signal to the memory device, obtaining a data output reference signal from the memory device-The data output reference signal transitions from the second time point to a third time point after a predetermined time interval And is output in synchronization with the operation control signal that periodically transitions; And
Acquiring data output in synchronization with the data output reference signal and the operation control signal from the third point in time; including,
The operation control signal is a read enable (RE) signal, the data output reference signal is a data strobe (DQS) signal, and the data is output through a data output (DQ) signal,
The operation control signal is provided longer than the data output reference signal so that the data output signal is output in synchronization with the operation control signal and the data output reference signal from the third time point until the data output is completed. ,
How to control the memory device.
The method of claim 7,
The read enable signal is transmitted to the memory device through the RE pin of the memory device,
The data strobe signal is obtained from the memory device through the DQS pin of the memory device,
The data output signal is output from the memory device through the DQ pin of the memory device.
How to control the memory device.
The method of claim 7,
The predetermined time, which is an interval between the second time point and the third time point, is predetermined as an integer multiple of the first period.
How to control the memory device.
The method of claim 7,
The data is aligned to the edge of the motion control signal and output.
How to control the memory device.
The method of claim 7,
The step of outputting the motion control signal further includes outputting the motion control signal that first transitions from the second point in time to after the first point in time,
The step of obtaining the data output reference signal further comprises obtaining the data output reference signal that first transitions from the third time point after the first time point.
How to control the memory device.
In the control method of a NAND type memory device,
The memory device enters a ready state, and obtaining an operation control signal from an external device-The operation control signal transitions from a first time point to a second time point after the memory device enters the ready state, and a first time thereafter. Transitioning periodically with a period -;
In response to acquiring the motion control signal from the external device, outputting a data output reference signal to the external device-The data output reference signal transitions from the second time point to a third time point after a predetermined time interval Ham -; And
Outputting data in synchronization with the data output reference signal and the operation control signal; Including,
The operation control signal is a read enable (RE) signal, the data output reference signal is a data strobe (DQS) signal, and the data is output through a data output (DQ) signal,
The operation control signal is provided longer than the data output reference signal so that the data output signal is output in synchronization with the operation control signal and the data output reference signal from the third time point until the data output is completed. ,
How to control the memory device.
The method of claim 12,
The read enable signal is transmitted to the memory device through the RE pin of the memory device,
The data strobe signal is obtained from the memory device through the DQS pin of the memory device,
The data output signal is output from the memory device through the DQ pin of the memory device.
How to control the memory device.
The method of claim 12,
The step of obtaining the motion control signal further includes obtaining the motion control signal that first transitions from the second point in time to after the first point in time,
The step of outputting the data output reference signal further comprises outputting the data output reference signal that first transitions from the third time point to the first time point.
How to control the memory device.
The method of claim 12,
The predetermined time, which is an interval between the second time point and the third time point, is predetermined as an integer multiple of the first period.
How to control the memory device.
The method of claim 12,
The data is aligned to the edge of the motion control signal and output.
How to control the memory device.
In the NAND type memory device,
A circuit that performs an operation based on a signal obtained from an external device;
A first pin acquiring an operation control signal from the external device;
A second pin for outputting a data output reference signal from the external device; And
A third pin outputting data to the external device; Including,
In the circuit, the first pin obtains the operation control signal from the external device, and in response thereto, outputs the data output reference signal through the second pin, and the data output reference signal through the third pin. Synchronously outputs the data, but the operation control signal transitions at a second time point after the first time point when the memory device enters the ready state, and periodically transitions with a first period thereafter.
The data output reference signal includes a first mode delayed for a predetermined time with respect to the operation control signal and asynchronously outputted to the operation control signal, and a second mode in which the data output reference signal is output in synchronization with the operation control signal. It has a plurality of modes and is provided to operate based on any one of the plurality of modes based on a mode selection signal input from the external device, and the data output reference signal is after a predetermined time interval from the second time point. Transition at the 3rd point -,
The operation control signal is a read enable (RE) signal, the data output reference signal is a data strobe (DQS) signal, and the data is output through a data output (DQ) signal,
The operation control signal is provided longer than the data output reference signal so that the data output signal is output in synchronization with the operation control signal and the data output reference signal from the third time point until the data output is completed. ,
Memory device.
The method of claim 17,
The first pin is an RE pin for obtaining the read enable signal,
The second pin is a DQS pin that outputs the data strobe signal,
The third pin is a DQ pin that outputs the data output signal,
The circuit,
A ready signal indicating that the memory device has entered the ready state is output at the first time point, and in response to outputting the ready signal, the read enable signal is obtained through the RE pin, and the first When the read enable signal transitions from the second point of time to the second point of time, the data strobe signal is provided to transition from the second point of time to the third point of time after a predetermined time interval.
Memory device.
The method of claim 17,
The circuit is changed to operate in any one of the plurality of modes based on the mode selection signal by default to operate in the second mode,
Memory device.
The method of claim 17,
The circuit is the data output criterion in which the first pin first transitions from the second point in time to the first point in time after the first point in time, and the second pin first transitions from the third point in time after the first point in time. Arranged to output a signal
Memory device.
The method of claim 17,
The predetermined time, which is an interval between the second time point and the third time point, is predetermined as an integer multiple of the first period.
Memory device.

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