KR102170904B1 - PCB having passive device and method of manufacturing the same - Google Patents

Abstract

A printed circuit board according to an embodiment includes a base substrate having an inner circuit pattern layer, an outer circuit pattern layer, and an interlayer insulating layer disposed between the inner circuit pattern layer and the outer circuit pattern layer. In addition, the printed circuit board includes a device accommodation space formed in a cavity exposing the inner circuit pattern layer in the interlayer insulating layer. In addition, the printed circuit board is disposed in the device accommodation space, the first passive electrode having first and second electrodes disposed to be spaced apart from each other, and a first functional layer disposed between the first and second electrodes Including elements. In addition, the printed circuit board is stacked on the first passive element and has third and fourth electrodes disposed to be spaced apart from each other, and a second functional layer disposed between the third and fourth electrodes. Includes 2 passive elements. At this time, the first and second electrodes of the first passive element are bonded to the inner circuit pattern layer, respectively, the third electrode of the second passive element is bonded to any one of the first and second electrodes, and the The fourth electrode is bonded to the outer circuit pattern layer.

Description

TECHNICAL FIELD [0002] A printed circuit board having a passive element and a method of manufacturing the same.

The present invention relates to a printed circuit board (PCB), and more particularly, to a printed circuit board including a passive element and a method of manufacturing the same.

With the miniaturization of electronic devices, electronic components built into the electronic devices have become more highly functional and more compact. With the advancement of digital networks, portable information terminal devices such as mobile phones and portable computers are becoming high-performance and highly functional, and various functions are fused to one device to be complex.

As described above, as electronic devices are miniaturized and highly functional, the number of component elements to be mounted on a printed circuit board constituting the electronic device is increasing, but the area of the substrate is not decreased. Rather, according to the aforementioned trend of miniaturization, it is requested to reduce the thickness of the existing printed circuit board and the thickness of the component element. Accordingly, the need for a new structure of a printed circuit board and a manufacturing method therefor to satisfy the above-described requirements is continuously increasing.

An embodiment of the present application provides a structure and manufacturing method of a printed circuit board capable of stacking a plurality of passive elements on a substrate.

A printed circuit board according to an aspect of the present application is provided. The printed circuit board includes a base substrate having an inner circuit pattern layer, an outer circuit pattern layer, and an interlayer insulating layer disposed between the inner circuit pattern layer and the outer circuit pattern layer. In addition, the printed circuit board includes a device accommodation space formed in a cavity exposing the inner circuit pattern layer in the interlayer insulating layer. In addition, the printed circuit board is disposed in the device accommodation space, the first passive electrode having first and second electrodes disposed to be spaced apart from each other, and a first functional layer disposed between the first and second electrodes Including elements. In addition, the printed circuit board is stacked on the first passive element and has third and fourth electrodes disposed to be spaced apart from each other, and a second functional layer disposed between the third and fourth electrodes. Includes 2 passive elements. At this time, the first and second electrodes of the first passive element are bonded to the inner circuit pattern layer, respectively, the third electrode of the second passive element is bonded to any one of the first and second electrodes, and the The fourth electrode is bonded to the outer circuit pattern layer.

A printed circuit board according to another aspect of the present disclosure is provided. The printed circuit board includes a base substrate including an inner circuit pattern layer, an outer circuit pattern layer, and an interlayer insulating layer disposed between the inner circuit pattern layer and the outer circuit pattern layer. In addition, the printed circuit board includes a device accommodation space formed in a cavity exposing the inner circuit pattern layer in the interlayer insulating layer. In addition, the printed circuit board includes a first passive element disposed in the device accommodation space and having first and second electrodes disposed to be spaced apart from each other, and a first functional layer disposed between the first and second electrodes. Include. In addition, the printed circuit board is stacked on the first passive element, the second having third and fourth electrodes disposed to be spaced apart from each other, and a second functional layer disposed between the third and fourth electrodes. Includes passive components. In this case, the first and second electrodes of the first passive element are bonded to the inner circuit pattern layer, respectively, and the third and fourth electrodes of the second passive element are connected to the first and second electrodes. Each is joined.

A method of manufacturing a printed circuit board according to another aspect of the present disclosure is provided. In the above manufacturing method, a base insulating layer including an inner circuit pattern layer is provided. An interlayer insulating layer is formed on the base insulating layer to cover the inner circuit pattern layer. An outer circuit pattern layer is formed on the interlayer insulating layer. The interlayer insulating layer is processed to form a cavity exposing the inner circuit pattern layer and the base insulating layer. A first passive element is mounted on the inner circuit pattern layer in the cavity. The first passive element includes first and second electrodes disposed to be spaced apart from each other, and a first functional layer disposed between the first and second electrodes. A second passive element is mounted on the first passive element. The second passive element includes third and fourth electrodes disposed to be spaced apart from each other, and a second functional layer disposed between the third and fourth electrodes. When the second passive element is mounted, the third electrode is bonded to one of the first and second electrodes, and the fourth electrode is bonded to the outer circuit pattern layer.

A method of manufacturing a printed circuit board according to another aspect of the present disclosure is provided. In the above manufacturing method, a base insulating layer including an inner circuit pattern layer is provided. An interlayer insulating layer is formed on the base insulating layer to cover the inner circuit pattern layer. An outer circuit pattern layer is formed on the interlayer insulating layer. The interlayer insulating layer is processed to form a cavity exposing the inner circuit pattern layer and the base insulating layer. A first passive element is mounted on the inner circuit pattern layer in the cavity. The first passive element includes first and second electrodes disposed to be spaced apart from each other, and a first functional layer disposed between the first and second electrodes. A second passive element is mounted on the first passive element. The second passive element includes third and fourth electrodes disposed to be spaced apart from each other, and a second functional layer disposed between the third and fourth electrodes. When mounting the second passive element, the third electrode and the fourth electrode are bonded to the first and second electrodes, respectively.

According to the exemplary embodiment of the present application, a plurality of passive elements may be stacked using an element accommodation space formed in a cavity of a printed circuit board. Through this, the thickness of the printed circuit board can be reduced. In addition, in connection with bonding between a plurality of stacked passive elements, each electrode of the passive element may be bonded to each other using a solder material. Accordingly, separate wiring for electrical connection between stacked passive elements may not be formed on the printed circuit board. As a result, it is possible to increase the mounting density of the passive elements in the printed circuit board, and to effectively reduce the size of the printed circuit board.

1 is a schematic cross-sectional view of a printed circuit board according to an embodiment of the present application.
2 is a schematic cross-sectional view of a printed circuit board according to another embodiment of the present application.
3 to 8 are cross-sectional views schematically illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present application.
9 and 10 are cross-sectional views schematically illustrating a method of manufacturing a printed circuit board according to another embodiment of the present application.

Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, in order to clearly express the constituent elements of each device, the size of the constituent elements, such as width or thickness, is slightly enlarged. Overall, it was described at the observer's point of view when explaining the drawings, and if one element is referred to as being positioned on another element, this means that the one element is positioned directly on another element or that an additional element may be interposed between them. Include.

The same reference numerals in the plurality of drawings refer to substantially the same elements. In addition, expressions in the singular should be understood as including plural expressions unless clearly defined otherwise in the context, and terms such as'include' or'have' are described features, numbers, steps, actions, components, and parts. It is to be understood that it is intended to designate the existence of a combination of these and not to preclude the possibility of the presence or addition of one or more other features or numbers, steps, actions, components, parts, or combinations thereof.

In addition, in performing the method or manufacturing method, each of the processes constituting the method may occur differently from the specified order unless a specific order is clearly stated in the context. That is, each process may occur in the same order as the specified order, may be performed substantially simultaneously, or may be performed in the reverse order.

As used herein, the term "top surface" or "bottom" of a substrate or device chip is a relative concept observed from the viewpoint of an observer. Accordingly, one of the two surfaces excluding the side surface of the substrate or the device chip may be referred to as “top” or “lower”, and correspondingly, the other side may be referred to as “lower” or “top”. Likewise, in the present specification, the concept of'top','top' or'bottom' and'bottom' may also be used as a relative concept.

1 is a schematic cross-sectional view of a printed circuit board according to an embodiment of the present application. Referring to FIG. 1, the printed circuit board 1 includes a base insulating layer 110 having a first surface 110S1 and a second surface 110S2. In the base insulating layer 110, upper inner circuit pattern layers 120a, 120a1, and 120a2 may be disposed on the first surface 110S1. In one embodiment, the upper inner circuit pattern layers 120a, 120a1, 120a2 excluding the upper surface, such that the upper surfaces of the upper inner circuit pattern layers 120a, 120a1, and 120a2 are positioned at the same level as the first surface 110S1. ) May be disposed to be buried in the base insulating layer 110. Meanwhile, the lower inner circuit pattern layers 120b, 120b1, and 120b2 may be disposed on the second surface 110S2. The lower inner circuit pattern layers 120b, 120b1, and 120b2 may be disposed to protrude from the second surface 110S2.

In addition, some 120a1 and 120a2 of the upper inner circuit pattern layers 120a, 120a1 and 120a2 and some 120b1 and 120b2 of the lower inner circuit pattern layers 120b, 120b1 and 120b are mutually formed by the core via 112 Can be electrically connected.

An upper interlayer insulating layer 130 may be disposed on the first surface 110S1 of the base insulating layer 110. Upper outer circuit pattern layers 140a and 140a1 may be disposed on the upper interlayer insulating layer 130. In addition, in the upper interlayer insulating layer 130, a portion of the upper outer circuit pattern layers 140a and 140a1 and a portion of the upper inner circuit pattern layers 120a, 120a1 and 120a2 are electrically connected to each other. ) Can be placed.

Likewise, the lower interlayer insulating layer 150 may be disposed on the second surface 110S2 of the base insulating layer 110. A lower outer circuit pattern layer 140b may be disposed on the lower interlayer insulating layer 150. In addition, in the lower interlayer insulating layer 150, a lower via 152 electrically connecting a portion of the lower outer circuit pattern layer 140b and a portion of the lower inner circuit pattern layers 120b, 120b1, 120b2 to each other is provided. Can be placed.

Referring again to FIG. 1, an upper solder resist pattern layer 160 selectively covering the upper outer circuit pattern layers 140a and 140a1 may be disposed on the upper interlayer insulating layer 130. A portion of the upper outer circuit pattern layers 140a and 140a1 exposed by the upper solder resist pattern layer 160 may function as an external device chip or a connection pad electrically connected to the external substrate. In FIG. 1, a portion 140a1 of the upper outer circuit pattern layers 140a and 140a1 may be applied as a connection pad for electrical connection with the passive element 20.

Meanwhile, a lower solder resist pattern layer 170 may be disposed on the lower interlayer insulating layer 150 to selectively cover the lower outer circuit pattern layer 140b. A portion of the lower outer circuit pattern layer 140b exposed by the lower solder resist pattern layer 170 may function as a connection pad electrically connected to the external substrate. As an example, a connection structure (not shown) such as a solder ball may be disposed on a portion of the lower outer circuit pattern layer 140b to be connected to a terminal of the external substrate.

In summary, the printed circuit board 1 according to the embodiment of the present application may include a base board 1a. The base substrate 1a includes inner circuit pattern layers 120a, 120a1, 120a2, 120b, 120b1, 120b2, outer circuit pattern layers 140a, 140a1, 140b, and inner circuit pattern layers 120a, 120a1, 120a2, 120b, The interlayer insulating layers 110, 130, and 150 may be disposed between the 120b1 and 120b2 and the outer circuit pattern layers 140a, 140a1 and 140b.

Meanwhile, referring again to FIG. 1, a cavity 1000 exposing the inner circuit pattern layers 120a1 and 120a2 may be formed in the upper interlayer insulating layer 130. The cavity 1000 may function as an element accommodation space in which the first passive element 10 is mounted.

The first passive element 10 may include a first electrode 12, a first functional layer 16 and a second electrode 14. The first electrode 12 and the second electrode 14 are disposed to be spaced apart from each other, and the first functional layer 16 may be disposed between the first electrode 12 and the second electrode 14. As an embodiment, the first passive element 10 may include a capacitor element. In this case, the first functional layer 16 may be a dielectric layer. As an example, the capacitor device may be a multilayer ceramic capacitor (MLCC). That is, when the first passive element 10 is a multilayer ceramic capacitor, the first electrode 12 and the second electrode 14 are electrically isolated from each other, and the first electrode 12 and the second electrode 14 ) May be electrically connected to the plurality of stacked dielectric layers, respectively. In another embodiment, the first passive element 10 may be an inductor element. In this case, when the first passive element 10 is an inductor element, the first electrode 12 and the second electrode 14 each function as a connection terminal, and the first functional layer 16 may be a coil layer. In another embodiment, the first passive element 10 may be a resistive element. When the first passive element 10 is a resistive element, the first electrode 12 and the second electrode 14 each function as a connection terminal, and the first functional layer 16 may be a resistance layer.

The first passive element 10 may be mounted in the element accommodation space by bonding the first electrode 12 and the second electrode 14 to the corresponding upper inner circuit pattern layers 120a1 and 120a2, respectively. In this case, the bonding may be made by the solder material 180. The solder material 180 may include a solder ball, a solder bump, or a solder paste. The solder material 180 has a lower melting point than the upper inner circuit pattern layers 120a1 and 120a2 and the first and second electrodes 12 and 14, and thus, when the solder material 180 is melted, the melted The solder material 180 may flow in contact with the upper inner circuit pattern layers 120a1 and 120a2 and the first and first electrodes 12 and 14. Subsequently, by cooling and solidifying the molten solder material 180, the solder material 180 may bond the upper inner circuit pattern layers 120a1 and 120a2 and the first and second electrodes 12 and 14 to each other. .

In one embodiment, the first electrode 12 may be made of a conductive material, and the solder material 180 may directly bond the outer surface of the first electrode 12 and the upper inner circuit pattern layer 120a1. In another embodiment, a separate conductive connection pad (not shown) having a predetermined cross-sectional area may be disposed on the outer surface of the first electrode 12, and the solder material 180 includes the connection pad and the upper inner circuit pattern layer. (120a1) can be bonded together. In this case, the melting point of the connection pad may be higher than the melting point of the solder material 180. Meanwhile, the second electrode 14 and the upper inner circuit pattern layer 120a2 may also be bonded to each other by employing the same method as described above.

Referring again to FIG. 1, the upper surfaces 10S of the first and second electrodes 12 and 14 may be positioned at the same level as the upper surfaces of the outer circuit pattern layers 140a and 140a1. Meanwhile, the upper surface 10S of the first and second electrodes 12 and 14 may be positioned higher than the upper surface 130S of the upper interlayer insulating layer 130. Through this, the second passive element 20 to be described later is reliably bonded to the second electrode 14 and the upper outer circuit pattern layer 140a1 of the first passive element 10 and the solder material 180. Can be.

A second passive element 20 may be stacked on the first passive element 10. The second passive element 20 may include a third electrode 22, a second functional layer 26 and a fourth electrode 24. The third electrode 22 and the fourth electrode 24 are disposed to be spaced apart from each other, and the second functional layer 26 may be disposed between the third electrode 22 and the fourth electrode 24. As an embodiment, the second passive element 20 may include a capacitor element. In this case, the second functional layer 26 may be a dielectric layer. In another embodiment, the second passive element 20 may be an inductor element. In this case, the third and fourth electrodes 22 and 24 each function as a connection terminal, and the second functional layer 26 may be a coil layer. In another embodiment, the second passive element 20 may be a resistive element. When the second passive element 20 is a resistance element, the third and fourth electrodes 22 and 24 function as connection terminals, respectively, and the second functional layer 26 may be a resistance layer.

In one embodiment, the second passive element 20 may be a device of the same type as the first passive element 10. As an example, the first and second passive elements 20 may be capacitor elements. The capacitor device may be a multilayer ceramic capacitor (MLCC). In another embodiment, the second passive element 20 may be a different type of element from the first passive element 10. As an example, one of the first and second passive elements 20 may be a capacitor element, and the other may be an inductor element.

The third electrode 22 of the second passive element 20 is bonded to the second electrode 14 of the first passive element 10, and the fourth electrode 24 is bonded to the upper outer circuit pattern layer 140a1. can do. At this time, a solder material 180 is applied to bond the third electrode 22 and the second electrode 14, and a solder material () to bond the fourth electrode 24 and the upper outer circuit pattern layer 140a1 180) can be applied. In an embodiment, the solder material 180 may be directly bonded to the outer surface of the third electrode 22 and the outer surface of the second electrode 14. In another embodiment, conductive connection pads (not shown) having a predetermined cross-sectional area are disposed on the outer surfaces of the third electrode 22 and the second electrode 14, respectively, and the solder material 180 is each of the connection pads. And can be joined. Similarly, the solder material 180 may be directly bonded to the outer surface of the fourth electrode 24 and the upper outer circuit pattern layer 140a1. Alternatively, a conductive connection pad (not shown) having a predetermined cross-sectional area is disposed on the outer surface of the fourth electrode 24, and the solder material 180 includes a connection pad disposed on the outer surface of the fourth electrode 24 and It may be bonded to the upper outer circuit pattern layer 140a1. As a result, the first passive element 10 and the second passive element 20 may be electrically connected in series with each other.

As described above, the printed circuit board according to the exemplary embodiment of the present application may have the following advantages. First, the thickness of the printed circuit board can be reduced by stacking a plurality of passive devices using the device accommodation space formed in the cavity of the printed circuit board. Second, for electrical connection between the stacked passive elements, a separate wiring may not be formed on the printed circuit board. That is, in the stacked passive device, each electrode of the passive device may be bonded to each other using a solder material. Accordingly, since the wiring can be omitted, the mounting density of the passive element in the printed circuit board can be increased. Accordingly, the size of the printed circuit board can be effectively reduced.

2 is a schematic cross-sectional view of a printed circuit board according to another embodiment of the present application. The printed circuit board 2 has substantially the same configuration as the printed circuit board 1 described above with respect to FIG. 1 except for the stacking method of the first passive element 10 and the second passive element 20. .

Referring to FIG. 2, the first passive element 10 is mounted in the cavity 1000 of the base substrate 1a. Subsequently, the second passive element 20 is stacked on top of the first passive element 10, and the third electrode 22 of the second passive element 20 and the first electrode of the first passive element 10 ( 12) are bonded to each other, and the fourth electrode 24 of the second passive element 20 and the second electrode 14 of the first passive element 10 are bonded to each other. The bonding may be performed using the solder material 180. As a result of the bonding, the first passive element 10 and the second passive element 20 may be electrically connected in parallel with each other.

In this embodiment, the bonding of the first passive element 10 and the second passive element 20 stacked on the base substrate 1a is made by bonding a solder material 180 between electrodes corresponding to each other. I can. Through this, for the electrical connection between the first passive element 10 and the second passive element 20, a separate wiring located on the base substrate 1a may not be used. As a result, it is possible to increase the mounting density of the passive element in the printed circuit board, and to reduce the size of the printed circuit board.

3 to 8 are cross-sectional views schematically illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present application. Referring to FIG. 3, a base substrate 1a is provided. The base substrate 1a is substantially the same as the base substrate 1a described above with respect to FIG. 1.

The base substrate 1a may include a base insulating layer 110 having a first surface 110S1 and a second surface 110S2. Upper inner circuit pattern layers 120a, 120a1, and 120a2 may be formed on the first surface 110S1. In an embodiment, the upper inner circuit pattern layers 120a, 120a1, 120a2 are formed such that the upper surface is positioned at the same level as the first surface 110S1, and the upper inner circuit pattern layers 120a, 120a1, and 120a2 except for the upper surface. ) May be formed to be buried in the base insulating layer 110. Meanwhile, lower inner circuit pattern layers 120b, 120b1, and 120b2 may be formed on the second surface 110S2. The lower inner circuit pattern layers 120b, 120b1, and 120b2 may be formed to protrude from the second surface 110S2.

In addition, some 120a1 and 120a2 of the upper inner circuit pattern layers 120a, 120a1 and 120a2 and some 120b1 and 120b2 of the lower inner circuit pattern layers 120b, 120b1 and 120b are mutually formed by the core via 112 Can be electrically connected. The upper inner circuit pattern layers 120a, 120a1 and 120a2, the lower inner circuit pattern layers 120b, 120b1 and 120b2, and the core via 112 may be formed by a known plating method. That is, the upper inner circuit pattern layers 120a, 120a1, and 120a2, the lower inner circuit pattern layers 120b, 120b1 and 120b2, and the core via 112 may be copper plating layers. Through the above-described process, the base insulating layer 110 including the upper inner circuit pattern layers 120a, 120a1, and 120a2, and the lower inner circuit pattern layers 120b, 120b1, and 120b2 may be provided.

Subsequently, an upper interlayer insulating layer 130 covering the upper inner circuit pattern layers 120a, 120a1 and 120a2 may be formed on the first surface 110S1 of the base insulating layer 110. Upper outer circuit pattern layers 140a and 140a1 may be formed on the upper interlayer insulating layer 130. In addition, in the upper interlayer insulating layer 130, a portion of the upper outer circuit pattern layers 140a and 140a1 and a portion of the upper inner circuit pattern layers 120a, 120a1 and 120a2 are electrically connected to each other. ) Can be formed.

Likewise, a lower interlayer insulating layer 150 covering the lower inner circuit pattern layers 120b, 120b1 and 120b2 may be formed on the second surface 110S2 of the base insulating layer 110. A lower outer circuit pattern layer 140b may be formed on the lower interlayer insulating layer 150. In addition, in the lower interlayer insulating layer 150, a lower via 152 electrically connecting a portion of the lower outer circuit pattern layer 140b and a portion of the lower inner circuit pattern layers 120b, 120b1, 120b2 to each other is provided. Can be formed.

The upper outer circuit pattern layers 140a and 140a1, the upper via 132, the lower outer circuit pattern layer 140b, and the lower via 152 may be formed by a known plating method. That is, the upper outer circuit pattern layers 140a and 140a1, the upper via 132, the lower outer circuit pattern layer 140b, and the lower via 152 may be copper plating layers.

Referring again to FIG. 3, an upper solder resist pattern layer 160 may be formed on the upper interlayer insulating layer 130 to selectively cover the upper outer circuit pattern layers 140a and 140a1. Meanwhile, in FIG. 3, a portion 140a1 of the upper outer circuit pattern layers 140a and 140a1 exposed by the upper solder resist pattern layer 160 may be applied as a connection pad for electrical connection with the passive element 20. .

Meanwhile, a lower solder resist pattern layer 170 may be formed on the lower interlayer insulating layer 150 to selectively cover the lower outer circuit pattern layer 140b. A portion of the lower outer circuit pattern layer 140b exposed by the lower solder resist pattern layer 170 may function as a connection pad electrically connected to the external substrate. As an example, a connection structure (not shown) such as a solder ball may be disposed on a portion of the lower outer circuit pattern layer 140b to be connected to a terminal of the external substrate.

4, a cavity exposing the upper inner circuit pattern layers 120a1 and 120a2 and the base insulating layer 110 by processing the upper interlayer insulating layer 130 not covered with the upper solder resist pattern layer 160 (1000) can be formed.

Referring to FIG. 5, a solder material 180 is disposed on the upper inner circuit pattern layers 120a1 and 120b1 exposed by the cavity 1000. The solder material 180 may include, for example, a solder ball, a solder bump, or a solder paste. As a method of arranging the solder material 180, a known vapor deposition method, a printing method, a paste method, or the like can be applied.

Referring to FIG. 6, the first passive element 10 is mounted in the element accommodation space inside the cavity 1000. The first passive element 10 includes first and second electrodes 12 and 14 disposed to be spaced apart from each other, and a first functional layer 16 disposed between the first and second electrodes 12 and 14. Can be equipped. In one embodiment, the passive element 10 may include a capacitor element. In this case, the first functional layer 16 may be a dielectric layer. As an example, the capacitor device may be a multilayer ceramic capacitor (MLCC). That is, the first electrode 12 and the second electrode 14 are electrically isolated from each other, and the first electrode 12 and the second electrode 14 may be electrically connected to a plurality of stacked dielectric layers, respectively. . In another embodiment, the first passive element 10 may be an inductor element. In this case, the first and second electrodes 12 and 14 each function as a connection terminal, and the first functional layer 16 may be a coil layer. In another embodiment, the first passive element 10 may be a resistive element. When the first passive element 10 is a resistive element, the first electrode 12 and the second electrode 14 each function as a connection terminal, and the first functional layer 16 may be a resistance layer.

In one embodiment, the first electrode 12 and the second electrode 14 of the first passive element 10, respectively, corresponding upper inner circuit pattern layers 120a1 and 120a2, and a solder material 180 Can be used to bond. Through this, the first passive element 10 can be seated in the element accommodation space in the cavity 1000.

Specifically, the solder material 180 may have a lower melting point than the upper inner circuit pattern layers 120a1 and 120a2 and the first and second electrodes 12 and 14. Accordingly, by applying heat to the base substrate 1a at a temperature capable of melting the solder material 180, the molten solder material 180 may have fluidity. Subsequently, the first passive element 20 may be attached to the base substrate 1a so that the upper inner circuit pattern layers 120a1 and 120a2 and the first and first electrodes 12 and 14 contact each other. Subsequently, by cooling the base substrate 1a, the solder material 180 may be solidified. Accordingly, the upper inner circuit pattern layers 120a1 and 120a2 and the first and first electrodes 12 and 14 may be bonded to each other by the solder material 180.

6 illustrates an embodiment in which the solder material 180 directly bonds the outer surface of the first electrode 12 and the upper inner circuit pattern layer 120a1. However, it is not necessarily limited thereto, and in another embodiment not shown, a separate conductive connection pad (not shown) having a predetermined cross-sectional area may be disposed on the outer surface of the first electrode 12, and the solder material 180 ) May bond the connection pad and the upper inner circuit pattern layer 120a1 to each other. In this case, the melting point of the connection pad may be higher than the melting point of the solder material 180. Similarly, the second electrode 14 and the upper inner circuit pattern layer 120a2 may also be bonded to each other by employing the same method as described above.

Referring again to FIG. 6, in the step of mounting the first passive element 10, the upper surface 10S of the first and second electrodes 12 and 14 is the upper surface of the upper outer circuit pattern layer 140a1 ( 140S1) and mounting to achieve the same level. Accordingly, the upper surface 10S of the first and second electrodes 12 and 14 may be positioned higher than the upper surface 130S of the upper interlayer insulating layer 130. As described above, since the upper surfaces 10S of the first and second electrodes 12 and 14 are located at the same level as the upper surface 140S1 of the upper outer circuit pattern layer 140a1, FIGS. 7 and 7 to be described later. As described with respect to 8, the second passive element 20 may be reliably stacked on the first passive element 10 and the upper outer circuit pattern layer 140a1.

Referring to FIG. 7, a solder material 180 is disposed on the second electrode 14 and the upper outer circuit pattern layer 140a1 of the first passive element 10. The solder material 180 may include, for example, a solder ball, a solder bump, or a solder paste. As a method of arranging the solder material 180, a known vapor deposition method, a printing method, a paste method, or the like can be applied.

Referring to FIG. 8, the second passive element 20 is mounted on the first passive element 10 seated in the element accommodation space inside the cavity 1000. In this case, the second passive element 20 includes third and fourth electrodes 22 and 24 disposed to be spaced apart from each other, and a second functional layer disposed between the third and fourth electrodes 22 and 24 ( 26) can be provided. In one embodiment, the passive element 20 may include a capacitor element. In this case, the second functional layer 26 may be a dielectric layer. As an example, the capacitor device may be a multilayer ceramic capacitor (MLCC). That is, the third electrode 22 and the fourth electrode 24 are electrically isolated from each other, and the third electrode 22 and the fourth electrode 24 may be electrically connected to a plurality of stacked dielectric layers, respectively. . In another embodiment, the second passive element 20 may be an inductor element. In this case, the third and fourth electrodes 22 and 24 may function as connection terminals, respectively. The second functional layer 26 may be a coil layer. In another embodiment, the second passive element 20 may be a resistive element. When the second passive element 20 is a resistance element, the third and fourth electrodes 22 and 24 function as connection terminals, respectively, and the second functional layer 26 may be a resistance layer.

In one embodiment, the third electrode 22 of the second passive element 20 is bonded to the second electrode 14 of the first passive element 10, and the fourth electrode 24 is attached to the upper outer layer circuit pattern. It may be bonded to the layer 140S1. In this case, the bonding of the third electrode 22 and the fourth electrode 24 may be performed using the solder material 180.

Specifically, the solder material 180 may have a lower melting point than the first to fourth electrodes 12, 14, 22, and 24. Accordingly, by applying heat to the base substrate 1a at a temperature capable of melting the solder material 180, the molten solder material 180 may have fluidity. Then, the second passive element 20 is attached to the first passive element 10 so that the third and fourth electrodes 22 and 24 contact each other with the second electrode 14 and the upper outer circuit pattern layer 140S1. Can be attached.

8 illustrates an embodiment in which the solder material 180 directly bonds the outer surface of the second electrode 14 and the outer surface of the third electrode 22. However, it is not necessarily limited thereto, and in other embodiments not shown, separate conductive connection pads (not shown) having a predetermined cross-sectional area are disposed on the outer surfaces of the second electrode 14 and the third electrode 22, respectively. The solder material 180 may bond the connection pads to each other. In this case, the melting point of the connection pads may be higher than the melting point of the solder material 180. Similarly, in another embodiment not shown, a separate conductive connection pad (not shown) having a predetermined cross-sectional area may be disposed on the outer surface of the fourth electrode 24, and the solder material 180 The upper outer circuit pattern layers 140a1 may be bonded to each other. In this case, the melting point of the connection pad may be higher than the melting point of the solder material 180.

A printed circuit board according to an embodiment of the present application may be manufactured by performing the above-described process. The printed circuit board manufactured through the process of FIGS. 3 to 8 may be the printed circuit board 1 described above with respect to FIG. 1. Meanwhile, in FIG. 8, the third electrode 22 of the second passive element 20 is in contact with the second electrode 14 of the first passive element 10, and the fourth electrode 24 of the second passive element 20 ) Shows an embodiment in contact with the upper outer circuit pattern layer 140a1, but is not limited thereto. In another embodiment not shown, the third electrode 22 of the second passive element 20 is in contact with the upper outer circuit pattern layer 140a, and the fourth electrode 24 of the second passive element 20 is 1 It may be stacked to be in contact with the first electrode 12 of the passive element 10.

As described above, according to the exemplary embodiment of the present application, a plurality of passive elements may be stacked using the element accommodation space formed in the cavity of the printed circuit board. Through this, the thickness of the printed circuit board can be reduced. In addition, in connection with bonding between a plurality of stacked passive elements, each electrode of the passive element may be bonded to each other using a solder material. Accordingly, separate wiring for electrical connection between stacked passive elements may not be formed on the printed circuit board. As a result, it is possible to increase the mounting density of the passive elements in the printed circuit board, and to effectively reduce the size of the printed circuit board.

9 and 10 are cross-sectional views schematically illustrating a method of manufacturing a printed circuit board according to another embodiment of the present application. In the present manufacturing method, compared to the manufacturing method described above with respect to FIGS. 3 to 8, the stacking method of the first and second passive elements 10 and 20 is differentiated.

Referring to FIG. 9, the process related to FIGS. 3 to 6 is performed to prepare a base substrate 1a on which the first passive element 10 is mounted in the cavity 1000. Subsequently, a solder material 180 is disposed on the first and second electrodes 12 and 14 of the first passive element 10, respectively.

Referring to FIG. 10, a second passive element 20 is stacked on the first passive element 10. At this time, by using the solder material 180, the third electrode 22 of the second passive element 20 and the first electrode 12 of the first passive element 10 are bonded together, and the second passive element ( The fourth electrode 24 of 20) and the second electrode 14 of the first passive element 10 are bonded together.

The printed circuit board according to the present embodiment may be manufactured by performing the above-described process. The printed circuit board manufactured through the process described above with respect to FIGS. 9 and 10 may be the printed circuit board 2 described above with respect to FIG. 2.

Although described above with reference to the drawings and embodiments, those skilled in the art will variously modify and change the embodiments disclosed in the present application within the scope not departing from the technical spirit of the present application described in the following claims. You will understand that you can do it.

1 2: printed circuit board,
10: first passive element, 20: second passive element,
12: first electrode, 14: second electrode, 16: first functional layer,
22: third electrode, 24: fourth electrode, 26: second functional layer,
110S1: first side, 110S2: second side,
110: base insulating layer,
120a, 120a1, 120a2: upper inner circuit pattern layer,
120b, 120b1, 120b2: lower inner circuit pattern layer,
130: upper interlayer insulating layer, 150: lower interlayer insulating layer,
140a, 140a1: upper outer circuit pattern layer,
140b: lower outer circuit pattern layer,
112: core via, 132: upper via, 152: lower via,
160: upper solder resist pattern layer, 170: lower solder resist pattern layer.

Claims (15)

A base substrate including an inner circuit pattern layer, an outer circuit pattern layer, and an interlayer insulating layer disposed between the inner circuit pattern layer and the outer circuit pattern layer;
An element accommodation space formed in a cavity exposing the inner circuit pattern layer in the interlayer insulating layer;
A first passive element disposed in the element accommodation space and having first and second electrodes disposed to be spaced apart from each other, and a first functional layer disposed between the first and second electrodes; And
A second passive element including third and fourth electrodes stacked on top of the first passive element and disposed to be spaced apart from each other, and a second functional layer disposed between the third and fourth electrodes,
The first and second electrodes of the first passive element are respectively bonded to the inner circuit pattern layer,
The third electrode of the second passive element is bonded to any one of the first and second electrodes, and the fourth electrode is bonded to the outer circuit pattern layer,
The second passive element is disposed on the outer circuit pattern layer outside the cavity
Printed circuit board.
The method of claim 1,
The first and second passive elements each include any one selected from a capacitor element, an inductor element, and a resistance element.
Printed circuit board.
The method of claim 2,
The capacitor device is a multilayer ceramic capacitor (MLCC)
Printed circuit board
The method of claim 1,
The first and second electrodes are bonded to the inner circuit pattern layer by a solder material.
Printed circuit board.
The method of claim 1,
The third electrode is bonded to any one of the first and second electrodes by a solder material,
The fourth electrode is bonded to the outer circuit pattern layer by a solder material
Printed circuit board.
The method of claim 1,
The upper surfaces of the first and second electrodes are positioned at the same level as the upper surface of the outer circuit pattern layer.
Printed circuit board.
The method of claim 1,
The first and second passive elements are electrically connected in series
Printed circuit board.
delete delete Providing a base insulating layer having an inner circuit pattern layer;
Forming an interlayer insulating layer on the base insulating layer to cover the inner circuit pattern layer;
Forming an outer circuit pattern layer on the interlayer insulating layer;
Processing the interlayer insulating layer to form a cavity exposing the inner circuit pattern layer and the base insulating layer;
A first passive element is mounted on the inner circuit pattern layer in the cavity, wherein the first passive element is spaced apart from each other, first and second electrodes, and a first and second electrodes disposed between the first and second electrodes. 1 providing a functional layer; And
A second passive element is mounted on the top of the first passive element, the second passive element being spaced apart from each other, third and fourth electrodes, and a second functional layer disposed between the third and fourth electrodes Including the step of having,
When mounting the second passive element, bonding the third electrode to any one of the first and second electrodes, bonding the fourth electrode to the outer circuit pattern layer,
The second passive element is disposed on the outer circuit pattern layer outside the cavity
A method of manufacturing a printed circuit board.
The method of claim 10,
Mounting the first passive element on the inner circuit pattern layer
And bonding the first and second electrodes to the inner circuit pattern layer using a solder material
Method of manufacturing a printed circuit board.
The method of claim 10,
Mounting the first passive element on the inner circuit pattern layer
Mounting the first and second electrodes so that the upper surfaces of the outer circuit pattern layers are at the same level as the upper surfaces of the outer circuit pattern layer.
Method of manufacturing a printed circuit board.
The method of claim 10,
The step of bonding the third electrode to any one of the first and second electrodes, and bonding the fourth electrode to the outer circuit pattern layer is performed using a solder material.
Method of manufacturing a printed circuit board.
delete delete

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