KR102167298B1 - Static memory device with write assist and control method thereof - Google Patents

Abstract

The present invention relates to a static memory device having a write assist function and a method for controlling the same. The static memory device according to an embodiment includes a memory cell including a plurality of transistors connected between a cell power line and a cell source line, and a memory In response to a precharge circuit that precharges the bit line and bit line bar connected to both ends of the cell and a write control signal, the precharged bit line is connected to the cell source line and the cell power line is connected to the bit line bar. It may include a write assist circuit.

Description

A static memory device having a write assist function and a control method thereof TECHNICAL FIELD

The present invention relates to a static memory device and a control method thereof, and more particularly, to a technical idea of a write assist function of a static memory device.

Transistors have difficulty in realizing the intended threshold voltage (V _th ) due to RDF (Random Dopant Fluctuation), LER (Line Edge Roughness), and WFV (Work Function Variation) occurring during the manufacturing process. have.

That is, the transistor has a variation in the threshold voltage (V _th variation), the threshold voltage becomes a random variable, and the distribution of the threshold voltage follows a Gaussian Distribution.

Meanwhile, the standard deviation of the threshold voltage can be derived through the following equation. That is, referring to the following equation, it can be seen that the V _th variation of the transistor increases as the length and width decrease.

[Equation]

Here, A _Vt is a constant determined according to device and process characteristics, Length is the length of the transistor, and Width is the width of the transistor.

Meanwhile, since a static random access memory (SRAM) device forming a memory cell with a plurality of transistors is manufactured in a very small size for high density integration, it can be greatly affected by V _th variation.

Specifically, in the SRAM device, during the write operation of the memory cell, the strength of the pull-up transistor becomes greater than the strength of the access transistor due to V _th variation, so that data is not flipped. Write Failure) may occur.

Accordingly, in order to prevent a write failure in an SRAM device, a balance of strength between transistors is required. However, if the V _th variation is large, the balance of strength is easily broken. Therefore, a technology capable of improving the V _th variation is required.

However, since the SRAM device is not easy to improve V _th variation due to high integration, a design considering V _th variation is required.

In addition, the SRAM device uses a low voltage supply voltage to implement low power, but under a low voltage supply voltage, the influence of V _th variation increases.

In other words, since the zoom influenced by the SRAM device V _th variation, a design considering the V _th variation under a low voltage environment it is required.

Korean Patent Laid-Open Patent No. 10-2007-0080206 "Semiconductor memory device including static memory cells" Korean Patent Registration No. 10-1579194 "Memory access method and memory device"

The present invention reduces the drain-source voltage (V _DS ) of a pull-up transistor provided in a memory cell by connecting a cell power line and a bit line bar during a write operation, and a bit precharged to the half power voltage (VDD/2) level. An object of the present invention is to provide a static memory device and method capable of reducing the gate-source voltage (V _GS ) of a pull-up transistor by connecting a line and a cell source line.

In addition, the present invention is to provide a static memory device and a method for minimizing write failure by reducing the drain-source voltage (V _DS ) and the gate-source voltage (V _GS ) of a pull-up transistor.

In addition, the present invention does not use a separate voltage source, but the cell source voltage V applied to the cell source line through charge recycling using a bit line precharged to the half power voltage (V _DD /2) level. A static memory device capable of increasing _SSM ) and a method thereof are provided.

In addition, the present invention is a static memory device capable of increasing the voltage applied to the bit line bar through charge recycling using a cell power line to which the cell power voltage (V _DDM ) is applied without using a separate voltage source. And to provide a method thereof.

A static memory device according to an embodiment includes a memory cell including a plurality of transistors connected between a cell power line and a cell source line, a precharge circuit for precharging a bit line and a bit line bar connected to both ends of the memory cell, and In response to a write control signal, a write assist circuit may be included for connecting a precharged bit line to a cell source line and a cell power line to a bit line bar.

According to one side, the precharge circuit may precharge the bit line to the half power voltage (VDD/2) level.

According to one side, the memory cell includes a first access transistor connected to a bit line, a second access transistor connected to a bit line bar, a first pull-up transistor and a second pull-up transistor connected to the cell power line, and a first pull-down connected to the cell source line, respectively. It may include a transistor and a second pull-down transistor.

According to one side, the write assist circuit may include a power voltage transistor connecting the cell power line and the cell power voltage source, and a source voltage transistor connecting the cell source line and the cell source voltage source.

According to one side, the write assist circuit floats the cell power line and the cell source line through the switching operation of the power voltage transistor and the source voltage transistor controlled according to the write control signal, and floats the precharged bit line. It is connected to the source line, and the floating cell power line can be connected to the bit line bar.

According to one side, the write assist circuit includes a first selection transistor connected between the cell power line and the bit line, a second selection transistor connected between the bit line and the cell source line, and a third selection transistor connected between the cell source line and the bit line bar. Including a selection transistor and a fourth selection transistor connected between the bit line bar and the cell power line, and connecting the precharged bit line to the floating cell source line through a switching operation of each of the first to fourth selection transistors, and The cell power line can be connected to the bit line bar.

According to one side, the write assist circuit is connected to the cell power line and the cell source line, respectively, and receives a control signal according to a bit-interleave operation to perform a switching operation for column selection. It may include an interleaved transistor and a second interleaved transistor.

According to one side, the write assist circuit is connected to the bit line and the bit line bar, respectively, and performs a switching operation for changing the voltage of the bit line and the voltage of the bit line bar to a ground level. It may include 2 ground transistors.

A method of controlling a static memory device according to an embodiment includes the steps of precharging a bit line and a bit line bar connected to both ends of a memory cell having a plurality of transistors in a precharge circuit, and writing in a write assist circuit. In response to the control signal, the precharged bit line may be connected to a cell source line connected to the memory cell, and a cell power line connected to the memory cell may be connected to the bit line bar.

According to one side, in the precharging step, the precharge circuit may precharge the bit line to the half power voltage (VDD/2) level.

According to one side, the step of connecting to the bit line bar is a step of floating the cell power line and the cell source line through a switching operation controlled according to the write control signal in the power voltage transistor and the source voltage transistor provided in the write assist circuit. And connecting the precharged bit line to the floating cell source line through the switching operation of each of the first to fourth selection transistors provided in the write assist circuit, and connecting the floating cell power line to the bit line bar. I can.

According to one side, the method for controlling a static memory device according to an embodiment is a connection between a precharged bit line and a floating cell source line through a switching operation of each of the first to fourth selection transistors included in the write assist circuit. The voltage of the bit line and the voltage of the bit line bar through the steps of releasing and releasing the connection between the floating cell power line and the bit line bar, and switching operations of the first ground transistor and the second ground transistor provided in the write assist circuit. It may further include the step of changing to a ground level (Ground Level).

According to an embodiment, during a write operation, the drain-source voltage (V _DS ) of the pull-up transistor provided in the memory cell is reduced by connecting the cell power line and the bit line bar, and the voltage is free to the half power voltage (VDD/2). The gate-source voltage V _GS of the pull-up transistor can be reduced by connecting the charged bit line and the cell source line.

According to an embodiment, by reducing the drain-source voltage (V _DS ) and the gate-source voltage (V _GS ) of the pull-up transistor, write failure may be minimized.

According to an embodiment, the cell source voltage applied to the cell source line through charge recycling using a bit line precharged to the half power voltage (V _DD /2) level without using a separate voltage source ( V _SSM ) can be increased.

According to an embodiment, a voltage applied to a bit line bar may be increased through charge recycling using a cell power line to which the cell power voltage V _DDM is applied without using a separate voltage source.

1 is a diagram illustrating a static memory device according to an embodiment.
2 is a diagram for describing an example of a memory cell included in a static memory device according to an embodiment.
3A is a diagram illustrating a detailed configuration of a static memory device according to an embodiment.
3B is a diagram illustrating an assist control signal generator provided in a static memory device according to an exemplary embodiment.
3C is a diagram illustrating an operation timing of a static memory device according to an exemplary embodiment.
4 is a diagram illustrating a method of controlling a static memory device according to an exemplary embodiment.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification are exemplified only for the purpose of describing the embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention They may be implemented in various forms and are not limited to the embodiments described herein.

Since the embodiments according to the concept of the present invention can apply various changes and have various forms, the embodiments will be illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be named as the second component, Similarly, the second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Expressions describing the relationship between components, for example, "between" and "just between" or "directly adjacent to" should be interpreted as well.

The terms used in the present specification are only used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate that the specified features, numbers, steps, actions, components, parts, or combinations thereof exist, but one or more other features or numbers, It is to be understood that the presence or addition of steps, actions, components, parts or combinations thereof does not preclude the possibility of preliminary exclusion.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this specification. Does not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these embodiments. The same reference numerals in each drawing indicate the same members.

1 is a diagram illustrating a static memory device according to an embodiment.

Referring to FIG. 1, in a static memory device 100 according to an embodiment, during a write operation, a cell power line and a bit line are connected to reduce the drain-source voltage V _DS of a pull-up transistor provided in the memory cell. Write failure can be minimized by reducing the gate-source voltage (V _GS ) of the pull-up transistor by connecting the bit line precharged to the half power voltage (VDD/2) level and the cell source line.

In addition, the static memory device 100 according to an exemplary embodiment does not use a separate voltage source, but uses a bit line precharged to a half power voltage (V _DD /2) through charge recycling. The cell source voltage V _SSM applied to the cell may be increased.

In addition, the static memory device 100 according to an embodiment may increase the voltage applied to the bit line bar through charge recycling using the cell power line to which the cell power voltage V _DDM is applied without using a separate voltage source. have.

In other words, the static memory device 100 according to an embodiment increases the cell source voltage (V _SSM ) and the voltage applied to the bit line bar through charge recycling without a separate voltage source, thereby being used for the size and write operation of the device. Power can be reduced.

To this end, the static memory device 100 according to an embodiment may include a memory cell 110, a precharge circuit 120, and a write assist circuit 130.

For example, the static memory device 100 may be a static random access memory (SRAM) device. In addition, in the static memory device 100, a plurality of memory cells 110 may be formed in an array structure, and in the drawing of reference numeral 100, a memory connected to any one column among the memory cells of the array structure It will be described by showing only the cells 110.

Specifically, the memory cell 110 according to an embodiment may include a plurality of transistors connected between the cell power line and the cell source line.

For example, the memory cell 110 according to an embodiment may be a 6T memory cell including six transistors. In addition, the cell power line may be a line to which the cell power voltage V _DDM is applied, and the cell source line may be a line to which the cell source voltage V _SSM is applied.

According to one side, the precharge circuit 120 may precharge the bit line BL and the bit line bar BLb connected to both ends of the memory cell 110.

According to one side, the precharge circuit 120 may precharge the bit line BL to the half power voltage VDD/2 level.

More specifically, in a static memory device of a 6T structure in which the read port and the write port are the same, if the bit line BL is precharged to 0V, read stability in an unselected column is achieved. ) Problems may occur.

Accordingly, the precharge circuit 120 according to an exemplary embodiment may precharge the bit line BL at the half power voltage (V _DD /2) level in order to improve the write characteristics without a read stability problem in the 6T structure.

In addition, the write assist circuit 130 according to an embodiment connects the precharged bit line BL to the cell source line and connects the cell power line to the bit line bar BLb in response to a write control signal. I can connect.

Here, the voltage of the bit line bar BLb may be discharged from the precharge level to the 0V level.

For example, the write assist circuit 130 is included in a write driver that performs a write operation on the memory cell 110 according to an embodiment, or is separate from the write driver to support a write operation. Can be

Also, the write control signal may be a control signal applied from the write driver.

That is, the write assist circuit 130 according to an embodiment connects the cell power line to which the cell power voltage V _DDM is applied and the bit line BL during a write operation on the memory cell 110 to connect the memory cell ( 110), the gate-source voltage of the pull-up transistor by reducing the drain-source voltage (V _DS ) of the pull-up transistor and connecting the precharged bit line and the cell source line to the half power voltage (V _DD /2) level. By reducing (V _GS ), it is possible to minimize write failure.

In addition, the write assist circuit 130 recycles charges through the connection between the cell power line and the bit line BL, so that a voltage applied to the bit line bar BLb may be increased without using a separate voltage source.

In addition, the write assist circuit 130 is a cell that is applied to the cell source line without using a separate voltage source because charge is recycled through the connection of the bit line BL precharged to the half power voltage (V _DD /2) level. The source voltage V _SSM can be increased.

According to one side, the write assist circuit 130 may connect the cell power line and the bit line and connect the cell source line and the bit line bar according to the data to be written.

Meanwhile, the static memory device 100 according to an embodiment is connected to the bit line BL and the bit line bar BLb, respectively, and receives a control signal according to a bit-interleave operation, and selects a selected row. A plurality of multiplexers connecting the bit line BL corresponding to the column and the bit line bar BLb may be further included.

In other words, the static memory device 100 according to an embodiment does not arrange the memory cells 110 belonging to the same data unit, that is, the same word adjacent to each other, but the memory cells 110 belonging to different words. It may be a memory formed in a bit interleaved structure in which they are arranged adjacent to each other.

A detailed configuration of the static memory device according to the exemplary embodiment described with reference to FIG. 1 will be described in more detail with reference to FIGS. 3A to 3C.

2 is a diagram for describing an example of a memory cell included in a static memory device according to an embodiment.

In other words, the memory cell 200 of FIG. 2 may be the memory cell 110 according to the embodiment described with reference to FIG. 1.

Referring to FIG. 2, a memory cell 200 according to an exemplary embodiment may be formed in a 6T structure including six transistors.

According to one side, the memory cell 200 may include a first access transistor PG1 connected to the bit line BL and a second access transistor PG2 connected to the bit line bar.

In addition, the memory cell 200 includes a first pull-up transistor PU1, a second pull-up transistor PU2 and a cell source voltage V _SSM respectively connected to the cell power line to which the cell power voltage V _DDM is applied. A first pull-down transistor PD1 and a second pull-down transistor PD2 respectively connected to the cell source line may be included.

According to one side, the first access transistor PG1 and the second access transistor PG2 may be composed of NMOS transistors, and the gate terminals of each of the first access transistor PG1 and the second access transistor PG2 are word lines. (WL) can be connected.

In addition, when the memory cell 200 is in any one of a hold, write, and read operation, the word line WL is applied with a gate control signal of a predetermined level so that the first access transistor ( Switching operations of the PG1 and the second access transistor PG2 may be controlled.

Meanwhile, the gate control signal of a predetermined level applied to the word line WL may be a signal applied through a separately provided word line control circuit, and the word line control circuit is a write control signal or a read control signal. The gate control signal can be applied when the control signal is applied.

According to one side, the first pull-up transistor PU1 and the second pull-up transistor PU2 may be composed of PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be composed of NMOS transistors. have.

In addition, gate terminals of the first pull-up transistor PU1 and the first pull-down transistor PD1 are connected to the V _R node, the drain terminal is connected to the V _L node to form one inverter, and the second pull-up transistor PU2 ) And the gate terminal of the second pull-down transistor PD2 are connected to the V _L node, and the drain terminal is connected to the V _R node to form another inverter.

In addition, the inverter formed of the first pull-up transistor PU1 and the first pull-down transistor PD1, and the inverter formed of the second pull-up transistor PU2 and the second pull-down transistor PD2 are cross-coupled. It can be composed of.

Meanwhile, a write operation may be performed in the memory cell 200 according to an exemplary embodiment.

More specifically, in the memory cell 200, the bit line BL reaches the half power voltage (V _DD /2) level, the bit line bar BLB is discharged to 0 V, and the power voltage V _{DD is} applied to the word line WL. ) Is applied, the first access transistor PG1 and the second access transistor PG2 are turned on and the voltage of the bit line BL is discharged to 0V, and V _L '0' may be written to the node and '1' may be written to the V _R node.

However, in the memory cell 200, the strength of the first pull-up transistor PU1 is greater than the strength of the first access transistor PG1 due to V _th variation during the above-described write operation, so that data is not flipped. Write failure may occur.

Accordingly, the write assist circuit according to the temporary example described in FIG. 1 connects the bit line BL precharged with the half power voltage (V _DD /2) to the cell source line and connects the cell power line in response to the write control signal. It can be connected to the bit line bar BLb.

That is, the write assist circuit according to the temporary example reduces the drain-source voltage (V _DS ) and the gate-source voltage (V _GS ) of the first pull-up transistor PU1 through the above-described connection operation, thereby reducing the first pull-up transistor ( Write failure can be minimized by weakening the strength of PU1).

3A is a diagram illustrating a detailed configuration of a static memory device according to an embodiment, and FIG. 3B is a diagram illustrating an assist control signal generator provided in the static memory device according to an embodiment.

In addition, FIG. 3C is a diagram illustrating an operation timing of a static memory device according to an embodiment.

In other words, FIGS. 3A to 3C are diagrams for explaining the detailed configuration and operation of the static memory device according to the exemplary embodiment described with reference to FIGS. 1 to 2, and contents described later with reference to FIGS. 3A to 3C Description of the contents overlapping with those described through the static memory device according to one embodiment will be omitted.

3A to 3C, reference numeral 310 denotes a detailed configuration of a static memory device according to an embodiment including a memory cell 311, a precharge circuit 312, and a write assist circuit 313.

According to one side, the static memory device 310 is connected to the bit line BL and the bit line bar BLb, respectively, and receives a control signal according to a bit-interleave operation to select a selected column. A plurality of multiplexers 314 connecting the bit line BL and the bit line bar BLb may be further included.

According to one side, the write assist circuit 313 includes a power supply voltage transistor P0, a source voltage transistor N0, a first interleaved transistor P1, a second interleaved transistor N1, a first selection transistor P2, and a A second selection transistor N2, a third selection transistor N3, a fourth selection transistor P3, a first ground transistor N4, and a second ground transistor N5 may be included.

Next, reference numeral 320 denotes an assist control signal generator that applies a control signal to the write assist circuit.

Specifically, the assist control signal generator 320 receives the first write word line control signal WWL0 and the second write word line control signal WWL1, and receives the control signal DP0 of the first selection transistor P2. , The control signal DN1 of the second selection transistor N2, the control signal DN0 of the third selection transistor N3, the control signal DP1 of the fourth selection transistor P3, and the first ground transistor A control signal DN2 of (N4) and a control signal DN2b of the second ground transistor N5 may be generated, and the generated control signals may be applied to respective transistors provided in the write assist circuit 313. .

For example, the assist control signal generator 320 may be provided in the static memory device 310 according to an embodiment.

In addition, the first write word line control signal WWL0 and the second write word line control signal WWL1 may be signals generated in response to the write control signals WR and /WR applied to the write assist circuit 313. .

Further, the first write word line control signal WWL0 and the second write word line control signal WWL1 may be signals applied from a write driver that applies the write control signals WR and /WR.

Next, reference numeral 330 denotes a timing diagram according to an operation of a static memory device according to an embodiment.

Specifically,'WL' in reference numeral 330 denotes a signal applied to the word line WL connected to the gate terminals of the first access transistor and the second access transistor provided in the memory cell 311, and'WR' is a power supply. It represents a write control signal applied to the voltage transistor P0.

Further,'WWL0' and'WWL1' in reference numeral 330 denote a first write word line control signal WWL0 and a second write word line control signal WWL1 applied as inputs of the assist control signal generator 320.

In addition,'V _DDM ' in reference numeral 330 denotes the cell power voltage (V _DDM ),'V _SSM ' denotes the cell source voltage (V _SSM ), and'BL' denotes a signal applied to the bit line BL. And'BLb' denotes a signal applied to the bit line bar BLb.

Further, in the reference numeral 330 'V _R' and 'V _L' represents a signal applied to the node V _R and V _L having the node in the memory cell 311.

Hereinafter, a detailed configuration of a static memory device according to an embodiment shown by reference numeral 310 will be described.

Specifically, the precharge circuit 312 according to an exemplary embodiment may precharge the bit line BL and the bit line bar BLb connected to both ends of the memory cell 311.

According to one side, the precharge circuit 312 may precharge the bit line BL to the half power voltage (V _DD /2) level.

Next, the write assist circuit 313 according to an embodiment may connect a precharged bit line to a cell source line and connect a cell power line to a bit line bar in response to the write control signal WR.

According to one side, the power voltage transistor P0 may connect the cell power line and the cell power voltage source, and the source voltage transistor N0 may connect the cell source line and the cell source voltage source.

In other words, the power supply voltage transistor P0 supplies the cell power voltage V _DDM to the cell power line through a switching operation, and the source voltage transistor N0 supplies the cell source voltage V _SSM to the cell source line through the switching operation. ) Can be supplied.

For example, the power voltage transistor P0 may be a PMOS transistor, and the source voltage transistor N0 may be an NMOS transistor.

In addition, the write control signal WR applied to control the switching operation of the power voltage transistor P0 and the control signal /WR applied to control the switching operation of the source voltage transistor N0 are the write driver. Driver).

In addition, if the control signal WR applied to the power voltage transistor P0 is'High', the control signal /WR applied to the source voltage transistor N0 is'Low', and is applied to the power voltage transistor P0. When the control signal WR is'Low', the control signal /WR applied to the source voltage transistor N0 may be'High'.

According to one side, the write assist circuit 313 connects the cell power line and the cell source line through a switching operation of the power voltage transistor P0 and the source voltage transistor N0 controlled according to the write control signals WR and /WR. It can be floated.

Further, the write assist circuit 313 may connect the precharged bit line BL to the floating cell source line, and connect the floating cell power line to the bit line bar BLb.

According to one side, the first selection transistor P2 may be connected between the cell power line and the bit line BL, and the second selection transistor N2 may be connected between the bit line BL and the cell source line.

Also, the third select transistor N3 may be connected between the cell source line and the bit line bar BLb, and the fourth select transistor P3 may be connected between the bit line bar BLb and the cell power line.

For example, the first selection transistor P2 and the fourth selection transistor P3 may be PMOS transistors, and the second selection transistor N2 and the third selection transistor N3 may be NMOS transistors.

In addition, a node provided between the first selection transistor P2 and the second selection transistor N2 and a node provided between the bit line BL and between the third selection transistor N3 and the fourth selection transistor P3 A plurality of multiplexers 314 may be connected between the and the bit line bar BLb.

According to one side, the write assist circuit 313 connects the precharged bit line BL with the floating cell source line through the switching operation of each of the first to fourth selection transistors P2, N2, N3, and P3. , The floating cell power line may be connected to the bit line bar BLb.

According to one side, the first interleaved transistor P1 and the second interleaved transistor N1 are connected to a cell power line and a cell source line, respectively, and receive a control signal according to a bit-interleave operation to select a column ( Switching operation for Column Select) can be performed.

For example, the first interleaved transistor P1 may be a PMOS transistor, and the second interleaved transistor N1 may be an NMOS transistor.

In addition, the first interleaved transistor P1 may be connected between a node provided between the first selection transistor P2 and the fourth selection transistor P3 and a cell power line, and the second interleaved transistor N1 is a second It may be connected between a node provided between the selection transistor N2 and the third selection transistor N3 and a cell source line.

According to one side, a control signal applied to each of the plurality of multiplexers 314, a control signal Sb0 applied to the first interleaved transistor P1, and a control signal S0 applied to the second interleaved transistor N1, respectively, are It may be provided from a separate means for controlling a bit-interleave operation of the static memory device 310 according to an embodiment.

According to one side, the first ground transistor N4 and the second ground transistor N5 are connected to the bit line BL and the bit line bar BLb, respectively, and the voltage of the bit line BL and the bit line bar BLb A switching operation for changing the voltage of) to a ground level may be performed.

For example, the first ground transistor N4 and the second ground transistor N5 may be NMOS transistors.

Hereinafter, with reference to reference numerals 310 to 320, the operation timing of the static memory device shown by reference numeral 330 will be described in more detail.

According to one side, the plurality of multiplexers 314, the first interleaved transistor P1, and the second interleaved transistor N1 maintain a turn-on state as a result of the bit interleaving operation during the period 331 to 335. , It is possible to support a write operation in the memory cell 311 provided in the selected column.

According to one side, in section 331, the precharge circuit 312 may precharge the bit line BL to the half power voltage VDD/2 level.

In addition, in section 331, the power voltage transistor P0 is turned on in response to the'Low' level control signal WR, and the source voltage transistor N0 is the'High' level control signal (/WR). It can be turned on in response to.

In other words, in section 331, the static memory device 310 according to an embodiment may supply a cell power voltage V _DDM to a cell power line and a cell source voltage V _SSM to the cell source line.

Next, in section 332, the first access transistor and the second access transistor provided in the memory cell 311 may be turned on in response to the control signal WL of the'High' level.

In addition, in section 332, the power voltage transistor P0 and the source voltage transistor N0 are turned off, so that the cell power line and the cell source line are floating.

Next, in section 333, the assist control signal generator 320 is a control signal corresponding to the first write word line control signal WWL0 of the'High' level and the second write word line control signal WWL1 of the'Low' level. And provide the generated control signals to each of the transistors included in the write assist circuit 313.

In addition, in response to the control signals provided in section 333, the second selection transistor N2 and the fourth selection transistor P3 are turned on, and the first selection transistor P2 and the third selection transistor P3 are turned on. N3), the first ground transistor N4, and the second ground transistor N5 may be turned off.

In other words, in section 333, the write assist circuit 313 operates between the precharged bit line BL and the floating cell source line according to the switching operation of the first to fourth selection transistors P2, N2, N3, and P3. A path connecting the cells and a path connecting the floating cell power line and the bit line bar BLb may be formed.

According to one side, in section 333, the static memory device 310 according to an embodiment may complete a write operation on the memory cell 311.

Next, in sections 334 to 335, the assist control signal generator 320 corresponds to the first write word line control signal WWL0 of the'Low' level and the second write word line control signal WWL1 of the'High' level. Control signals may be generated, and the generated control signals may be provided to each transistor included in the write assist circuit 313.

In addition, in response to control signals provided in sections 334 to 335, the first to fourth selection transistors P2, N2, N3, and P3 are turned off, and the first ground transistor N4 and the second The ground transistor N5 may be turned on.

In other words, in the period 334 to 335, the write assist circuit 313 is configured to be a precharged bit line BL and a floating cell source line according to the switching operation of the first to fourth selection transistors P2, N2, N3, P3 It is possible to cut off the connection and cut off the connection between the floating cell power line and the bit line bar BLb.

In addition, in the period 334 to 335, the write assist circuit 313 discharges the bit line BL and the bit line bar BLb to the ground level through the first ground transistor N4 and the second ground transistor N5. ).

4 is a diagram illustrating a method of controlling a static memory device according to an exemplary embodiment.

In other words, FIG. 4 is a diagram illustrating a method for controlling a static memory device according to an embodiment described with reference to FIGS. 1 to 3C, and contents described in the static memory device according to an embodiment of the contents described later with reference to FIG. 4 A description that overlaps with will be omitted.

Referring to FIG. 4, in step 410, the method for controlling a static memory device according to an embodiment may precharge bit lines and bit line bars connected to both ends of a memory cell including a plurality of transistors in a precharge circuit. have.

According to one side, in step 410, the method for controlling the static memory device according to an embodiment may precharge the bit line and the bit line bar to the half power voltage (VDD/2) level in the precharge circuit.

Next, in step 420, the method for controlling a static memory device according to an embodiment connects the precharged bit line to the cell source line connected to the memory cell in response to a write control signal in the write assist circuit, The cell power line connected to the cell can be connected to the bit line bar.

According to one side, in step 420, the control method of the static memory device according to an embodiment includes the cell power line and the cell source through a switching operation controlled according to a write control signal in the power voltage transistor and the source voltage transistor provided in the write assist circuit. You can float the line.

Next, in step 420, the method for controlling the static memory device according to an embodiment connects the precharged bit line to the floating cell source line through the switching operation of each of the first to fourth selection transistors provided in the write assist circuit. And, the floating cell power line can be connected to the bit line bar.

According to one side, in step 430, the method for controlling a static memory device according to an embodiment includes a precharged bit line and a floating cell source line through switching operations of each of the first to fourth selection transistors included in the write assist circuit. It is possible to disconnect the connection and disconnect the connection between the floating cell power line and the bit line bar.

In step 440, the control method of the static memory device according to an embodiment is to convert the voltage of the bit line and the voltage of the bit line bar to the ground level through the switching operation of the first ground transistor and the second ground transistor provided in the write assist circuit. It can be changed to (Ground Level).

According to one side, in step 440, the method of controlling a static memory device according to an embodiment precharges the bit line and the bit line bar, changes the cell power line to the cell power voltage (V _DDM ) level, and changes the cell source line to the cell source. It can be changed to the voltage (V _SSM ) level.

In other words, in step 440, the method of controlling a static memory device according to an embodiment changes the cell power line to the cell power voltage level by connecting the cell power line and the cell power voltage source, and connecting the cell source line and the cell source voltage source. And you can change the cell source voltage to the ground level.

In the end, according to the present invention, the drain-source voltage (V _DS ) of the pull-up transistor provided in the memory cell is reduced by connecting the cell power line and the bit line during the write operation, and free to the half power voltage (VDD/2). The gate-source voltage V _GS of the pull-up transistor can be reduced by connecting the charged bit line and the cell source line.

In addition, the present invention may minimize write failure by reducing the drain-source voltage (V _DS ) and the gate-source voltage (V _GS ) of the pull-up transistor.

In addition, the present invention does not use a separate voltage source, but the cell source voltage (V _SSM) applied to the cell source line through charge recycling using a bit line precharged to the half power voltage (V _DD /2) level. ) Can be increased.

In addition, according to the present invention, a voltage applied to a bit line bar can be increased through charge recycling using a cell power line to which the cell power voltage V _DDM is applied without using a separate voltage source.

The apparatus described above may be implemented as a hardware component, a software component, and/or a combination of a hardware component and a software component. For example, the devices and components described in the embodiments include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It can be implemented using one or more general purpose computers or special purpose computers, such as a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications executed on the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to the execution of software. For the convenience of understanding, although it is sometimes described that one processing device is used, one of ordinary skill in the art, the processing device is a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that it may include. For example, the processing device may include a plurality of processors or one processor and one controller. In addition, other processing configurations are possible, such as a parallel processor.

As described above, although the embodiments have been described by the limited drawings, various modifications and variations are possible from the above description to those of ordinary skill in the art. For example, the described techniques are performed in a different order from the described method, and/or components such as a system, structure, device, circuit, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and claims and equivalents fall within the scope of the claims to be described later.

100: static memory device 110: memory cell
120: precharge circuit 130: write assist circuit

Claims (12)

A memory cell including a plurality of transistors connected between the cell power line and the cell source line;
A precharge circuit for precharging a bit line and a bit line bar connected to both ends of the memory cell, and
And a power voltage transistor connecting the cell power line and a cell power voltage source, and a source voltage transistor connecting the cell source line and a cell source voltage source, In response to a write control signal, a write assist circuit for connecting the precharged bit line to the cell source line and connecting the cell power line to the bit line bar
Including,
The light assist circuit is
Floating the cell power line and the cell source line through a switching operation of the power voltage transistor and the source voltage transistor controlled according to the write control signal, and converting the precharged bit line into the floating cell source A line and connecting the floating cell power line to the bit line bar
Static memory device. The method of claim 1,
The precharge circuit is
Precharging the bit line and the bit line bar to a half power voltage (VDD/2) level
Static memory device. The method of claim 1,
The memory cell is
A first access transistor connected to the bit line, a second access transistor connected to the bit line bar, a first pull-up transistor and a second pull-up transistor connected to the cell power line, and a first pull-down transistor connected to the cell source line, respectively, Including 2 pull-down transistors
Static memory device. delete delete The method of claim 1,
The light assist circuit is
A first selection transistor connected between the cell power line and the bit line, a second selection transistor connected between the bit line and the cell source line, and a third selection transistor connected between the cell source line and the bit line bar And a fourth selection transistor connected between the bit line bar and the cell power line,
Connecting the precharged bit line to the floating cell source line through a switching operation of each of the first to fourth selection transistors, and connecting the floating cell power line to the bit line bar.
Static memory device. The method of claim 1,
The light assist circuit is
A first interleaved transistor and a second interleaved transistor connected to the cell power line and the cell source line, respectively, and performing a switching operation for column selection by receiving a control signal according to a bit-interleave operation Including transistor
Static memory device. The method of claim 1,
The light assist circuit is
A first ground transistor and a second ground transistor connected to the bit line and the bit line bar, respectively, and performing a switching operation for changing the voltage of the bit line and the voltage of the bit line bar to a ground level. Included
Static memory device. Precharging a bit line and a bit line bar connected to both ends of a memory cell including a plurality of transistors in a precharge circuit; and
In response to a write control signal in a write assist circuit, connecting the precharged bit line to a cell source line connected to the memory cell, and connecting a cell power line connected to the memory cell to the bit line bar
Including,
Connecting with the bit line bar
Floating the cell power line and the cell source line through a switching operation controlled according to the write control signal in a power voltage transistor and a source voltage transistor provided in the write assist circuit; and
Connecting the precharged bit line to the floating cell source line through a switching operation of each of the first to fourth selection transistors provided in the write assist circuit, and connecting the floating cell power line to the bit line bar. step
Control method of a static memory device comprising a. The method of claim 9,
The precharging step
Precharging the bit line and the bit line bar to a half power voltage (VDD/2) level in the precharge circuit
Control method of static memory device. delete The method of claim 9,
The connection between the precharged bit line and the floating cell source line is released through a switching operation of each of the first to fourth selection transistors provided in the write assist circuit, and the floating cell power line and the bit line Breaking the connection between the bars and
Changing the voltage of the bit line and the voltage of the bit line bar to a ground level through a switching operation of a first ground transistor and a second ground transistor provided in the write assist circuit
Control method of a static memory device further comprising.

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