KR102166644B1 - Electronic system including a plurality of heterogeneous cores and operating method therof - Google Patents

Abstract

According to an embodiment of the present invention, in a method of operating an electronic system including heterogeneous multi-cores, measuring the temperature and workload of the big core, and according to the temperature and workload of the big core, the big There is provided a method of operating an electronic system comprising performing core switching between a core and at least one small core corresponding to the big core. The big core is a high performance and high power core compared to the at least one small core.

Description

Electronic system including a plurality of heterogeneous cores and its operation method {ELECTRONIC SYSTEM INCLUDING A PLURALITY OF HETEROGENEOUS CORES AND OPERATING METHOD THEROF}

The present invention relates to an electronic system and a method of operation thereof, and more particularly to an electronic system including a low-power core and a high-performance core, and a method of operation thereof.

The mobile application processor uses a high-performance core and a low-power core implemented in one chip to ensure fast performance and low current consumption.

The high-performance core has high power consumption, heat generation, and stability problems when used. The low-power core consumes little power, but has limitations in task processing speed and processing capacity.

When the low power core is used and the CPU load increases, the low power core is switched to the high performance core. As the number of high-performance cores used increases, power consumption and heat generation increase significantly. Meanwhile, when the CPU load is reduced, it switches from a high-performance core to a low-power core.

Various switching techniques are being developed to perform more effective temperature management in multi-core processors.

The technical problem to be achieved by the present invention is to provide an electronic system and a method of operating the same for performing more effective temperature management.

According to an embodiment of the present invention, in a method of operating an electronic system including heterogeneous multi-cores, measuring the temperature and workload of the big core, and according to the temperature and workload of the big core, the big There is provided a method of operating an electronic system comprising performing core switching between a core and at least one small core corresponding to the big core.

The electronic system may use in-kernel switching.

The performing of the core switching includes moving a job queue of the big core to the small core when the temperature of the big core reaches a first reference temperature or more, and clocking the big core. Gating or power gating may be included.

The step of moving the job queue of the big core to the small core includes changing a normal DVFS (Dynamic Voltage and Frequency Scaling) table corresponding to the big core to a throttled DVFS table, and the throttle DVFS table May use only the performance area corresponding to the small core.

The normal DVFS table and the throttle DVFS table may be different from each other in a performance area corresponding to the small core.

The electronic system includes a plurality of big cores, and each of the normal DVFS table and the throttle DVFS table may be different according to the number of activations of the big cores.

The performing of the core switching may further include moving the job queue to the big core when the temperature of the big core falls below the second reference temperature.

The second reference temperature may be lower than the first reference temperature.

The temperature of the big core may be measured by a temperature sensor provided in the big core.

The performing of the core switching may further include moving job queues of big cores adjacent to the big core to small cores corresponding to the adjacent big cores according to a preset condition.

The small core corresponding to the big core may be dynamically variable.

The electronic system includes N (N is an integer of 1 or more) of the big cores, M (M is an integer of 1 or more) of the small cores, and N may be different from M.

The electronic system may be a system-on chip (SoC).

According to another embodiment of the present invention, a high-performance cluster including N (N is an integer of 1 or more) high-performance cores, a low-power cluster including M (M is an integer of 1 or more) low-power cores, and the temperature of each of the high-performance cores. Accordingly, an electronic system including a switcher for performing core switching between each of the high-performance cores and at least one low-power core corresponding to the high-performance core is provided.

Each of the high performance cores may be dynamically or statically mapped to any one of the low power cores.

When the temperature of at least one of the high-performance cores reaches a first reference temperature or higher, the switcher may migrate a job queue of the high-performance core to a low-power core corresponding to the high-performance core.

After moving the job queue to the low power core, the switcher may clock gating or power gating the high performance core.

When the temperature of the high-performance core reaches a third reference temperature or higher, the switcher may move job queues of high-performance cores adjacent to the high-performance core to low-power cores corresponding to the high-performance cores adjacent to each other.

When the temperature of each of the high-performance cores falls below the second reference temperature, the switcher may move the job queue of the low-power core corresponding to the high-performance core to each of the high-performance cores.

According to another embodiment of the present invention, each includes a first type core and a second type core having different performance or power characteristics from the first type core, and one of the first type core and the second type core There is provided an electronic system including at least one core pair selectively operating, and a kernel applying different DVFS tables to the core pair according to the temperature and workload of the first type core.

The kernel may control the core pair to operate the second type core of the core pair when the temperature of the first type core is equal to or higher than a first reference temperature.

The kernel applies a throttle DVFS table to the core pair when the temperature of the first type core is equal to or higher than a first reference temperature, and the throttle DVFS table may use only a performance region corresponding to the second type core.

The kernel may control the core pair to operate the first type core of the core pair when the temperature of the first type core is less than or equal to a second reference temperature.

According to another embodiment of the present invention, a first type core and at least one second type core corresponding to the first type core are included, and the first type core and the at least one second type core are selectively selected. A method of operating an electronic system operating as a method, comprising: measuring a temperature of the first type core, determining whether a temperature of the first type core is equal to or higher than a first reference temperature, wherein the temperature of the first type core is When the temperature is higher than the first reference temperature, moving the job queue of the first type core to the at least one second type core, clock gating or power gating the first type core, the temperature of the first type core Determining whether is less than or equal to a second reference temperature, and if the temperature of the first type core is less than or equal to the second reference temperature, moving the job queue of the at least one second type core to the first type core A method of operating a containing electronic system is provided.

In the operating method of the electronic system, determining whether a temperature of the first type core is equal to or higher than a third reference temperature, and if the temperature of the first type core is equal to or higher than the third reference temperature, a second type adjacent to the first type core The step of moving the job queues of the first type cores to the second type cores corresponding to the adjacent first type cores may be further included.

According to an embodiment of the present invention, since core switching is performed between heterogeneous cores according to temperature increase in a heterogeneous multi-core structure, the temperature condition of an application processor (AP) can be satisfied, and With the use of different cores, there is an effect that more effective thermal management can be performed.

1 shows a block diagram of an electronic system according to an embodiment of the present invention.
2 is a block diagram specifically showing the CPU of FIG. 2.
FIG. 3 shows the operation of the CPU of FIG. 2 during in-kernel switching.
4 is a block diagram illustrating the switcher of FIG. 2.
5 shows an example of the operation of the CPU of FIG. 2.
6 shows a DVFS policy applied to each core pair.
7A shows a range of available capabilities according to a DVFS policy according to an embodiment of the present invention.
Figure 7b shows a graph of the performance and power of the core pair of Figure 7a.
7C shows a graph of performance and power of a core pair according to another embodiment of the present invention.
8 is a flowchart showing a method of changing a normal DVFS table to a throttle DVFS table.
9 is a flowchart showing a method of changing a throttle DVFS table to a normal DVFS table.
10 is a flowchart illustrating an embodiment of the operation of the CPU of FIG. 2.
11 is a flow chart showing another embodiment of the operation of the CPU of FIG. 2.
12 is a block diagram showing an embodiment of an electronic system including an SoC according to an embodiment of the present invention.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification are exemplified only for the purpose of describing the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present invention can apply various changes and have various forms, the embodiments will be illustrated in the drawings and described in detail in the present specification. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of the rights according to the concept of the present invention, the first component may be referred to as the second component, and similarly The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in this specification are used only to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate the presence of a set feature, number, step, action, component, part, or combination thereof, but one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this specification. Does not.

Hereinafter, the present invention will be described in detail by describing a preferred embodiment of the present invention with reference to the accompanying drawings.

1 shows a block diagram of an electronic system according to an embodiment of the present invention.

Referring to FIG. 1, an electronic system 1 includes a mobile phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, and a digital Video camera (digital video camera), portable multimedia player (PMP), personal navigation device or portable navigation device (PND), handheld game console, or e-book It can be implemented as a handheld device.

The electronic system 1 includes a system on chip (SoC) 10, an external memory 30, and a display device 20.

The SoC 10 includes a central processing unit (CPU) 100, a read only memory (ROM) 110, a random access memory (RAM) 120, a timer 130, a display controller 140, and graphics processing. It may include a graphics processing unit (GPU) 150, a memory controller 160, a clock management unit (CMU) 170, and a bus 180. The SoC 10 may further include other components in addition to the illustrated components. The electronic system 1 may further include a power management IC (PMIC) 40.

In the embodiment of FIG. 1, the PMIC 40 is implemented outside the SoC 10, but in another embodiment, the SoC 10 is a power management unit capable of performing the function of the PMIC 40. PMU)).

The CPU 100, which may also be referred to as a processor, may process or execute programs and/or data stored in the external memory 30. For example, the CPU 100 may process or execute the programs and/or the data in response to an operation clock signal output from the CMU 170.

The CPU 100 may be implemented as a multi-core processor. The multi-core processor is a computing component having two or more independent substantial processors (referred to as'cores'), each of the processors being program instructions (program instructions). ) Can be read and executed.

Programs and/or data stored in the ROM 110, the RAM 120, and/or the external memory 30 may be loaded into the memory (not shown) of the CPU 100 as needed.

ROM 110 may store permanent programs and/or data.

The ROM 110 may be implemented as an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM).

The RAM 120 may temporarily store programs, data, or instructions. For example, programs and/or data stored in the memory 110 or 30 may be temporarily stored in the RAM 120 under the control of the CPU 100 or a booting code stored in the ROM 110. have. The RAM 120 may be implemented as dynamic RAM (DRAM) or static RAM (SRAM).

The timer 130 may output a count value representing a time based on the operation clock signal output from the CMU 170.

The GPU 150 may convert data read from the external memory 30 by the memory controller 160 into a signal suitable for the display device 20.

The CMU 170 generates an operation clock signal. The CMU 170 may include a clock signal generation device such as a phase locked loop (PLL), a delayed locked loop (DLL), or a crystal oscillator.

The operation clock signal may be supplied to the GPU 150. Of course, the operation clock signal may be supplied to other components (eg, the CPU 100 or the memory controller 160). The CMU 170 may change the frequency of the operating clock signal.

The CPU 100 may include heterogeneous multi-cores, for example, a first type core and a second type core. According to an embodiment, the CPU 100 may further include a third type core in addition to the first type core and the second type core.

Hereinafter, the first type core will be referred to as a high performance core or a big core, and the second type core will be referred to as a low power core, a little core, or a small core.

The CPU 100 allocates a task to a low-power core, measures a CPU load in the low-power core to which the task is assigned, and switches to a high-performance core when the measured CPU load exceeds a workload that can be performed in the low-power core. In addition, based on the measured CPU load, when it is determined that the work load being executed by the high-performance core can be performed by the low-power core, the CPU 100 reverses the switch from the high-performance core to the low-power core.

The memory controller 160 interfaces with the external memory 190. The memory controller 160 overall controls the operation of the external memory 190 and controls data exchange between the host and the external memory 190. For example, the memory controller 160 may write data to the external memory 190 or read data from the external memory 190 at the request of the host. Here, the host is the CPU 100, the GPU 150, or the display It may be a master device such as the controller 140.

The external memory 30 is a storage medium for storing data, and may store an operating system (OS), various programs, and/or various data. The external memory 30 may be, for example, a DRAM, but is not limited thereto.

For example, the external memory 30 may be a nonvolatile memory device (eg, a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM)), or a FeRAM device). In another embodiment of the present invention, the external memory 30 may be an internal memory provided in the SoC 10. Also, the external memory 30 may be a flash memory, an embedded multimedia card (eMMC), or a universal flash storage (UFS).

Each of the components 100, 110, 120, 130, 140, 150, 160, and 170 may communicate with each other through the bus 180.

The display device 20 may display image signals output from the display controller 140. For example, the display device 20 may be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, or a flexible display. .

The display controller 140 controls the operation of the display device 25.

2 is a block diagram specifically showing the CPU of FIG. 2.

2, the CPU 100, that is, the processor includes a high-performance cluster (Big Cluster, 220), a low-power cluster (Little Cluster, 230), a kernel 301, and CCI (Cache Coherent Interconnect, 210). .

At least one application (not shown) executed in the CPU 100 causes a core to perform a task. Kernel 301 receives a task from each application and performs resource allocation for each cluster, that is, each core.

The high performance cluster 220 includes a plurality (eg, N) of high performance cores 221 and a first cache 225. The low power cluster 230 includes a plurality (eg, M) of low power cores 231 and a second cache 235. The high-performance core 221 consumes high power and operates at a high operating frequency. The low power core 231 consumes low power and operates at a low operating frequency. The number of high-performance cores (N) and the number of low-power cores (M) may be different or the same.

The processor 100 includes a high-performance core 221 and a low-power core 231, and operates an appropriate core according to the CPU load provided by each application. The processor 100 operates the low power core 231 when the CPU load is small, and operates the high performance core 221 when the CPU load is large.

In addition, the processor 100 stably operates the SoC 10 by controlling the operation of each core according to external requests such as forcibly adjusting the number of cores during operation, user's configuration, and system setting.

The kernel 301 switches the task from the low power core 231 to the high performance core 221 when the CPU load measured by the low power core 231 exceeds a threshold value. When the CPU load measured by the high performance core 221 is less than the second threshold, the kernel 301 switches the task from the high performance core 221 to the low power core 231. The switching operation of the kernel 301 may be performed even between cores that are not in a pair relationship.

In order to perform core switching between heterogeneous cores by the kernel 301, the second cache 235 is CCI to the first cache 225 or the first cache 225 to the second cache 235 Synchronize data through (210). Due to the synchronization of data between caches through the CCI 210, the switched core can immediately execute a given task during core switching.

The first cache 225 and the second cache 235 are cache memories included in each of the cores 221 and 231.

The kernel 301 may include a switcher 300 for switching cores of different performances.

In this specification, the kernel 301 and the switcher 300 may mean hardware capable of performing functions and operations according to respective names described in this specification, and a computer program capable of performing specific functions and operations. It may mean a code, or an electronic recording medium, such as a processor, on which a computer program code capable of performing a specific function and operation is mounted.

That is, each component 301 and 300 may mean a functional and/or structural combination of hardware for performing the technical idea of the present invention and/or software for driving the hardware.

The switcher 300 transfers a task according to the CPU load from the low-power core 231 to a high-performance core when the CPU load measured by the low-power core 231 exceeds the work capacity of the low-power 231 core. 221). The switcher 300 switches from the high-performance core 221 to the low-power core 231 when the CPU load measured by the high-performance core 221 is smaller than the working capacity of the low-power 231 core.

FIG. 3 shows the operation of the CPU of FIG. 2 during in-kernel switching.

* Referring to FIGS. 2 and 3, when in-kernel switching is used, each of the big cores 221-1 to 221-4 dynamically or statically corresponds to one small core 231-1 to 231-4. Is mapped. When dynamically mapped, the small cores 231-1 to 231-4 corresponding to the big cores 221-1 to 221-4 may be dynamically variable.

One big core and one small core to be mapped constitute a core pair. For example, the Kth (K is an integer greater than or equal to 1) core pair may include the Kth big core 221-K and the Kth little core 231-K.

During in-kernel switching, only one core can be activated by selectively operating in each core pair. For example, only the small cores 231-1 to 231-4 may be activated in each core pair.

The kernel 301 may apply a different Dynamic Voltage and Frequency Scaling (DVFS) table to each core pair according to the temperature of the big cores 221-1 to 221-4.

According to an embodiment, the switcher 300 may perform core switching between a big core and a little core at a DVFS operating point of each core pair.

For example, the switcher 300 migrates the job queue of the first little core 231-1 from the first core pair to the first big core 221-1, and then moves the first little core ( 231-1) can be clock-gated or power-gated.

4 is a block diagram illustrating the switcher of FIG. 2.

Referring to FIG. 4, the switcher 300 operates the high performance cores 221-1 to 221-N or the low power cores 231-1 to 231-M according to the load of the CPU.

For example, when the CPU load measured by the low-power core 231-3 exceeds the working capacity of the low-power core 231-1, the switcher 300 operates from the low-power core 231-3 to the high-performance core ( 221-N). The switcher 300 transfers a task from the high-performance core 221-1 to the low-power core 231 when the CPU load measured by the high-performance core 221-1 is less than the capacity of the low-power 231 core. Switch to -2).

Each high-performance core (eg, 221-1) may be maintained to be in a pair relationship with one low-power core 231-2 corresponding to each high-performance core 221-1.

According to another embodiment, each high-performance core (eg, 221-1) may not form a pair with the low-power core 231-2 when not in use. When each high-performance core 221-1 is in use, it may form a pair with a corresponding low-power core 231-2. At this time, the low power core 231-2 may be in a standby state to enable switching with the high-performance core 221-1.

5 shows an example of the operation of the CPU of FIG. 2.

2 and 5, the temperature of each of the big cores 221-1 to 221-4 may be measured at each preset period. According to an embodiment, each of the big cores 221-1 to 221-4 includes a temperature sensor, and the temperature sensor may measure a temperature. According to another embodiment, a temperature sensor is not built into each of the big cores, and the temperature may be measured in another module adjacent to the big core. According to another embodiment, the temperature sensor may not periodically measure the temperature, and may generate an interrupt when a specific condition is met.

Depending on the temperature of the big core, core switching may be performed between the big core and the small core corresponding to the big core.

For example, the temperature sensor may generate an interrupt when the temperature exceeds a preset first reference temperature. When the temperature of the first big core 221-1 is equal to or higher than the first reference temperature, the switcher 300 sets the job queue of the first big core 221-1 to the first small core 231-1. 1), and clock gating or power gating of the first big core 221-1 may be performed.

In a heterogeneous structure, the small core is thermally safe. Therefore, when throttling occurs in the big core, only the small core is used to prevent thermal attack of the big core, thereby increasing the stability of the electronic system.

The switcher 300 stores the job queues of the big cores (for example, 221-2 and 221-3) adjacent to the first big core 221-1, according to a preset condition, to the adjacent big cores 221-2 and 221. Each of the small cores 231-2 and 231-3 corresponding to -3) can be moved.

For example, when the temperature of the first big core 221-1 is equal to or higher than the third reference temperature, the switcher 300 may match the job queues of the adjacent big cores 221-2 and 221-3 to the corresponding small cores ( 231-2, 231-3) can be moved respectively. The switcher 300 may clock or power gate adjacent big cores 221-2 and 221-3. In this case, the third reference temperature may be a value higher than the first reference temperature.

Therefore, since the temperature of the overheated big core can be cooled more quickly, thermal attack of the big core can be more effectively prevented.

When the temperature of the first big core 221-1 falls below the second reference temperature, the switcher 300 moves the job queue from the first small core 231-1 to the first big core 221-1. I can.

In order to prevent overhead due to frequent core switching, the second reference temperature may be set to a value lower than the first reference temperature.

6 shows a DVFS policy applied to each core pair, and FIG. 7A shows a range of available performance according to a DVFS policy according to an embodiment of the present invention.

2, 6, and 7A, in a heterogeneous core system, each core pair has one job queue (or process, job queue).

The kernel 301 can control each core pair. When the big cores 221-1 to 221-N of each core pair are not overheated, the kernel 301 may use a normal DVFS table for the job queue of each core pair.

In the case of using a normal DVFS table, each core pair uses a core capable of exhibiting performance according to the workload required for the process, and is dynamically or statically mapped to the core. The other cores that are mapped can be power gating.

For example, the first combination to the (X+Y) combination (E1 to E(X+Y)) each represents a frequency and/or voltage, and the first combination (E1) represents the lowest frequency and/or voltage, The (X+Y)th combination (E(X+Y)) may represent the highest frequency and/or voltage.

When using the normal DVFS table, each core pair can operate the small core according to the first combination (E1) when the workload of the process is the lowest, and subtract the big core (X+Y) when the workload of the process is the highest. ) Can be operated according to the combination (E(X+Y)).

When using the big cores 221-1 to 221-N, when one big core (eg, the first big core, 221-1) reaches a first reference temperature or higher, the overheated first big core 221-1 The job queue of must be migrated to the first small core 231-1.

The kernel 301 may apply a throttled DVFS table to the first core pair instead of the normal DVFS table.

According to an embodiment, the throttle DVFS table may use only a performance area corresponding to the first small core 231-1. For example, the throttle DVFS table may use only the first to Xth combinations (E1 to EX).

Accordingly, under the control of the kernel 301, the first big core 221-1 may be power-gated or clock-gated in the first core pair, and the first small core 231-1 may operate.

When the throttle DVFS table is applied when executing a process that requires more than the reference performance P, the first small core 231-1 may use the Xth combination EX. However, embodiments of the present invention are not limited thereto.

Figure 7b shows a graph of the performance and power of the core pair of Figure 7a.

7A and 7B, thermal throttle occurs in the first big core 221-1 that was executing the (X+Y)th combination (E(X+Y)), and the (X+1)th combination When changing to execute (E(X+1)), the first core pair consumes a lot of power due to the high temperature of the first big core 221-1.

On the other hand, even if the first core pair is executing a process that requires high performance, when the first big core 221-1 is overheated and changes to the (X+1)th combination (E(X+1)), The first core pair may exhibit only performance similar to the X-th combination EX of the first small core 231-1.

Accordingly, it may be changed to execute the Xth combination EX by switching from the first big core 221-1 to the first small core 231-1. This has the effect of enabling a more stable operation by consuming less power while producing almost the same performance as compared to the change to execute the existing (X+1) combination (E(X+1)).

7C shows a graph of performance and power of a core pair according to another embodiment of the present invention.

* Referring to FIG. 7C, according to an embodiment, a DVFS table may be configured such that a big core and a small core have a section in which performance overlaps. Comparing the performance-power characteristics of the big core and the small core, when a small core is used instead of a big core, there is a power saving effect at the same performance, and a performance improvement effect at the same power consumption. Therefore, by switching the big core to the corresponding small core, it is possible to efficiently manage performance and power while preventing damage to the big core by heat.

Referring back to FIGS. 2, 6 and 7A, the kernel 301 applies the normal DVFS table to the first core pair instead of the throttle DVFS table when the temperature of the first big core 221-1 is less than the second reference temperature. Thus, the first big core 221-1 of the first core pair can be operated.

In FIG. 7A, the normal DVFS table and the throttle DVFS table are illustrated to have the same combination values (E1 to EX) in the performance region corresponding to the small core. However, according to embodiments, the normal DVFS table and the throttle DVFS table may be set differently in a performance area corresponding to the small core.

For example, in the throttle DVFS table, the number of combinations less than or equal to the reference performance (P) may be set to Z different from X (Z is an integer of 1 or more). Depending on the embodiment, Z may be greater than X.

Therefore, when the process is concentrated on the small core due to overheating of the big core, the small core can be controlled more efficiently.

Each of the normal DVFS table and the throttle DVFS table may be set differently according to the number of activations of the big core. According to an embodiment, each of the normal DVFS table and the throttle DVFS table may be set differently according to the position of the activated big core.

For example, if the big core is activated more or adjacent big cores are activated, the risk due to heat may be greater. Accordingly, the normal DVFS table or the throttle DVFS table of the corresponding core pair may be set to have a lower operating frequency and an operating voltage.

8 is a flowchart showing a method of changing a normal DVFS table to a throttle DVFS table.

8, the temperature of the big core is measured (S11).

It is determined whether the temperature of the big core is higher than the first reference temperature (or the upper limit threshold) (S13).

When the temperature of the big core is higher than the upper limit threshold, the DVFS table of the corresponding core pair is changed to the throttle DVFS table (S15).

9 is a flowchart showing a method of changing a throttle DVFS table to a normal DVFS table.

9, the temperature of the big core is measured (S21).

It is determined whether the temperature of the big core is lower than the second reference temperature (or the lower limit threshold) (S23).

If the temperature of the big core is lower than the lower limit threshold, the DVFS table of the corresponding core pair is changed to the normal DVFS table (S25).

10 is a flowchart illustrating an embodiment of the operation of the CPU of FIG. 2.

2, 3, and 10, the temperature and work amount of each of the big cores (221-1 to 221-4) is measured (S31). The temperature may be measured by a temperature sensor provided in each of the big cores 221-1 to 221-4.

The switcher 300 performs core switching between the big cores 221-1 to 221-4 and the small cores 231-1 to 231-4 according to the temperature and workload of the big cores 221-1 to 221-4. Do (S33).

11 is a flow chart showing another embodiment of the operation of the CPU of FIG. 2.

2, 3, and 11, the kernel 301 determines whether the temperature of the first type core (for example, 221-1) is equal to or higher than the first reference temperature (S41).

When the temperature of the first type core 221-1 is equal to or higher than the first reference temperature, the kernel 301 moves the job queue of the first type core 221-1 to the second type core 231-1 ( S43).

Thereafter, the kernel 301 clock-gates or powers-gates the first type core 221-1 (S45).

Depending on the embodiment, the kernel 301 may determine whether the temperature of the first type core 221-1 is equal to or higher than the third reference temperature. When the temperature of the first type core 221-1 is equal to or higher than the third reference temperature, the kernel 301 is The job queue may be moved to the second type cores 231-2 and 231-3 corresponding to the adjacent first type cores 221-2 and 221-3.

The kernel 301 determines whether the temperature of the first type core 221-1 is less than or equal to the second reference temperature (S47).

If the temperature of the first type core 221-1 is less than or equal to the second reference temperature, the kernel 301 moves the job queue of the second type core 231-1 to the first type core 221-1 ( S49).

12 is a block diagram showing an embodiment of an electronic system including an SoC according to an embodiment of the present invention.

Referring to FIG. 12, the electronic system may be implemented as a personal computer (PC), a data server, or a portable electronic device.

The portable electronic device includes a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, It may be implemented as a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, or an e-book. .

The electronic system includes an SoC 10, a power source 910, a storage 920, a memory 930, an input/output port 940, an expansion card 950, a network device 960, and a display 970. . According to the embodiment. The electronic system may further include a camera module 980.

The SoC 10 may include the CPU 100 shown in FIG. 1. In this case, the CPU 100 may be a multi-core processor.

The SoC 10 may control at least one operation among elements 910 to 980.

The power source 910 may supply an operating voltage to at least one of the components 100 and 910 to 980. The power source 910 may be controlled by the PMIC 40 of FIG. 1.

The storage 920 may be implemented as a hard disk drive or a solid state drive (SSD).

The memory 930 may be implemented as a volatile memory or a nonvolatile memory, and may correspond to the external memory 30 of FIG. 1. According to an embodiment, a memory controller capable of controlling a data access operation for the memory 930, for example, a read operation, a write operation (or a program operation), or an erase operation may be integrated or embedded in the SoC 10 have. According to another embodiment, the memory controller may be implemented between the SoC 10 and the memory 930.

The input/output ports 940 refer to ports through which data is transmitted to an electronic system or data output from the electronic system 10 is transmitted to an external device. For example, the input/output port 940 may be a port for connecting a pointing device such as a computer mouse, a port for connecting a printer, or a port for connecting a USB drive.

The expansion card 950 may be implemented as a secure digital (SD) card or a multimedia card (MMC). According to an embodiment, the expansion card 950 may be a subscriber identification module (SIM) card or a universal subscriber identity module (USIM) card.

The network device 960 refers to a device capable of connecting an electronic system to a wired network or a wireless network.

The display 970 may display data output from the storage 920, the memory 930, the input/output port 940, the expansion card 950, or the network device 960. The display 970 may be the display device 20 of FIG. 1.

The camera module 980 refers to a module capable of converting an optical image into an electrical image. Accordingly, the electrical image output from the camera module 980 may be stored in the storage 920, the memory 930, or the expansion card 950. In addition, the electrical image output from the camera module 980 may be displayed through the display 970.

Although the present invention has been described with reference to an embodiment shown in the drawings, this is only exemplary, and those of ordinary skill in the art will appreciate that various modifications and other equivalent embodiments are possible therefrom . Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the attached registration claims.

1: Electronic System 10: SoC
20: display device 30: external memory
40: PMIC 100: CPU
130: timer 140: display controller
150: GPU 160: memory controller
170: CMU 210: CCI
220: high performance cluster 230: low power cluster
300: switcher 301: kernel
221-1~221-4: Big Core 231-1~231-4: Small Core

Claims (10)

In the operating method of an electronic system including a heterogeneous multi-core processor,
The heterogeneous multi-core processor
A big core cluster including a plurality of big cores including a first big core and a second big core; And
Including a small core cluster comprising a first small core and a second small core,
The first and second big cores are high performance/high power cores, respectively, the first and second small cores are low performance/low power cores, respectively,
The first big core and the first small core are mapped to a first core pair together, the second big core and the second small core are mapped to a second core pair together,
The operation method,
Measuring the temperature of the first big core using a temperature sensor;
Switching at least one task from a first CPU load allocated to the first big core to the first small core when the measured temperature of the first big core exceeds a first reference temperature;
When the measured temperature of the first big core exceeds a second reference temperature higher than the first reference temperature, the plurality of big cores are physically adjacent to the first big core and allocated to the second big core. Switching at least one task from a second CPU load to the second small core;
According to the measured temperature of the first core exceeding the first reference temperature and the determination that the second big core is physically adjacent to the first big core, the first core pair and the second core pair are A method of operating an electronic system, including applying different DVFS (Dynamic Voltage and Frequency Scailing) tables. The method of claim 1,
Switching the at least one task from the first CPU load to the first small core comprises:
Including in-kernel switching to activate only one of the first big core and the first small core at a specified time in the first core pair,
Switching the at least one task from the second CPU load to the second small core comprises:
And in-kernel switching to activate only one of the second big core and the second small core at a specified time in the second core pair. The method of claim 1,
At least one of the first big core and the second big core is at least one of clock gating and power gating until the measured temperature of the first big core falls below a third reference temperature less than the first reference temperature. The method of operating an electronic system, further comprising the step of performing one. The method of claim 3, wherein switching the at least one task from the first CPU load to the first small core,
The first job-queue in which the remaining tasks of the first CPU load of the first big core are stored is moved to the first small core,
Switching the at least one task from the second CPU load to the second small core,
And moving (migrate) the second job-queue in which the remaining tasks of the second CPU load of the second big core are stored to the second small core. The method of claim 4, wherein the step of moving the first job-queue from the first big core to the first small core
The first normal DVFS table for the first big core is changed to a first throttle DVFS table that defines a performance range only for the first small core and used,
The step of moving the second job-queue from the second big core to the second small core
A method of operating an electronic system using a second normal DVFS table for the second big core to a second throttle DVFS table defining a performance range only for the second small core. The method of claim 5, wherein the first normal DVFS table and the first throttle DVFS table are different from each other in defining the respective performance ranges for the first small core,
The second normal DVFS table and the second throttle DVFS table are different from each other in defining respective performance ranges for the second small core. The method of claim 5, wherein the first and second normal DVFS tables and the first and second throttle DVFS tables are
A method of operating an electronic system that varies according to the number of activated big cores among a plurality of big cores in the heterogeneous multi-core processor. The method of claim 1,
Switching the first CPU load from the first small core to the first big core when the measured temperature of the first big core falls below a third reference temperature; And
When the measured temperature of the first big core falls below a fourth reference temperature, switching the second CPU load from the second small core to the second big core. . Including heterogeneous multi-core porcelain,
The heterogeneous multi-core processor
A plurality of big cores including a first big core and a second big core, and a plurality of small cores including a first small core and a second small core,
The first big core and the first small core are mapped together as a first core pair, and the second big core and the second small core are mapped together as a second core pair,
The first big core and the second big core operate at high performance/high power, respectively, compared to the first small core and the second small core;
According to a determination as to whether the measured temperature at the first core exceeds a first reference temperature and whether the second big core is physically adjacent to the first big core, the first core pair and the second core pair An electronic system including a kernel that applies a different DVFS (Dynamic Voltage and Frequency Scaling) table to each. In claim 9, the kernel
As long as the measured temperature of the first big core is maintained below the first reference temperature, a first normal DVFS table is applied to the first core pair, and a second normal DVFS table is applied to the second core pair. ,
If the measured temperature of the first big core exceeds the first reference temperature, the kernel applies a first throttle DVFS table to the first core pair and a second throttle DVFS table to the second core pair. , Electronic system.

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