KR102165776B1 - 시스템 성능 향상을 위한 적응적 값 범위 프로파일링 - Google Patents

시스템 성능 향상을 위한 적응적 값 범위 프로파일링 Download PDF

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KR102165776B1
KR102165776B1 KR1020187021915A KR20187021915A KR102165776B1 KR 102165776 B1 KR102165776 B1 KR 102165776B1 KR 1020187021915 A KR1020187021915 A KR 1020187021915A KR 20187021915 A KR20187021915 A KR 20187021915A KR 102165776 B1 KR102165776 B1 KR 102165776B1
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memory
memory addresses
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KR20180099819A (ko
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마우리키오 브레터니츠
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
KR1020187021915A 2016-01-25 2017-01-18 시스템 성능 향상을 위한 적응적 값 범위 프로파일링 Active KR102165776B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662286618P 2016-01-25 2016-01-25
US62/286,618 2016-01-25
US15/130,793 US10019365B2 (en) 2016-01-25 2016-04-15 Adaptive value range profiling for enhanced system performance
US15/130,793 2016-04-15
PCT/US2017/013934 WO2017132026A1 (en) 2016-01-25 2017-01-18 Adaptive value range profiling for enhanced system performance

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KR20180099819A KR20180099819A (ko) 2018-09-05
KR102165776B1 true KR102165776B1 (ko) 2020-10-14

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US (2) US10387315B2 (enExample)
EP (1) EP3408748B1 (enExample)
JP (1) JP6725671B2 (enExample)
KR (1) KR102165776B1 (enExample)
CN (1) CN108496160B (enExample)
WO (1) WO2017132026A1 (enExample)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10402326B1 (en) * 2016-04-26 2019-09-03 Apple Inc. Accessing memories in coherent and non-coherent domains in a computing system
CN107870916A (zh) * 2016-09-23 2018-04-03 伊姆西Ip控股有限责任公司 存储管理方法及设备
US10402355B2 (en) 2017-02-08 2019-09-03 Texas Instruments Incorporated Apparatus and mechanism to bypass PCIe address translation by using alternative routing
US11385926B2 (en) * 2017-02-17 2022-07-12 Intel Corporation Application and system fast launch by virtual address area container
US10528478B2 (en) * 2017-05-30 2020-01-07 Ati Technologies Ulc Page table management for differing virtual and physical address page alignment
US10761743B1 (en) 2017-07-17 2020-09-01 EMC IP Holding Company LLC Establishing data reliability groups within a geographically distributed data storage environment
DE102017217807B4 (de) * 2017-10-06 2026-08-06 Bayerische Motoren Werke Aktiengesellschaft Verfahren und vorrichtung zum verarbeiten einer software-aktualisierung
US10880040B1 (en) 2017-10-23 2020-12-29 EMC IP Holding Company LLC Scale-out distributed erasure coding
US10382554B1 (en) 2018-01-04 2019-08-13 Emc Corporation Handling deletes with distributed erasure coding
US10496457B2 (en) 2018-04-02 2019-12-03 Micron Technology, Inc. Grouping requests to reduce inter-process communication in memory systems
US10579297B2 (en) 2018-04-27 2020-03-03 EMC IP Holding Company LLC Scaling-in for geographically diverse storage
US10936196B2 (en) 2018-06-15 2021-03-02 EMC IP Holding Company LLC Data convolution for geographically diverse storage
US11023130B2 (en) 2018-06-15 2021-06-01 EMC IP Holding Company LLC Deleting data in a geographically diverse storage construct
US11099753B2 (en) * 2018-07-27 2021-08-24 EMC IP Holding Company LLC Method and apparatus for dynamic flow control in distributed storage systems
US10997083B2 (en) * 2018-09-04 2021-05-04 Arm Limited Parallel page table entry access when performing address translations
US11436203B2 (en) 2018-11-02 2022-09-06 EMC IP Holding Company LLC Scaling out geographically diverse storage
US10901635B2 (en) 2018-12-04 2021-01-26 EMC IP Holding Company LLC Mapped redundant array of independent nodes for data storage with high performance using logical columns of the nodes with different widths and different positioning patterns
US11232039B2 (en) 2018-12-10 2022-01-25 Advanced Micro Devices, Inc. Cache for storing regions of data
US11119683B2 (en) 2018-12-20 2021-09-14 EMC IP Holding Company LLC Logical compaction of a degraded chunk in a geographically diverse data storage system
US10931777B2 (en) 2018-12-20 2021-02-23 EMC IP Holding Company LLC Network efficient geographically diverse data storage system employing degraded chunks
US10892782B2 (en) 2018-12-21 2021-01-12 EMC IP Holding Company LLC Flexible system and method for combining erasure-coded protection sets
US11023331B2 (en) 2019-01-04 2021-06-01 EMC IP Holding Company LLC Fast recovery of data in a geographically distributed storage environment
US10942827B2 (en) 2019-01-22 2021-03-09 EMC IP Holding Company LLC Replication of data in a geographically distributed storage environment
US10942825B2 (en) 2019-01-29 2021-03-09 EMC IP Holding Company LLC Mitigating real node failure in a mapped redundant array of independent nodes
US10936239B2 (en) 2019-01-29 2021-03-02 EMC IP Holding Company LLC Cluster contraction of a mapped redundant array of independent nodes
US10866766B2 (en) 2019-01-29 2020-12-15 EMC IP Holding Company LLC Affinity sensitive data convolution for data storage systems
US10846003B2 (en) 2019-01-29 2020-11-24 EMC IP Holding Company LLC Doubly mapped redundant array of independent nodes for data storage
US11029865B2 (en) * 2019-04-03 2021-06-08 EMC IP Holding Company LLC Affinity sensitive storage of data corresponding to a mapped redundant array of independent nodes
US10944826B2 (en) 2019-04-03 2021-03-09 EMC IP Holding Company LLC Selective instantiation of a storage service for a mapped redundant array of independent nodes
US11121727B2 (en) 2019-04-30 2021-09-14 EMC IP Holding Company LLC Adaptive data storing for data storage systems employing erasure coding
US11119686B2 (en) 2019-04-30 2021-09-14 EMC IP Holding Company LLC Preservation of data during scaling of a geographically diverse data storage system
US11113146B2 (en) 2019-04-30 2021-09-07 EMC IP Holding Company LLC Chunk segment recovery via hierarchical erasure coding in a geographically diverse data storage system
US11748004B2 (en) 2019-05-03 2023-09-05 EMC IP Holding Company LLC Data replication using active and passive data storage modes
US11209996B2 (en) 2019-07-15 2021-12-28 EMC IP Holding Company LLC Mapped cluster stretching for increasing workload in a data storage system
US11449399B2 (en) 2019-07-30 2022-09-20 EMC IP Holding Company LLC Mitigating real node failure of a doubly mapped redundant array of independent nodes
US11023145B2 (en) 2019-07-30 2021-06-01 EMC IP Holding Company LLC Hybrid mapped clusters for data storage
US11228322B2 (en) 2019-09-13 2022-01-18 EMC IP Holding Company LLC Rebalancing in a geographically diverse storage system employing erasure coding
US11449248B2 (en) 2019-09-26 2022-09-20 EMC IP Holding Company LLC Mapped redundant array of independent data storage regions
US11288139B2 (en) 2019-10-31 2022-03-29 EMC IP Holding Company LLC Two-step recovery employing erasure coding in a geographically diverse data storage system
US11435910B2 (en) 2019-10-31 2022-09-06 EMC IP Holding Company LLC Heterogeneous mapped redundant array of independent nodes for data storage
US11119690B2 (en) 2019-10-31 2021-09-14 EMC IP Holding Company LLC Consolidation of protection sets in a geographically diverse data storage environment
US11169927B2 (en) * 2019-11-22 2021-11-09 EMC IP Holding Company LLC Efficient cache management
US11435957B2 (en) 2019-11-27 2022-09-06 EMC IP Holding Company LLC Selective instantiation of a storage service for a doubly mapped redundant array of independent nodes
US11144220B2 (en) 2019-12-24 2021-10-12 EMC IP Holding Company LLC Affinity sensitive storage of data corresponding to a doubly mapped redundant array of independent nodes
US11231860B2 (en) 2020-01-17 2022-01-25 EMC IP Holding Company LLC Doubly mapped redundant array of independent nodes for data storage with high performance
CN111274163B (zh) * 2020-03-27 2024-11-26 西安紫光国芯半导体有限公司 储存级存储器的双列直插式存储模块装置及其缓存方法
US11507308B2 (en) 2020-03-30 2022-11-22 EMC IP Holding Company LLC Disk access event control for mapped nodes supported by a real cluster storage system
US11294808B2 (en) 2020-05-21 2022-04-05 Micron Technology, Inc. Adaptive cache
US20210374056A1 (en) * 2020-05-28 2021-12-02 Samsung Electronics Co., Ltd. Systems and methods for scalable and coherent memory devices
US11288229B2 (en) 2020-05-29 2022-03-29 EMC IP Holding Company LLC Verifiable intra-cluster migration for a chunk storage system
US11422934B2 (en) * 2020-07-14 2022-08-23 Micron Technology, Inc. Adaptive address tracking
US11409657B2 (en) * 2020-07-14 2022-08-09 Micron Technology, Inc. Adaptive address tracking
US11507516B2 (en) 2020-08-19 2022-11-22 Micron Technology, Inc. Adaptive cache partitioning
US11693983B2 (en) 2020-10-28 2023-07-04 EMC IP Holding Company LLC Data protection via commutative erasure coding in a geographically diverse data storage system
US11379281B2 (en) * 2020-11-18 2022-07-05 Akamai Technologies, Inc. Detection and optimization of content in the payloads of API messages
US11847141B2 (en) 2021-01-19 2023-12-19 EMC IP Holding Company LLC Mapped redundant array of independent nodes employing mapped reliability groups for data storage
US11625174B2 (en) 2021-01-20 2023-04-11 EMC IP Holding Company LLC Parity allocation for a virtual redundant array of independent disks
US11354191B1 (en) 2021-05-28 2022-06-07 EMC IP Holding Company LLC Erasure coding in a large geographically diverse data storage system
US11449234B1 (en) 2021-05-28 2022-09-20 EMC IP Holding Company LLC Efficient data access operations via a mapping layer instance for a doubly mapped redundant array of independent nodes
US11899589B2 (en) * 2021-06-22 2024-02-13 Samsung Electronics Co., Ltd. Systems, methods, and devices for bias mode management in memory systems
US11625175B1 (en) * 2021-06-29 2023-04-11 Amazon Technologies, Inc. Migrating virtual resources between non-uniform memory access (NUMA) nodes
CN117980876A (zh) * 2021-10-27 2024-05-03 华为技术有限公司 内存控制器和用于内存系统的内存控制器的方法
JP7801011B2 (ja) * 2021-11-01 2026-01-16 Necソリューションイノベータ株式会社 キャッシュ制御装置、情報処理装置、キャッシュ制御方法、プログラム及び記録媒体
EP4469891A4 (en) * 2022-02-23 2025-03-26 Huawei Technologies Co., Ltd. Cache based memory access tracking
CN119292764B (zh) * 2022-06-15 2025-05-30 华为技术有限公司 数据处理方法、装置、电子设备以及计算机可读存储介质
US12468624B2 (en) * 2024-03-11 2025-11-11 Trustteks Ltd. Hot-data-based decision-making method for using in a storage device of a computer
US12566745B1 (en) * 2024-06-11 2026-03-03 Vast Data Ltd. Splitting a node of a tree data structure
US12645362B2 (en) 2024-09-25 2026-06-02 Ati Technologies Ulc Systems and methods for providing extended memory access in a parallel processor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100169602A1 (en) 2008-12-29 2010-07-01 Jared E Hulbert Method and Apparatus for Efficient Memory Placement
US20120124323A1 (en) 2010-11-12 2012-05-17 Inventec Corporation Method for setting memory address space
US20120137075A1 (en) 2009-06-09 2012-05-31 Hyperion Core, Inc. System and Method for a Cache in a Multi-Core Processor
US20130185475A1 (en) 2012-01-12 2013-07-18 Fusion-Io, Inc. Systems and methods for cache profiling
US20150169227A1 (en) 2013-12-16 2015-06-18 International Business Machines Corporation Adaptive statistics for a linear address space

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6233667B1 (en) * 1999-03-05 2001-05-15 Sun Microsystems, Inc. Method and apparatus for a high-performance embedded memory management unit
US7562179B2 (en) * 2004-07-30 2009-07-14 Intel Corporation Maintaining processor resources during architectural events
WO2007072324A2 (en) * 2005-12-20 2007-06-28 Nxp B.V. Multi-processor circuit with shared memory banks
US7757045B2 (en) * 2006-03-13 2010-07-13 Intel Corporation Synchronizing recency information in an inclusive cache hierarchy
US7930513B2 (en) * 2006-11-04 2011-04-19 Virident Systems Inc. Writing to asymmetric memory
US8706914B2 (en) * 2007-04-23 2014-04-22 David D. Duchesneau Computing infrastructure
US20100169708A1 (en) * 2008-12-29 2010-07-01 John Rudelic Method and apparatus to profile ram memory objects for displacment with nonvolatile memory
JP5702808B2 (ja) * 2011-01-12 2015-04-15 パナソニック株式会社 プログラム実行装置およびコンパイラシステム
US8977803B2 (en) * 2011-11-21 2015-03-10 Western Digital Technologies, Inc. Disk drive data caching using a multi-tiered memory
US9424191B2 (en) * 2012-06-29 2016-08-23 Intel Corporation Scalable coherence for multi-core processors
US9330736B2 (en) * 2012-11-09 2016-05-03 Qualcomm Incorporated Processor memory optimization via page access counting
CN103744799B (zh) * 2013-12-26 2017-07-21 华为技术有限公司 一种内存数据访问方法、装置和系统
US20170060434A1 (en) * 2015-08-27 2017-03-02 Samsung Electronics Co., Ltd. Transaction-based hybrid memory module

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100169602A1 (en) 2008-12-29 2010-07-01 Jared E Hulbert Method and Apparatus for Efficient Memory Placement
US20120137075A1 (en) 2009-06-09 2012-05-31 Hyperion Core, Inc. System and Method for a Cache in a Multi-Core Processor
US20120124323A1 (en) 2010-11-12 2012-05-17 Inventec Corporation Method for setting memory address space
US20130185475A1 (en) 2012-01-12 2013-07-18 Fusion-Io, Inc. Systems and methods for cache profiling
US20150169227A1 (en) 2013-12-16 2015-06-18 International Business Machines Corporation Adaptive statistics for a linear address space

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
L. Ramos, et al., "Page Placement in Hybrid Memory Systems", ICS’11, pp. 85-95, May 31, 2011.

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US20170212845A1 (en) 2017-07-27
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CN108496160A (zh) 2018-09-04
US10387315B2 (en) 2019-08-20
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