KR102144185B1 - Processing In Memory Device using a Conventional Memory Bus - Google Patents

Abstract

A method of operating a PIM using an existing commercial memory bus without modification and a PIM device to which this method is applied are provided. A processing in memory (PIM) device according to an embodiment of the present invention includes a memory for storing data; A memory control device that reads and writes data from a corresponding address in the memory; An input/output device for receiving an address, data, and command; Including, the input/output device receives a destination address through an address signal, and receives a packet including a command to be executed by the computing device, an operand address, and data through the DQ signal. can do.
Accordingly, PIM can be implemented without modification of hardware and software of the existing computer system, and in particular, PIM can be used in all commercial motherboards using PSRAM.

Description

Processing In Memory Device using a Conventional Memory Bus}

The present invention relates to a PIM (processing in memory) device compatible with a traditional computer system, and more particularly, a PIM protocol using a commercially available memory bus, a packet structure, an operation method, and a hardware structure of the PIM device. About.

The reason why PIM is not easily commercialized despite the continuous research and development of PIM is the problem of compatibility with existing computer systems as the biggest cause. The compatibility problem with the existing system can be largely divided into hardware and software aspects. To overcome this, a complex approach of hardware and software is inevitable, and this approach can only be realized by persuading the existing market and seeking cooperation.

The hardware compatibility problem between PIM and existing systems is caused by the vertical memory hierarchy of the existing computer system. Today's computer systems rely on caches to solve memory bottlenecks so that even small embedded system application processors (APs) use multiple layers of cache, so it is hard to expect that processors will give up cache in the future. However, the cache is a method of providing a memory address that is repeatedly accessed by referring to previously accessed data. In PIM, even if the same address is accessed, the data to be written or read may vary depending on the operation being performed. Therefore, when PIM and cache are used together, a cache consistency problem and cache coherence problem occur individually or simultaneously.

Existing memory buses are also an obstacle to using PIM. The main memory bus used by most systems today follows the JEDEC standard. This standard memory bus is a fixed-latency method with a constant response time for read and write. On the other hand, a variable-latency memory bus is required because PIM processes operation instructions in addition to read/write operations. In addition, a channel capable of transmitting not only read/write, address, and data of the existing memory channel, but also information for PIM operation to the PIM without damage, must be prepared in hardware.

The problem of software compatibility between PIM and existing systems stems from the memory management of the operating system. Most operating systems today use virtual memory, and a virtual address for virtual memory is mapped to a physical address through the processor's memory management unit (MMU) to access the real physical memory (a processor that does not have an MMU is used. In some systems, the OS performs the MMU function). However, in order to use the operation function of PIM, the physical address of the operand required for the operation must be clearly indicated, but the virtual address used in the software is managed in a non-contiguous allocated page unit. It is very difficult to accurately predict all physical addresses.

The best way to overcome the problems described so far is to develop an interface only for PIM, and provide technical support so that the processor, motherboard, peripheral device, operating system, etc. that intend to use PIM can use PIM. However, this requires persuading the existing market and seeking cooperation, as mentioned earlier. In the case of HMC (hybrid memory cube), it has reached the level of technical commercialization by various manufacturers and research groups, but due to the peculiarity of the interface, it is not compatible with the existing system.

The present invention has been conceived to solve the above problems, and an object of the present invention is to provide a method for operating a PIM using an existing commercial memory bus without modification, and a PIM device to which the method is applied.

According to an embodiment of the present invention for achieving the above object, a PIM (processing in memory) device includes a memory in which data is stored; A memory control device that reads and writes data from a corresponding address in the memory; An input/output device for receiving an address, data, and command; Including, the input/output device receives a destination address through an address signal, and receives a packet including a command to be executed by the computing device, an operand address, and data through the DQ signal. can do.

The length of the packet is. It may be determined by the memory size, the number of instructions, and the size of data words.

The packet may be transmitted to the input/output device in the same manner as a data write operation through a write burst protocol of a memory.

The input/output device may change the received packet into control information that can be processed by the computing device and transmit it to the computing device.

The memory control device may store an operation result of the operation device in a destination address of a memory, and the stored operation result may be accessible to the system through a read protocol.

The input/output device may indicate that the processing device is not ready to process the next packet by leaving a specific signal in an invalid state when the processing device is processing a previously received command.

The input/output device may store and wait for an address signal and a WE signal received when the processing device is processing a command previously received.

The input/output device may activate a processing waiting signal for notifying that there is a next packet waiting.

The input/output device may deactivate the processing waiting signal when receiving the next packet waiting or changing a specific signal to a valid state.

On the other hand, according to another embodiment of the present invention, a PIM (processing in memory) method includes: receiving, by an input/output device, a destination address through an address signal; Receiving, by the input/output device, a packet including a command to be executed by the computing device, an operand address, and data through the DQ signal; Performing, by the computing device, an instruction; And storing, by the memory control device, a result of executing the command in a memory.

Meanwhile, according to another embodiment of the present invention, a computing system includes a processing in memory (PIM) device; And a system for storing data in the PIM device, wherein the PIM device includes: a memory for storing data; A memory control device that reads and writes data from a corresponding address in the memory; An input/output device for receiving an address, data, and command; Including, the input/output device may receive a destination address through an address signal and a packet including an instruction to be executed by the computing device through a DQ signal.

On the other hand, according to another embodiment of the present invention, a PIM (processing in memory) method includes: transmitting, by a system, a destination address to an input/output device of a PIM (processing in memory) device; Transmitting, by the system, to an input/output device of the PIM device through a DQ signal, a packet including a command to be executed by the computing device of the PIM device, an operand address, and data; The operation device of the PIM device, performing an instruction; And storing, by the memory control device of the PIM device, a result of executing the command in the memory.

As described above, according to embodiments of the present invention, PIM can be implemented without modification of hardware and software of an existing computer system, and in particular, PIM can be used in all commercial motherboards using PSRAM. .

1 is a PSRAM 4-word burst read operation,
2 is a PSRAM 4-word burst write operation,
3 is a block diagram of a hardware structure of a PIM device;
4 is a PIM packet structure,
5 is a PIM packet transmission method,
6 is a logic circuit for preserving a destination address and a read/write command of a packet waiting to be processed;
7 is a logic circuit for generating a signal to be processed,
8 is a prototype of a PIM device according to an embodiment of the present invention, and,
9 is a table comparing image processing results processed by PIM and CPU.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

In an embodiment of the present invention, a PIM device using a commercial memory bus is presented. Specifically, we propose a PIM protocol, a packet structure, an operation method, and a hardware structure of a PIM device using a commercially available memory bus to be compatible with a traditional computer system.

To this end, in an embodiment of the present invention, a PIM interface is implemented using a protocol of a conventional pseudostatic random-access memory (PSRAM), which is a conventional memory, without modification, and a PIM packet structure capable of using the PSRAM bus as it is. It proposes a hardware structure of a PIM device using a PSRAM bus.

In an embodiment of the present invention, a PIM (processing in memory) device using a JEDEC pseudostatic SRAM (PSRAM) bus, a packet structure, and an operation method are provided. To aid in understanding the embodiments of the present invention, features of the PSRAM and the PSRAM bus will be first described.

PSRAM is a DRAM that incorporates a refresh circuit and an address-decoder, and is a memory that combines the high integration of DRAM and the ease of access of SRAM.

During read or write operation of PSRAM, refreshes and collisions may occur internally. For this case, PSRAM bus is a variable response delay method, unlike other DRAM-based memory buses that use a fixed latency bus protocol. latency) of the bus protocol.

In order to provide accurate timing of read and write according to the variable response delay method, the PSRAM memory bus uses WAIT signals, and the PSRAM controller can read read data or input write data according to the state of the WAIT signal.

In addition, the burst length is selectable, and the delay time between the DQ signal outputting valid data after the WAIT signal is asserted is also selectable. The protocol of the PSRAM bus is shown in Figs. 1 and 2.

In Figures 1 and 2, the ADV # signal indicates a valid address period, and CE # is used as a chip select signal and WE # is used as a write enable signal. DQ is a data signal, but since it is a bi-directional bus, the input/output direction of the current DQ is determined through the OE # signal.

The WAIT signal is a signal sent from the PSRAM to the system. In the read mode, the WAIT signal is asserted before the PSRAM outputs the requested address data, indicating that the data output from the DQ is valid. In write mode, the PSRAM asserts a WAIT signal when it is ready to receive write data, and the memory controller transmits the write data according to the promised burst length and timing.

The PIM according to an embodiment of the present invention is the same as the PSRAM in terms of basic functions of a memory. DRAM is used as a core-memory and has built-in address-decoder and refresh circuit. In addition, it provides some computational functions. The hardware structure of the PIM device is shown in FIG. 3.

A PIM device according to an embodiment of the present invention, as shown in FIG. 3, includes an input/output device 110, an operation device 120, a memory control device 130, and a DRAM 140.

The DRAM 140 is used as an internal memory of the PIM, and major DRAM operations such as address decoding and refresh are controlled by the memory control device 130.

The computing device 120 executes a command code received from the input/output device 110 of the PIM, and performs basic operations and calculation functions of the memory.

The input/output device 110 decomposes the PIM access packet according to the PSRAM bus protocol, transmits it so that the computing device 120 can process it, and responds with the result.

Since the PIM proposed in the embodiment of the present invention uses a commercial memory bus, only some control signals and signals such as addresses and data are used. Therefore, in order to transmit an operation instruction to the PIM, the existing memory bus must be operated in a different way.

The structure of a PIM packet proposed in an embodiment of the present invention is shown in FIG. 4, and a method of transmitting the PIM packet using a PSRAM bus is shown in FIG.

PIM performs basic memory functions and operation functions, and these functions can be used for specific functions through instruction codes of packets. In FIG. 4, the destination address is used as an address to which the result of a write and read command and an operation command is applied. The command code represents the command to be executed by the PIM device.

The operation instructions executed by PIM are largely divided into R-type and I-type. When executing R-type instructions, data necessary for operation is retrieved through the operand address (recall), and the I-type instruction is a packet The value of the data field included in is used as an operand.

All functions of the instruction code require a destination address, and operand addresses and data are required according to the type of instruction to perform other operation functions.

Since the destination address is required for all PIM access, the address signal of the PSRAM bus is used as the destination address as shown in FIG. 5. Since the DQ signal is used to transmit the packet to the PIM device, all packets except the read command of the PIM use the write protocol of the PSRAM bus.

The length of the PIM packet is determined by the size of the accessible memory inside the PIM, the number of instructions, and the size of the system's data words. For example, in a system with 64 MB of PIM, 64 operations, and 32-bit words, the length of the PIM packet is 64 bits.

These packets are delivered to the PIM in the same way as data write operations through the PSRAM write burst protocol. The PIM device analyzes the received packet by the input/output device 110 of FIG. 3, converts the received packet into control information that can be processed by the computing device 120, and transmits it.

Since all operation commands are transmitted by the write protocol of the PSRAM bus, the operation result is also applied to the destination address, and this value can be accessed through a separate read command.

Therefore, the PIM read command proposed in the embodiment of the present invention does not use the PIM packet but uses the read protocol of the PSRAM bus as it is. The processing time of the PIM packet varies depending on the type of the command to be processed. In particular, the processing time becomes longer when overlapping with the reflash operation of the DRAM 140 during packet processing.

Since the PSRAM bus protocol does not know at all information on the packet processing process of the current PIM, some commands may not be properly executed when the system transmits consecutive commands to the PIM.

In an embodiment of the present invention, the WAIT signal of the PSRAM bus is used to solve this problem and ensure the reliability of command transmission. When the PIM is processing a previously received command, it leaves the WAIT signal in an invalid state and indicates that it is not ready to process the next packet. Even if the system makes a read request, the PIM makes the system wait through the WAIT signal.

However, since the address signal and WE # signal used as the destination address are sent from the system to the PIM regardless of the WAIT signal, the waiting address signal and WE # signal must be preserved. Preserving the waiting address signal and WE # signal is processed by the input/output device 110 of FIG. 3, and a logic circuit for this is as shown in FIG. 6. 6 is a logic circuit for preserving a destination address of a packet waiting to be processed and a read/write command.

In addition, after PIM processes one packet, it must inform whether there is a next packet already waiting. To this end, the input/output device 110 internally creates and uses a pending flag, and a logic circuit for creating a processing pending signal is shown in FIG. 7. 7 is a logic circuit for generating a signal to be processed.

The processing waiting signal remains active-high if there is a pending destination address and read and write commands, and when the PIM receives the rest of the pending packets or makes the WAIT signal valid to respond to a read request, the processing wait signal is generated. By making it active-low, it informs that there is no packet waiting to be processed.

After median-filter processing a 24-bit color photo of 512x512 size through the PIM developed through the embodiment of the present invention, the results of the CPU processing were compared. The system using PIM used an embedded system that supports an external memory bus, and the external memory bus supports the PSRAM bus. The processor of the system used is an ARM coretex-A9 based AP, and the OS is 32-bit Linux 4.1.15. The external memory bus is also managed as virtual memory in Linux. The entire PIM address area is mapped at once using the maximum page size allowed by the system, and the physical address of the PIM is accurately predicted and accessed through the offset value of the address.

The processing result is shown in FIG. 9. When the same algorithm is performed as shown in FIG. 9, the calculation result is the same as the CPU and PIM, but the processing time is improved by 20 times or more than the processing time of the CPU.

Up to now, a preferred embodiment has been described in detail for a processing in-memory device using a commercial memory bus.

In an embodiment of the present invention, a PIM device capable of using an existing commercial memory bus, a PIM packet structure, and a PIM operation method are presented, so that the PSRAM is not required to modify the hardware and software of the existing computer system in order to use PIM. PIM can be used on all commercial motherboards used.

Meanwhile, in the present specification, the address and the DQ bus are expressed as two buses for conceptual understanding. However, the actual operation of the DQ bus does not have a separate DQ bus (based on the PSRAM standard), and the address bus set as a bi-directional bus can be used interchangeably with DQ. At this time, the address and data are It should be noted that the classification is made through MUX.

In addition, although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention claimed in the claims. In addition, various modifications are possible by those of ordinary skill in the art, and these modifications should not be individually understood from the technical idea or perspective of the present invention.

110: input/output device
120: computing device
130: memory control device
140: DRAM

Claims (12)

A memory in which data is stored;
A memory control device that reads and writes data from a corresponding address in the memory;
An input/output device for receiving an address, data, and command;
Including; a computing device that performs an instruction on the data,
The input/output device is:
Through the address signal, receive the destination address,
Through the DQ signal, a packet containing an instruction to be executed, an operand address, and data is received, and
If the processing unit is processing a previously received command, it leaves the WAIT signal in an invalid state, indicating that it is not ready to process the next packet,
A PIM (processing in memory) device, characterized in that when the processing unit is processing a previously received command, the received Address signal and WE signal are preserved and waited.
The method according to claim 1,
The length of the packet is.
A PIM (processing in memory) device, characterized in that it is determined by a memory size, a number of instructions, and a size of a data word.
The method according to claim 1,
Packet,
A PIM (processing in memory) device, characterized in that it is transmitted to an input/output device in the same manner as a data write operation through a write burst protocol of memory.
The method of claim 3,
The input/output device is:
A PIM (processing in memory) device, characterized in that the received packet is changed into control information that can be processed by the computing device and transmitted to the computing device.
The method of claim 4,
The memory control device,
Saves the operation result of the operation device to the destination address of the memory,
The saved calculation result is,
A PIM (processing in memory) device, characterized in that the system can access it through a read protocol.
delete delete The method according to claim 1,
The input/output device is:
PIM (processing in memory) device, characterized in that for activating a processing waiting signal for notifying that there is a next packet waiting.
The method of claim 8,
The input/output device is:
A PIM (processing in memory) device, characterized in that, upon receiving a next packet waiting or changing a specific signal to a valid state, inactivating a processing waiting signal.
Receiving, by an input/output device, a destination address through an address signal;
Receiving, by the input/output device, a packet including a command to be executed by the computing device, an operand address, and data through the DQ signal;
Performing, by the computing device, an instruction;
And storing, by the memory control device, a result of executing the command in a memory,
The input/output device is:
If the processing unit is processing a previously received command, it leaves the WAIT signal in an invalid state, indicating that it is not ready to process the next packet,
When the processing unit is processing a previously received command, the PIM (processing in memory) method, characterized in that for waiting by preserving the received Address signal and WE signal.
Processing in memory (PIM) devices; And
Including; a system for storing data in the PIM device,
The PIM device,
A memory in which data is stored;
A memory control device that reads and writes data from a corresponding address in the memory;
An input/output device for receiving an address, data, and command;
Including; a computing device that performs an instruction on the data,
The input/output device is:
Through the address signal, receive the destination address,
Through the DQ signal, a packet containing an instruction to be executed by the computing device is received,
The input/output device is:
If the processing unit is processing a previously received command, it leaves the WAIT signal in an invalid state, indicating that it is not ready to process the next packet,
When the computing device is processing a command previously received, the computing system is characterized in that the received Address signal and WE signal are stored and waited.
Transmitting, by the system, a destination address to an input/output device of a processing in memory (PIM) device through an address signal;
Transmitting, by the system, to an input/output device of the PIM device through a DQ signal, a packet including a command to be executed by the computing device of the PIM device, an operand address, and data;
The operation device of the PIM device, performing an instruction;
Including, by the memory control device of the PIM device, storing the command execution result in a memory,
The input/output device of the PIM device is:
If the processing unit is processing a previously received command, it leaves the WAIT signal in an invalid state, indicating that it is not ready to process the next packet,
When the processing unit is processing a previously received command, the PIM (processing in memory) method, characterized in that for waiting by preserving the received Address signal and WE signal.

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