KR102143186B1 - Cell balancing circuit - Google Patents

Abstract

The present invention relates to a cell balancing circuit which controls four switches constituting a direct current (DC)-DC buck-boost converter and one additional balancing operation exclusive switch to control voltage charged in each cell to remain the same.

Description

Cell balancing circuit {CELL BALANCING CIRCUIT}

The present invention relates to a cell balancing circuit.

Supercapacitors are devices that have a much larger capacitance than conventional capacitors. It has a long life due to a high charge/discharge cycle and is expected to be a next-generation energy storage device that can replace batteries in recent years because of the advantage that it can supply a large amount of current instantly. However, due to the limitations of the device itself, the maximum voltage that can be charged to one cell is about 2.5V, and in order to charge a voltage higher than that, several cells must be connected in series.

In a series-connected supercapacitor, even if the same supercapacitor with the same capacity is connected in series due to a mismatch between leakage resistance and capacitance inside the device, the voltage charged in each supercapacitor cell is different. In this case, the overcharged supercapacitor cell is damaged and does not operate, or the lifespan is shortened, so that the replacement cycle of the supercapacitor cell is shortened. To prevent this, a cell balancing circuit is required so that each supercapacitor cell can be charged with the same voltage.

The structure of a commonly used supercapacitor cell balancing circuit is shown in FIGS. 1 and 2.

1 is a diagram showing a supercapacitor cell balancing circuit using a balancing resistor.

As shown in FIG. 1, by connecting a resistor R having the same resistance value to both ends of the supercapacitor cells CAP1 and CAP2 in parallel, it is possible to maintain the same voltage at both ends of the supercapacitor cells. Although it is simple to implement, there is a problem in that the energy stored in the supercapacitor cell decreases because a leakage current continuously flows through the resistor R, thereby reducing energy efficiency.

2 is a diagram showing a supercapacitor cell balancing circuit using an operational amplifier (op-amp).

As shown in FIG. 2, after generating a voltage of 1/2 of the charging voltage using two resistors R having the same resistance value, each supercapacitor cell CAP1 is generated using an operational amplifier composed of a buffer. , CAP2) can be adjusted so that the charged voltage is the same. In this case, since the operational amplifier continuously consumes current, and the amount of current flowing in the operational amplifier must be increased for fast balancing operation, energy efficiency decreases and storage performance decreases as in the method using the resistor described in FIG. 1A. There is a problem.

It is intended to provide a cell balancing circuit capable of improving energy efficiency and reducing power consumption and circuit area.

According to one aspect of the invention, a first switch, an inductor, and a second switch connected between an input terminal and an output terminal, a third switch connected between a first node and a ground to which the first switch and the inductor are connected, A fourth switch connected between a ground and a second node to which the inductor and the second switch are connected, and a third node to which the first node and the first supercapacitor cell and the second supercapacitor cell are connected, A balancing logic unit that compares the voltage sensed voltage of the fifth switch and the third node with a first reference voltage and a second reference voltage, and determines whether a balancing operation is required according to the comparison result, and a determination result of the balancing logic unit In the first balancing situation, the second switch and the third switch are first turned on, and if the determination result of the balancing logic unit is a second balancing situation, the second supercapacitor cell is discharged, and then the second switch and the third switch are turned on. And a switch control circuit for turning on a third switch, wherein the first balancing condition is that the voltage of the first supercapacitor cell is higher than the voltage of the second supercapacitor cell, and the second balancing condition is the second supercapacitor The voltage of the cell may be higher than the voltage of the first supercapacitor cell.

In the first balancing situation, during the ON period of the second switch and the third switch, the first supercapacitor cell and the second supercapacitor cell may discharge.

The switch control circuit may turn on the fourth switch and the fifth switch after an on period of the second switch and the third switch ends in the first balancing situation.

In the first balancing situation, the second supercapacitor cell may be charged during the ON period of the fourth switch and the fifth switch.

The switch control circuit may turn on the fourth switch and the fifth switch when discharging the second supercapacitor cell in the second balancing situation.

The switch control circuit may charge the first supercapacitor cell and the second supercapacitor cell during the ON period of the second switch and the third switch in the second balancing situation.

The cell balancing circuit further includes a first comparator for comparing the sense voltage and a first reference voltage, and a second comparator for comparing the sense voltage and a second reference voltage, and the balancing logic unit includes the first comparator And it may be determined that a balancing operation is required according to the output of the second comparator.

One end of the first supercapacitor cell is connected to the output terminal, the other end of the first supercapacitor cell and one end of the second supercapacitor cell are connected to the third node, and the other end of the second supercapacitor cell It is connected to this ground, and the first reference voltage may be higher than the second reference voltage.

The cell balancing circuit, when the sense voltage is higher than the first reference voltage, the balancing logic unit determines the second balancing condition, and when the sense voltage is lower than the second reference voltage, the balancing logic unit It can be determined as the first balancing situation.

The cell balancing circuit includes a current sampling unit for sensing a current flowing through the inductor, a first sampling switch connected between the first node and the current sampling unit, and between the second node and the current sampling unit. It may further include a second sampling switch connected.

The switch control circuit, in the first balancing situation, turns on the second sampling switch, turns off the first sampling switch, in the second balancing situation, turns on the first sampling switch, The second sampling switch may be turned off.

It provides a cell balancing circuit capable of improving energy efficiency and reducing power consumption and circuit area.

1 is a diagram showing a supercapacitor cell balancing circuit using a balancing resistor.
2 is a diagram showing a supercapacitor cell balancing circuit using an operational amplifier (op-amp).
3 is a circuit diagram showing a cell balancing circuit according to an embodiment.
4A and 4B are diagrams for describing a balancing operation of a cell balancing circuit according to an exemplary embodiment in a first balancing situation.
5A and 5B are diagrams for describing a balancing operation of a cell balancing circuit according to an exemplary embodiment in a second balancing situation.

The present invention relates to a power supply device and a cell balancing circuit capable of controlling and implementing balancing between supercapacitor cells included in the power supply device. In order to solve the problem of reducing the efficiency of the DC-DC converter used for charging due to continuous power consumption of the conventional cell balancing circuits, the cell balancing circuit of the present invention may be implemented as a cell balancing circuit of a switch control method, and specifically , Cell balancing operation may be performed using a DC-DC buck-boost converter included in the power supply device. Specifically, the cell balancing circuit can maintain the same voltage charged in each cell by controlling four switches constituting the DC-DC buck-boost converter and one additional switch dedicated for balancing operation.

According to an embodiment of the present invention, when cell balancing is not required, the power supply device converts an input voltage into an output voltage through a DC-DC buck-boost converter and supplies it. When balancing between supercapacitor cells is required, a DC-DC buck-boost converter and a balancing switch perform a cell balancing operation. Hereinafter, for convenience of description, the power supply device and the cell balancing circuit are collectively referred to as a cell balancing circuit.

Hereinafter, with reference to the accompanying drawings, an embodiment of the present invention will be described in detail so that those of ordinary skill in the art can easily implement the present invention. However, the present invention may be implemented in various different forms and is not limited to the exemplary embodiment described herein. In addition, in order to clearly describe the present invention in the drawings, parts irrelevant to the description are omitted, and like reference numerals are assigned to similar parts throughout the specification.

In addition, in the following description, the connection between the configuration and the configuration is an electrical connection, and not only a direct connection, but also does not exclude that other configurations may be additionally connected, although not specifically shown and described.

3 is a circuit diagram showing a cell balancing circuit according to an embodiment.

As shown in Fig. 3, the cell balancing circuit 1 is connected to two supercapacitor cells 2 and 3 connected in series. The cell balancing circuit (1) includes a DC-DC buck-boost converter, and the DC-DC buck-boost converter includes four switches (S1-S4) and an inductor (10). do. The cell balancing circuit 1 further includes a switch S5 and two sampling switches 21 and 22 for current sampling as a switch dedicated to the balancing operation.

The current sampling unit 20 senses the current by sampling the current flowing to the ground through one of the sampling switches 21 and 22 turned on, and a signal indicating the magnitude of the sensed current (hereinafter, a current detection signal) ( ISE) can be generated and output to the switch control circuit 30.

The cell balancing circuit 1 includes two comparators 50 and 60 and a balancing logic unit 40 to determine whether balancing is necessary.

The comparator 50 compares the detection voltage VCM of the node N4 between the cells of the two supercapacitors 2 and 3 with the upper limit reference voltage VR1, and compares the first comparison signal BS1 according to the comparison result. Generate. The comparator 60 compares the sense voltage VCM with the lower limit reference voltage VR2, and generates a second comparison signal BS2 according to the comparison result. The upper limit reference voltage VR1 may be a value obtained by adding a predetermined margin a to 1/2 of the output voltage VOUT, and the lower limit reference voltage VR2 is equal to 1/2 of the output voltage VOUT. It may be the value minus a).

Specifically, when the sensing voltage VCM is lower than the lower limit reference voltage VR2, the second comparison signal BS2 falls to a low level, and the balancing logic unit 40 is the low level second comparison signal BS2. Accordingly, it is determined that the voltage of the supercapacitor cell 2 is higher than the voltage of the supercapacitor cell 3 and thus a first balancing situation that requires balancing. When the sensing voltage VCM is higher than the upper limit reference voltage VR1, the first comparison signal BS1 falls to a low level, and the balancing logic unit 40 is superimposed according to the low level first comparison signal BS1. Since the voltage of the capacitor cell 3 is higher than the voltage of the supercapacitor cell 2, it is determined as a second balancing situation requiring balancing.

In the case of the first balancing situation, the balancing logic unit 40 generates a balancing control signal BCS of the first level indicating this, and in the case of the second balancing situation, the balancing control signal BCS of the second level indicating this. ) Can be created. For example, a balancing control signal BCS of a relatively high level indicates a first balancing situation (voltage of 2> a voltage of 3), and a balancing control signal BCS of a relatively low level indicates a second balancing situation ( Voltage of 3> voltage of 2) can be indicated. In addition, when balancing is not required, that is, when the sensing voltage VCM is between the upper limit reference voltage VR1 and the lower limit reference voltage VR2 (both BS1 and BS2 are at high levels), the A balancing control signal BCS of a third level different from the first level and the second level may be generated. However, the invention is not limited thereto, and different balancing control signals may be triggered according to each balancing situation using at least two balancing control signals.

When the first level of the balancing control signal BCS is received, the switch control circuit 30 controls a balancing operation of discharging the supercapacitor cell 2 and charging the supercapacitor cell 3, and balancing the second level. When the control signal BCS is received, a balancing operation of discharging the supercapacitor cell 3 and charging the supercapacitor cell 2 is controlled. The balancing operation control of the switch control circuit 30 will be described later with reference to FIGS. 4A, 4B, 5A, and 5B.

The switch control circuit 30 may receive a feedback voltage corresponding to the output voltage VOUT and control the switching operation of the switches S1-S4 to regulate the output voltage VOUT. The operation of controlling the output voltage VOUT is a power control operation applied to a general power supply device, and a detailed description thereof will be omitted.

Hereinafter, a configuration of the cell balancing circuit 1 according to an embodiment and a connection relationship thereof will be described with reference to FIG. 3.

As shown in FIG. 3, both ends of the switch S1 are connected between the input terminal N0 and the node N1, and a gate voltage VG1 is supplied to the gate of the switch S1. Both ends of the switch S2 are connected between the node N1 and the ground, and the gate voltage VG2 is supplied to the gate of the switch S2. Both ends of the switch S3 are connected between the node N2 and the ground, and the gate voltage VG3 is supplied to the gate of the switch S3. Both ends of the switch S4 are connected between the node N2 and the output terminal N3, and a gate voltage VG4 is supplied to the gate of the switch S4. Both ends of the switch S5 are connected between the node N1 and the node N4, and a gate voltage VG5 is supplied to the gate of the switch S5.

Since the switches S1, S4, and S5 are P-channel type transistors, the on level of the gate voltages VG1, VG4, and VG5 is a low level, and the off level is a high level. Since the switches S2 and S3 are N-channel type transistors, the on level of the gate voltages VG2 and VG3 is a high level, and the off level is a low level.

The inductor 10 is connected between the node N1 and the node N2. The sampling switch 21 is connected between the node N1 and the current sampling unit 20, and the sampling switch 21 is switched by the sampling signal SS1. The sampling switch 22 is connected between the node N2 and the current sampling unit 20, and the sampling switch 22 is switched by the sampling signal SS2.

The supercapacitor cells 2 and 3 are connected in series between the output terminal N3 and the ground, and the node N4 to which the two supercapacitor cells 2 and 3 are connected is the inverting terminal (-) of the comparator 50 and It is connected to the non-inverting terminal (+) of the comparator 60.

Hereinafter, the operation of the cell balancing circuit 1 in the first balancing situation will be described with reference to FIGS. 4A and 4B.

4A and 4B are diagrams for describing a balancing operation of a cell balancing circuit according to an exemplary embodiment in a first balancing situation.

As shown in FIGS. 4A and 4B, the balancing operation in the first balancing situation according to an embodiment may be performed according to the switching operation of the other switches S2-S5 in the off state of the switch S1. .

First, after the first balancing condition is detected by the balancing logic unit 40, the switch control circuit 30 turns off the switch S1. First, as shown in Fig. 4A, the switch control circuit 30 turns on the switches S2 and S4, and turns off the switches S3 and S5. At this time, the switch control circuit 30 turns on the switch 22 and turns off the switch 21, so that the current sampling unit 20 is connected to the node N2 to sense the current IL. To be. Since the switch S1 is turned off during the cell balancing operation, it is assumed that the current (load current) supplied to the load from the current IL flowing through the inductor 10 is not included.

If the load current is omitted, the current IL flows through the on-state switches S2 and S4 and the supercapacitor cells 2 and 3. The on-period of the switches S2 and S4 shown in FIG. 4A is D*T, which is the product of the period (T) of the switching frequency and the on-duty ratio (D). Specifically,'T' is the period of the switching frequency of the switches S2-S5 in the balancing operation, and D is the on-duty ratio obtained by dividing the ON period of the switches S2 and S4 by the period T of the switching frequency. . During the ON period of the switches S2 and S4, the voltage change of each of the supercapacitor cells 2 and 3 is as shown in Equations 1 and 2 below.

[Equation 1]

△VC1 = -(IL/C1)*D*T

[Equation 2]

△VC1 = -(IL/C2)*D*T

In Equations 1 and 2, each of C1 and C2 denotes a capacity of each of the supercapacitor cells 2 and 3.

Subsequently, as shown in FIG. 4B, the switch control circuit 30 turns on the switches S3 and S5, and turns off the switches S2 and S4.

The switches S3 and S5 are in the ON state for a period of (1-D)T, and if the load current part is omitted during this period, no current flows in the supercapacitor cell 2, and the current IL is the switch S3, It flows to the supercapacitor cell 3 through S5), and charges are charged in the supercapacitor cell 3 by the current IL. During the ON period ((1-D)T) of the switches S3 and S5, the voltage change of each of the supercapacitor cells 2 and 3 is as shown in Equations 3 and 4 below.

[Equation 3]

△VC1 = 0

[Equation 4]

△VC2 = (IL/C2)*(1-D)*T

4A and 4B are repeated, and before the balancing operation starts, the voltage VC1 of the supercapacitor cell 2 was higher than the voltage VC2 of the supercapacitor cell 3, but the switch for balancing Whenever one period of the switching frequency of (S2-S5) passes, ΔVC1 (= -(IL/C1)*D*T) of Equation 1 is added to the voltage VC1 of the supercapacitor cell 2, The sum of ΔVC2 in Equations 2 and 4 (=(IL/C2)*(1-2D)*T) is added to the voltage VC2 of the supercapacitor cell 3. The D value can be controlled to a value less than 0.5.

That is, in one period of the switching frequency of the switches S2-S5, since the voltage change amount of the voltage VC1 is a negative value (=-(IL/C1)*D*T), the voltage VC1 decreases, The voltage change amount of the voltage VC2 is a positive value (=(IL/C2)*(1-2D)*T), and the voltage VC2 increases. Accordingly, as the balancing switching operation is repeated, the difference between the voltage VC1 and the voltage VC2 gradually decreases.

As a result, the voltage VCM comes into the range between the upper limit reference voltage VR1 and the lower limit reference voltage VR2, and the first and second comparison signals BC1 and BC2, which are outputs of the comparators 50 and 60, respectively. Are all high level. Then, the balancing logic unit 40 outputs the third level balancing control signal BCS to the switch CL control circuit 30, the switch control circuit 30 stops the balancing operation, and regulates the output voltage VOUT. Controls the buck-boost operation for

5A and 5B are diagrams for describing a balancing operation of a cell balancing circuit according to an exemplary embodiment in a second balancing situation.

As shown in FIGS. 5A and 5B, the balancing operation in the second balancing situation according to an embodiment may be performed according to the switching operation of the other switches S2-S5 in the off state of the switch S1. .

First, after the second balancing condition is sensed by the balancing logic unit 40, the switch control circuit 30 turns off the switch S1. First, as shown in Fig. 5A, the switch control circuit 30 turns on the switches S3 and S5, and turns off the switches S2 and S4. At this time, the switch control circuit 30 turns on the switch 21 and turns off the switch 22, so that the current sampling unit 20 is connected to the node N1 to detect the current IL. To be.

If the load current part is omitted, current does not flow in the supercapacitor cell 2, and the current IL flows from the supercapacitor cell 3 through the switches S3 and S5, and the supercapacitor cell 3 is discharged. The on-period of the switches S3 and S5 shown in FIG. 5A is D*T, which is the product of the period T of the switching frequency and the on-duty ratio D. Specifically,'T' is the period of the switching frequency of the switches S2-S5 in the balancing operation, and D is the on-duty ratio obtained by dividing the ON period of the switches S3 and S5 by the period T of the switching frequency. . During the ON period of the switches S3 and S5, the voltage change of each of the supercapacitor cells 2 and 3 is as shown in Equations 5 and 6 below.

[Equation 5]

△VC1 = 0

[Equation 6]

△VC2 = -(IL/C2)*D*T

In Equation 6, C2 denotes the capacity of the supercapacitor cell 3.

Subsequently, as shown in Fig. 5B, the switch control circuit 30 turns on the switches S2 and S4, and turns off the switches S3 and S5.

The switches (S2, S4) are on for a period of (1-D) * T, and if the load current part is omitted during this period, the current (IL) is transferred to the supercapacitor cells (2, 3) through the switches (S2, S4) ), and the supercapacitors 2 and 3 are charged. During the ON period of the switches S2 and S4, the voltage change of each of the supercapacitor cells 2 and 3 is as shown in Equations 7 and 8 below.

[Equation 7]

△VC1 = (IL/C1)*(1-D)*T

[Equation 8]

△VC2 = (IL/C2)*(1-D)*T

When the operation shown in FIGS. 5A and 5B is repeated and the voltage VC1 is lower than the voltage VC2 before the balancing operation starts, but one cycle of the switching frequency of the switches S2-S5 for balancing passes Each time, ΔVC1 = (IL/C1)*(1-D)*T is added to the voltage VC1 of the supercapacitor cell 2, and Equations 6 and 8 are added to the voltage VC2 of the supercapacitor cell 2 The sum of ΔVC2 of (=(IL/C2)*(1-2D)*T) is added.

That is, in one period of the switching frequency of the switches S2-S5, the voltage change amount of the voltage VC2 is a negative value (=(IL/C2)*(1-2D)*T), so the voltage VC2 is Decreases, and the voltage change amount of the voltage VC1 becomes a positive value (= (IL/C1)*(1-D)*T), and the voltage VC1 increases. Accordingly, as the balancing switching operation is repeated, the difference between the voltage VC1 and the voltage VC2 gradually decreases. In this case, the D value may be controlled to a value greater than 0.5.

As a result, the sensing voltage VCM comes into the range between the upper limit reference voltage VR1 and the lower limit reference voltage VR2, and the first and second comparison signals BC1 and BC2, which are outputs of the comparators 50 and 60, respectively. ) Are all high level. Then, the balancing logic unit 40 outputs the third level balancing control signal BCS to the switch CL control circuit 30, the switch control circuit 30 stops the balancing operation, and regulates the output voltage VOUT. Controls the buck-boost operation for

In the present invention, by using the switches S2-S4 for the balancing operation, only one current sampling unit is required. Then, it is possible to minimize the power consumption and area generated by the current sampling unit.

Although an embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention defined in the following claims are also present. It belongs to the scope of rights of

1: cell balancing circuit
2, 3: supercapacitor cell
10: inductor
20: current sampling unit
30: switch control circuit
40: balancing logic unit
50, 60: comparator

Claims (11)

A first switch, an inductor, and a second switch connected between the input terminal and the output terminal,
A third switch connected between a ground and a first node to which the first switch and the inductor are connected,
A fourth switch connected between a ground and a second node to which the inductor and the second switch are connected,
A fifth switch connected between the first node and a third node to which the first supercapacitor cell and the second supercapacitor cell are connected,
A balancing logic unit that compares the sense voltage, which is the voltage of the third node, with a first reference voltage and a second reference voltage, and determines whether a balancing operation is necessary according to the comparison result, and
If the determination result of the balancing logic unit is in a first balancing situation, first turn on the second switch and the third switch, and if the determination result of the balancing logic unit is a second balancing situation, after discharging the second supercapacitor cell, And a switch control circuit for turning on the second switch and the third switch,
In the first balancing situation, the voltage of the first supercapacitor cell is higher than the voltage of the second supercapacitor cell, and in the second balancing situation, the voltage of the second supercapacitor cell is higher than the voltage of the first supercapacitor cell. High,
Cell balancing circuit. The method of claim 1,
In the first balancing situation, during the ON period of the second switch and the third switch, the first supercapacitor cell and the second supercapacitor cell discharge,
Cell balancing circuit. The method of claim 1,
The switch control circuit,
In the first balancing situation, after the on period of the second switch and the third switch ends,
Turning on the fourth switch and the fifth switch,
Cell balancing circuit. The method of claim 3,
In the first balancing situation, during the ON period of the fourth switch and the fifth switch, the second supercapacitor cell is charged,
Cell balancing circuit. The method of claim 1,
The switch control circuit,
In the second balancing situation, when discharging the second supercapacitor cell,
Turning on the fourth switch and the fifth switch,
Cell balancing circuit. The method of claim 1,
The switch control circuit,
In the second balancing situation, during the ON period of the second switch and the third switch,
The first supercapacitor cell and the second supercapacitor cell are charged,
Cell balancing circuit. The method of claim 1,
A first comparator for comparing the sensed voltage and a first reference voltage, and
Further comprising a second comparator for comparing the sense voltage and a second reference voltage,
The balancing logic unit,
Determining whether a balancing operation is required according to the outputs of the first comparator and the second comparator,
Cell balancing circuit. The method of claim 7,
One end of the first supercapacitor cell is connected to the output terminal, the other end of the first supercapacitor cell and one end of the second supercapacitor cell are connected to the third node, and the second supercapacitor cell The other end is connected to the ground, and the first reference voltage is higher than the second reference voltage,
Cell balancing circuit. The method of claim 8,
When the sense voltage is higher than the first reference voltage, the balancing logic unit determines that the second balancing condition is
When the sense voltage is lower than the second reference voltage, the balancing logic unit determines that the first balancing situation,
Cell balancing circuit. The method of claim 1,
A current sampling unit for sensing a current flowing through the inductor,
A first sampling switch connected between the first node and the current sampling unit, and
Further comprising a second sampling switch connected between the second node and the current sampling unit,
Cell balancing circuit. The method of claim 10,
The switch control circuit,
In the first balancing situation, turning on the second sampling switch, turning off the first sampling switch,
In the second balancing situation, turning on the first sampling switch and turning off the second sampling switch,
Cell balancing circuit.

Images