KR102138697B1 - 캐시 태그 압축을 위한 방법 및 장치 - Google Patents

캐시 태그 압축을 위한 방법 및 장치 Download PDF

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KR102138697B1
KR102138697B1 KR1020177033433A KR20177033433A KR102138697B1 KR 102138697 B1 KR102138697 B1 KR 102138697B1 KR 1020177033433 A KR1020177033433 A KR 1020177033433A KR 20177033433 A KR20177033433 A KR 20177033433A KR 102138697 B1 KR102138697 B1 KR 102138697B1
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tag
entry
order bits
memory
cache
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KR20180008507A (ko
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3세 헨리 아더 펠리린
토마스 필립 스파이어
토마스 앤드류 사토리어스
미카엘 윌리엄 모로
제임스 노리스 디펜더퍼
케네스 알란 닥서
미카엘 스콧 매킬베인
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6032—Way prediction in set-associative cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020177033433A 2015-05-20 2016-04-08 캐시 태그 압축을 위한 방법 및 장치 Active KR102138697B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/716,947 2015-05-20
US14/716,947 US9514061B1 (en) 2015-05-20 2015-05-20 Method and apparatus for cache tag compression
PCT/US2016/026664 WO2016186747A1 (en) 2015-05-20 2016-04-08 Method and apparatus for cache tag compression

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KR20180008507A KR20180008507A (ko) 2018-01-24
KR102138697B1 true KR102138697B1 (ko) 2020-07-28

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US (1) US9514061B1 (cg-RX-API-DMAC10.html)
EP (1) EP3298493B1 (cg-RX-API-DMAC10.html)
JP (1) JP6724043B2 (cg-RX-API-DMAC10.html)
KR (1) KR102138697B1 (cg-RX-API-DMAC10.html)
CN (1) CN107735773B (cg-RX-API-DMAC10.html)
AU (1) AU2016265131B2 (cg-RX-API-DMAC10.html)
ES (1) ES2787002T3 (cg-RX-API-DMAC10.html)
HU (1) HUE049200T2 (cg-RX-API-DMAC10.html)
TW (1) TWI698745B (cg-RX-API-DMAC10.html)
WO (1) WO2016186747A1 (cg-RX-API-DMAC10.html)

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WO2023219204A1 (ko) * 2022-05-11 2023-11-16 서울시립대학교 산학협력단 명령어를 처리하는 방법 및 이를 위한 프로세서 모듈
KR20250064407A (ko) 2023-11-02 2025-05-09 대한민국(방위사업청장) 안보심리지수 생성방법 및 그 시스템

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US9996471B2 (en) * 2016-06-28 2018-06-12 Arm Limited Cache with compressed data and tag
US10387305B2 (en) * 2016-12-23 2019-08-20 Intel Corporation Techniques for compression memory coloring
US10061698B2 (en) * 2017-01-31 2018-08-28 Qualcomm Incorporated Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur
US10254961B2 (en) 2017-02-21 2019-04-09 International Business Machines Corporation Dynamic load based memory tag management
US10229061B2 (en) 2017-07-14 2019-03-12 International Business Machines Corporation Method and arrangement for saving cache power
GB2566469B (en) * 2017-09-13 2021-03-24 Advanced Risc Mach Ltd Cache line statuses
US10831669B2 (en) 2018-12-03 2020-11-10 International Business Machines Corporation Systems, methods and computer program products using multi-tag storage for efficient data compression in caches
US11720495B2 (en) * 2019-05-24 2023-08-08 Texas Instmments Incorporated Multi-level cache security
US10983915B2 (en) * 2019-08-19 2021-04-20 Advanced Micro Devices, Inc. Flexible dictionary sharing for compressed caches
US11436144B2 (en) * 2020-04-10 2022-09-06 Micron Technology, Inc. Cache memory addressing
CN114201265B (zh) * 2021-12-10 2025-09-02 北京奕斯伟计算技术股份有限公司 支持物理地址大于虚拟地址的虚拟内存管理方法及装置
CN121213333B (zh) * 2025-09-17 2026-06-05 摩尔线程智能科技(北京)股份有限公司 一种数据获取方法及装置、电子设备和存储介质

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US20130007358A1 (en) 2011-06-29 2013-01-03 New Jersey Institute Of Technology Replicating tag entries for reliability enhancement in cache tag arrays

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US20130007358A1 (en) 2011-06-29 2013-01-03 New Jersey Institute Of Technology Replicating tag entries for reliability enhancement in cache tag arrays

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023219204A1 (ko) * 2022-05-11 2023-11-16 서울시립대학교 산학협력단 명령어를 처리하는 방법 및 이를 위한 프로세서 모듈
KR20250064407A (ko) 2023-11-02 2025-05-09 대한민국(방위사업청장) 안보심리지수 생성방법 및 그 시스템

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JP2018519570A (ja) 2018-07-19
ES2787002T3 (es) 2020-10-14
CN107735773B (zh) 2021-02-05
HUE049200T2 (hu) 2020-09-28
EP3298493B1 (en) 2020-02-12
CN107735773A (zh) 2018-02-23
US20160342530A1 (en) 2016-11-24
AU2016265131B2 (en) 2020-09-10
KR20180008507A (ko) 2018-01-24
TW201706853A (zh) 2017-02-16
EP3298493A1 (en) 2018-03-28
WO2016186747A1 (en) 2016-11-24
TWI698745B (zh) 2020-07-11
BR112017024623A2 (pt) 2018-07-31
US9514061B1 (en) 2016-12-06
AU2016265131A1 (en) 2017-11-02
JP6724043B2 (ja) 2020-07-15

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