KR102135958B1 - Method and apparatus for storing image data using a multiple memory controller - Google Patents

Abstract

Divides an image into a predetermined image processing unit, groups at least one divided image processing unit into at least one group, maps at least one group with at least one memory controller, and processes at least one segmented image. Disclosed is a method for storing image data, comprising storing the units in a memory controlled by a memory controller mapped to each group.

Description

Method and apparatus for storing image data using multiple memory controllers {Method and apparatus for storing image data using a multiple memory controller}

The present invention relates to a method and apparatus for storing image data using a plurality of memory controllers.

In order for the image processing apparatus to process image data, a reference image from which a previous image was restored may be used. That is, when the image processing apparatus encodes or decodes image data, a reconstructed image of a previous image may be used as a reference image. In this case, the image processing apparatus may store a reconstructed image of a previous image that can be used as a reference image in memory or read stored image data in order to use the reference image.

Therefore, in order for the display device to decode and display an ultra-high-definition image in real time, it is necessary to rapidly record or acquire large-capacity image data that can be used as a reference image.

The present invention relates to a method and apparatus for storing or acquiring image data using a plurality of memory controllers.

An image data storage method according to an embodiment of the present invention includes: dividing an image into predetermined image processing units; Grouping the divided at least one image processing unit into at least one group; Mapping the at least one group to at least one memory controller, respectively; And storing the divided at least one image processing unit in a memory controlled by the mapped memory controller for each group.

The dividing step includes dividing each color component of the image into a predetermined image processing unit.

The storing may include storing image data of an area of a predetermined size adjacent to each image processing unit in a memory controlled by a memory controller mapped to each image processing unit.

The image data storage method according to an embodiment of the present invention further includes mapping at least one decoder to the at least one memory controller, and data stored in the memory controlled by the at least one memory controller is It can be accessed by the mapped decoder.

A method for storing image data according to an embodiment of the present invention includes: a first decoder accessing data stored in a memory controlled by a memory controller mapped with a second decoder; The data may be further recorded in a cache of at least one of the first decoder and the second decoder.

The image data storage method according to an embodiment of the present invention includes: determining whether data to be acquired by the first decoder is data stored in a memory controlled by a memory controller mapped with the second decoder; Accessing a cache that can be accessed by the first decoder and the second decoder according to the determination result; If the result of the access, the data can be obtained from the cache, characterized in that it further comprises the step of obtaining the data from the cache.

A method for storing image data according to an embodiment of the present invention includes: a first decoder accessing data stored in a memory controlled by a memory controller mapped with a second decoder; The data may be further recorded in a cache of at least one of the first decoder and the second decoder.

The image data storage method according to an embodiment of the present invention includes: determining whether data to be acquired by the first decoder is data stored in a memory controlled by a memory controller mapped with the second decoder; Accessing a cache that can be accessed by the first decoder and the second decoder according to the determination result; If the result of the access, the data can be obtained from the cache, characterized in that it further comprises the step of obtaining the data from the cache.

In the image data storage method according to an embodiment of the present invention, when the data cannot be obtained from the cache as a result of the access, the memory controlled by the memory controller mapped with the second decoder is accessed to access the data Obtaining a; The data is characterized in that it further comprises the step of writing to the cache.

In one embodiment of the present invention, image data may be stored in a memory using a plurality of memory controllers.

In one embodiment of the present invention, image data may be acquired more quickly using a plurality of memory controllers.

1 is a block diagram illustrating an internal structure of an image processing apparatus including a plurality of memory controllers in an embodiment of the present invention.
2 is an exemplary diagram illustrating an example of grouping divided image data into one or more groups in one embodiment of the present invention.
3A is a flowchart illustrating a method of storing image data using a plurality of memory controllers in an embodiment of the present invention.
3B is a flowchart illustrating a method of accessing image data stored in a memory using a plurality of memory controllers in an embodiment of the present invention.
4 is an exemplary diagram illustrating an example of grouping divided image data into one or more groups for each color component in an embodiment of the present invention.
5 is an exemplary diagram illustrating an example of grouping divided image data into one or more groups in another embodiment of the present invention.
6 is an exemplary view showing an example of storing image data using a plurality of memory controllers in another embodiment of the present invention.
7 is a flowchart illustrating a method of storing image data using a plurality of memory controllers in another embodiment of the present invention.
8 is a flowchart illustrating a method of accessing image data using a plurality of memory controllers in another embodiment of the present invention.
9 is a block diagram illustrating an internal structure of an image processing apparatus that processes stored image data using a plurality of memory controllers in an embodiment of the present invention.
10 is a flowchart illustrating a method of processing stored image data using a plurality of memory controllers in an embodiment of the present invention.
11 is a block diagram illustrating an internal structure of an image processing apparatus that processes stored image data using a plurality of memory controllers in another embodiment of the present invention.
12 is a flowchart illustrating a method of processing stored image data using a plurality of memory controllers in another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, in the following description and attached drawings, detailed descriptions of well-known functions or configurations that may obscure the subject matter of the present invention are omitted. In addition, it should be noted that the same components throughout the drawings are denoted by the same reference numerals as much as possible.

The terms or words used in the present specification and claims described below should not be interpreted as being limited to ordinary or lexical meanings, and the inventor appropriately defines terms as terms for describing his or her invention in the best way. Based on the principle that it can be done, it should be interpreted as a meaning and a concept consistent with the technical idea of the present invention. Therefore, the embodiments shown in the embodiments and the drawings described in this specification are only the most preferred embodiments of the present invention, and do not represent all of the technical spirit of the present invention, and can replace them at the time of this application. It should be understood that there may be equivalents and variations.

The principles of the present invention can be applied to any intra-frame and inter-frame based encoding standard. The term'image' used throughout this specification describes not only the term'image' itself, but also various types of video image information that can be known in the relevant field as'frame','field', and'slice'. Can be used as a generic term.

The reference image may be an image that can be used to inter-predict blocks in the current image.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating an internal structure of an image processing apparatus including a plurality of memory controllers in an embodiment of the present invention.

Referring to FIG. 1, the image processing apparatus 100 may include a control unit 110 and a plurality of memory controllers 120, 130, 140, 150 and memories 121, 131, 141, 151. However, not all of the illustrated components are essential components. The image processing apparatus 100 may be implemented by more components than the illustrated components, or the image processing apparatus 100 may be implemented by fewer components.

Hereinafter, the components will be described in turn.

The controller 110 may control the overall operation of the image processing apparatus 100. For example, the controller 110 may control the restored image to be stored in the memory 121, 131, 141, 151 when encoding the image data. Specifically, the controller 110 may perform control and processing related to a method of storing image data using a plurality of memory controllers 120, 130, 140, and 150. That is, the control unit 110 may control the plurality of memory controllers 120, 130, 140, and 150 and the memories 121, 131, 141, and 151 as a whole.

In one embodiment of the present invention, the control unit 110 may control the memory controllers 120, 130, 140, 150 so that the restored image is stored in the memory 121, 131, 141, 151.

The plurality of memory controllers 120, 130, 140, and 150 may store or acquire data in the memory 121, 131, 141, 151 and transfer it to another device. That is, the memory controllers 120, 130, 140, and 150 may overall control the memories 121, 131, 141, and 151.

In an embodiment of the present invention, the image processing apparatus 100 may divide an image into predetermined image processing units and group the divided image processing units into at least one group. In addition, the image processing apparatus 100 may map at least one group to at least one memory controller, and store the divided image processing units in a memory controlled by a memory controller mapped to each group.

Therefore, the image processing apparatus 100 according to an embodiment of the present invention uses a plurality of memory controllers when processing ultra-high-definition image data, so that the memory bandwidth becomes larger, and thus the ultra-high-definition image is processed at a higher speed. Can handle it.

The memory bandwidth refers to the size of data that can be transmitted to or received from memory for a predetermined period of time. Therefore, the larger the memory bandwidth, the larger the size of data that can be written to or read from the memory for a predetermined period of time.

A method of processing image data according to an embodiment of the present invention using a plurality of memory controllers will be described in more detail in FIGS. 2 to 4 below.

2 is an exemplary diagram illustrating an example of grouping divided image data into one or more groups in one embodiment of the present invention.

Referring to FIG. 2, the image 200 is divided into blocks of a predetermined size, and each block may belong to one of the first to fourth groups.

According to an embodiment of the present invention, the image 200 may be divided into predetermined image processing units so that a plurality of memory controllers can be used. In addition, each divided image processing unit may be grouped into one or more groups.

For example, a predetermined image processing unit may be a block of M by N units. Also, the image 200 may be divided into units in which images, such as slices and tiles, can be processed or various types of units.

The predetermined image processing units may be grouped into one or more groups according to certain rules. For example, it may be grouped into one or more groups according to the arrangement order of each image processing unit. Referring to FIG. 2, image processing units positioned in an odd-numbered column in an odd row may be set as a first group, and image processing units positioned in an even-numbered column in an odd row may be set as a second group. Also, the image processing units positioned in the even-numbered rows in the even-numbered rows may be set to the third group, and the image processing units positioned in the even-numbered rows in the even-numbered rows may be set to the fourth group.

In addition, the first to fourth groups may be mapped to the first to fourth memory controllers, respectively. Accordingly, the image processing units grouped into the first to fourth groups may be processed by the memory controller mapped to the group to which the image processing units belong. In other words, grouped image processing units may be recorded in a memory controlled by a memory controller mapped to each group. For example, when the first group is mapped to the first memory controller, image processing units belonging to the first group may be recorded in a memory controlled by the first memory controller. Also, image processing units belonging to the first group may be obtained from the memory by the first memory controller.

Also, each memory controller may be mapped to one or more groups. For example, when the first to eighth groups exist, the first and second groups may be mapped to the first memory controller. The first and second groups may be mapped to the first memory controller. The third and fourth groups may be mapped to the second memory controller. The fifth and sixth groups may be mapped to the third memory controller. The seventh and eighth groups may be mapped to the fourth memory controller.

In one embodiment of the present invention, a method of grouping predetermined image processing units may be grouped in various ways, not limited to the above-described method.

According to an embodiment of the present invention, each divided image processing unit may be processed by a different memory controller according to a group to which it belongs. Therefore, according to an embodiment of the present invention, when the image processing apparatus 100 processes a large image data, since a plurality of memory controllers can be used, the memory bandwidth is larger than when using a single memory controller, and thus, faster Can process images.

3A is a flowchart illustrating a method of storing image data using a plurality of memory controllers in an embodiment of the present invention.

Referring to FIG. 3A, in step S301, the image processing apparatus 100 may divide the image 200 into predetermined image processing units. In one embodiment of the present invention, the image 200 that can be processed in the image processing apparatus 100 may be divided into image processing units of the same size, but is not limited thereto, in various method or size image processing units. Can be divided.

In step S303, the image processing apparatus 100 may group each divided image processing unit into one or more groups. For example, each divided image processing unit may be grouped into first to fourth groups. The group of each image processing unit may be determined according to a certain rule, but is not limited thereto, and may be determined according to preset information or conditions.

In step S305, the image processing apparatus 100 may map each group grouped in step S303 with a memory controller.

In step S307, the image processing apparatus 100 may store the divided image processing units in a memory controlled by a memory controller mapped to a group to which each image processing unit belongs. That is, each of the divided image processing units may be processed by different memory controllers according to a group to which they belong. Accordingly, according to an embodiment of the present invention, when the image processing apparatus 100 processes large sized image data, a plurality of memory controllers may be used, so images may be processed faster than when using a single memory controller. .

3B is a flowchart illustrating a method of accessing image data stored in a memory using a plurality of memory controllers in an embodiment of the present invention.

Referring to FIG. 3B, in step S309, the image processing apparatus 100 may determine a group to which the image processing unit of the image to be accessed belongs. The group that may be determined in step S309 may be a group to which each image processing unit belongs according to the result grouped in step S303 in FIG. 3A. For example, each image processing unit may be determined as one of the first to fourth groups. The group of each image processing unit may be determined according to a certain rule, but is not limited thereto, and may be determined according to preset information or conditions.

In step S311, the image processing apparatus 100 may determine a memory controller mapped to the group determined in step S311. The memory controller that may be determined in step S311 may be a memory controller mapped to each group according to the result mapped in step S305 in FIG. 3A.

In step S313, the image processing apparatus 100 may access the image processing unit of the image by accessing the memory through the memory controller determined in step S311. That is, each image processing unit may be processed by a different memory controller according to a group to which it belongs.

4 is an exemplary diagram illustrating an example of grouping divided image data into one or more groups for each color component in an embodiment of the present invention.

Referring to FIG. 4, an image is divided into blocks of a predetermined size for each color component 410, 420, and 430, and each block may belong to one of the first to fourth groups.

For example, when the color components of the image are composed of Y, Cb, and Cr, the images 410, 420, and 430 for each Y component, Cr component, and Cb component may be divided into predetermined image processing units. Also, the divided image processing units may be grouped into one or more groups, and each group may be mapped to one or more memory controllers. Accordingly, the divided image processing units may be stored or accessed in memory by a memory controller mapped to each group.

In one embodiment of the present invention, each color component of an image that can be divided into one or more predetermined image processing units is not limited to YCbCr, but may also include color components separated by RGB or other methods.

5 is an exemplary diagram illustrating an example of grouping divided image data into one or more groups in another embodiment of the present invention.

Referring to FIG. 5, the image 500 may be divided into slice units, one of image processing units. When the image 500 is divided in slice units, a plurality of image regions may be divided in a horizontal direction. In addition, each divided slice unit of the image 500 may be grouped into first to fourth groups. When the first to fourth groups are mapped to the first to fourth memory controllers, each slice unit may be recorded or accessed in memory by the memory controller mapped to the group to which it belongs.

The image processing apparatus 100 may access reference image data stored in each memory to process the current image. In other words, the image processing apparatus 100 determines a group to which a predetermined region of the reference image for processing a predetermined region of the current image belongs, and a memory controller that controls the memory in the memory in which the predetermined region of the reference image is recorded Can be accessed through.

At this time, the image processing apparatus 100 may further require image data belonging to a region adjacent to a predetermined region of the reference image in order to process a predetermined region of the current image according to characteristics of the image data region to be processed. However, when a group to which a region adjacent to a predetermined region of a reference image belongs is different from a group to which a predetermined region belongs, access through a memory controller mapped to a group different from the group to which the predetermined region belongs. In this case, complexity of an image processing process or data congestion may increase.

Accordingly, according to an embodiment of the present invention, image data belonging to at least one adjacent region between image processing units belonging to each group in the reference image are respectively stored in a memory controlled by a memory controller mapped to each group. Can be.

Referring to FIG. 5, at least one adjacent region 510, 520, or 530 may be determined between image processing units belonging to each group. Adjacent regions 510, 520, and 530 that may be determined may exist between boundaries between image processing units belonging to different groups. In addition, image data belonging to the adjacent regions 510, 520, and 530 may be redundantly stored in a memory in which image processing units belonging to different groups are stored.

Hereinafter, the above-described embodiment in FIG. 5 will be described in more detail with reference to FIGS. 6 to 8.

6 is an exemplary view showing an example of storing image data using a plurality of memory controllers in another embodiment of the present invention.

Referring to FIG. 6, the image processing apparatus 600 may include a control unit 610 and first to fourth memory controllers 620, 630, 640, 650 and memories 621, 631, 641, 651. . The control unit 610 of FIG. 6 and the first to fourth memory controllers 620, 630, 640, and 650 and the memory 621, 631, 641, and 651 are the control unit 110 of FIG. 1 and the first to fourth memory It corresponds to the controllers 120, 130, 140, 150 and the memory 121, 131, 141, 151, and duplicate description will be omitted.

The memories 621, 631, 641, and 651 may be controlled by the connected first to fourth memory controllers 620, 630, 640, and 650, respectively.

The internal structure of the memories 621, 631, 641, and 651 shown in FIG. 6 shows regions of the image 600 that can be stored in each memory.

The image processing unit 622 belonging to the first group of the image 500 may be stored in the memory 621 that can be controlled by the first memory controller 620. In addition, the image data region 623 belonging to a partial region among the image data regions of the image processing unit belonging to the second group of the image 500 may be stored in the memory 621. That is, the image data region 623 belonging to the adjacent region 510 between the image processing unit belonging to the first group and the image processing unit belonging to the second group may be stored in the memory 621.

Accordingly, when the image processing apparatus 600 accesses the image processing unit belonging to the first group in the reference image through the first memory controller 620 for image processing, the image data belonging to another group is also the first memory controller ( 620). That is, the image processing apparatus 600 may access not only image processing units belonging to the first group but also image data of a predetermined region belonging to another group adjacent to the image processing units belonging to the first group through the first memory controller 620. Can.

Also, the image processing unit 633 belonging to the second group of the image 500 may be stored in the memory 631 that can be controlled by the second memory controller 630. In addition, the adjacent region 510 between the image processing unit belonging to the first group and the image processing unit belonging to the second group and the image data area 632 belonging to the first group may be stored in the memory 631. In addition, the adjacent region 520 between the image processing unit belonging to the second group and the image processing unit belonging to the third group and the image data area 634 belonging to the third group may be stored in the memory 631.

Also, the image processing unit 643 belonging to the third group of the image 500 may be stored in the memory 641 that can be controlled by the third memory controller 640. In addition, the adjacent region 520 between the image processing unit belonging to the second group and the image processing unit belonging to the third group and the image data area 642 belonging to the second group may be stored in the memory 641. In addition, the adjacent region 530 between the image processing unit belonging to the third group and the image processing unit belonging to the fourth group and the image data area 644 belonging to the fourth group may be stored in the memory 641.

Also, the image processing unit 653 belonging to the fourth group of the image 500 may be stored in the memory 651 that can be controlled by the fourth memory controller 650. In addition, the adjacent region 510 and the image data region 652 belonging to the third group between the image processing unit belonging to the third group and the image processing unit belonging to the fourth group may be stored in the memory 651.

Accordingly, when the image processing apparatus 600 accesses an image processing unit belonging to a predetermined group in a reference image through a memory controller mapped to the corresponding group, image data belonging to another group may be accessed through the same memory controller. That is, the image processing apparatus 600 may not only image processing units belonging to a predetermined group, but also image processing units belonging to a predetermined group and image data of a predetermined region belonging to another group adjacent to the image processing unit mapped to an image processing unit belonging to a predetermined group. Can be accessed through

Therefore, since the image processing apparatus 600 can access the image data of a predetermined range of adjacent regions belonging to a group different from the group to which the image processing unit currently being accessed belongs, the data congestion may be lowered.

7 is a flowchart illustrating a method of storing image data using a plurality of memory controllers in another embodiment of the present invention. Steps S701 to S707 of FIG. 7 correspond to steps S301 to S307 of FIG. 3, and redundant content will be omitted.

Referring to FIG. 7, in step S701, the image processing apparatus 600 may divide the image 500 into predetermined image processing units.

In step S703, the image processing apparatus 600 may group each divided image processing unit into one or more groups. For example, each divided image processing unit may be grouped into first to fourth groups.

In step S705, the image processing apparatus 600 may map each group grouped in step S703 with a memory controller.

In step S707, the image processing apparatus 600 may store the divided image processing unit in a memory controlled by a memory controller mapped to a group to which each image processing unit belongs. That is, each of the divided image processing units may be processed by different memory controllers according to a group to which they belong.

In the following description, a memory controlled by a memory controller mapped to a group to which each image processing unit belongs may be expressed as a group to which each image processing unit belongs or a memory mapped to each image processing unit for convenience of description.

In step S709, the image processing apparatus 600 may determine adjacent regions for each of the divided image processing units.

At this time, the adjacent region that can be determined may be determined as a range of image data regions belonging to a boundary region between each image processing unit and an image processing unit belonging to a different group. For example, when the corresponding image has a large movement in the image, the adjacent region may be determined to be a wider range. For example, if the corresponding image has a small movement in the image, the adjacent region may be determined to be a smaller range. The range of the adjacent region may be determined according to the image characteristics, but the range of the adjacent region for each of the divided image processing units of predetermined images may be determined according to a preset value, not according to the image characteristics.

In step S711, the image processing apparatus 600 may repeatedly store the image data belonging to the adjacent region determined in step S709 in a memory controlled by a memory controller mapped to a group to which each adjacent region belongs.

For example, image data belonging to the adjacent region determined in step S709 may belong to the first group or the second group. At this time, among the image data belonging to the adjacent region, the image data belonging to the first group may be redundantly stored in the memory mapped to the first group as well as the memory mapped to the first group. Similarly, the image data belonging to the second group among the image data belonging to the adjacent region may be stored in the memory mapped to the second group as well as the memory mapped to the first group.

8 is a flowchart illustrating a method of accessing image data using a plurality of memory controllers in another embodiment of the present invention. Steps S801 to S805 of FIG. 8 correspond to steps S309 to S313 of FIG. 3, and overlapping contents will be omitted.

Referring to FIG. 8, in step S801, the image processing apparatus 600 may determine a group to which the image processing unit of the image to be accessed belongs. The group that can be determined in step S801 may be a group to which each image processing unit belongs according to the result grouped in step S703 in FIG. 7.

In step S803, the image processing apparatus 600 may determine the memory controller mapped to the group determined in step S801. The memory controller that may be determined in step S801 may be a memory controller mapped to each group according to the result mapped in step S705 in FIG. 7.

In step S805, the image processing apparatus 600 may access the image processing unit of the image by accessing the memory through the memory controller determined in step S803.

In step S807, if the image processing apparatus 600 wants to acquire image data of an adjacent region of the image processing unit accessed in step S805, in step S809, whether the group to which the adjacent region belongs differs from the group to which the image processing unit belongs. I can judge.

As a result of the determination in step S809, if the group to which the adjacent region belongs is the same as the group to which the image processing unit belongs, the image processing apparatus 600 accesses the memory in which the image data of the adjacent region is stored through the memory controller determined in step S805 in step S811 can do.

However, as a result of determining in step S809, when the group to which the adjacent region belongs is different from the group to which the image processing unit belongs, the image processing apparatus 600 may determine the group to which the adjacent region belongs in step S815. The group that may be determined in step S815 may be a group to which an image processing unit including an adjacent region belongs according to the result grouped in step S703 in FIG. 7.

In step S817, the image processing apparatus 600 may determine the memory controller mapped to the group determined in step S815. The memory controller that may be determined in step S815 may be a memory controller mapped to each group according to the result mapped in step S705 in FIG. 7.

In step S819, the image processing apparatus 600 may access the image data in the adjacent area by accessing the memory through the memory controller determined in step S817.

Accordingly, according to an embodiment of the present invention, the image processing apparatus 600 may store some image data belonging to a predetermined image processing unit and an adjacent region in the same memory together with a predetermined image processing unit. At this time, some of the image data belonging to the adjacent region belong to a group different from a predetermined image processing unit and may be repeatedly stored in a memory mapped to another group.

Therefore, the image processing apparatus 600 may acquire some image data belonging to the image processing unit being processed and the adjacent region from the memory mapped to the image processing unit being processed, so data congestion may be reduced because it does not need to access another memory. have.

9 is a block diagram illustrating an internal structure of an image processing apparatus for processing stored image data using a plurality of memory controllers in an embodiment of the present invention.

Referring to FIG. 9, the image processing apparatus 900 includes a control unit 910, first to fourth memory controllers 920, 930, 940, and 950, memories 921, 931, 941, and 951, and first to fourth It may include four decoders (960, 970, 980, 990) and first to fourth caches (961, 971, 981, 991). The controller 110 of FIG. 1, the first to fourth memory controllers 120, 130, 140, 150 and the memories 121, 131, 141, 151, and the first to fourth memory controllers 620 of FIG. 6 630, 640, 650) and memory (621, 631, 641, 651) is the control unit 910, the first to fourth memory controllers 920, 930, 940, 950 of Figure 9 and the memory (921, 931, 941) , 951), and redundant descriptions will be omitted.

The controller 910 may control the overall operation of the image processing apparatus 900. For example, the control unit 910 may control the restored image to be stored in the memories 921, 931, 941, and 951 when encoding the image data. In addition, when decoding the image data, the control unit 910 may control the restored image to be obtained from the memories 921, 931, 941, and 951.

The plurality of memory controllers 920, 930, 940, and 950 may store or acquire data in the memories 921, 931, 941, and 951 and transfer them to other devices. That is, the memory controllers 920, 930, 940, and 950 may control the memories 921, 931, 941, and 951 as a whole.

The memories 921, 931, 941, and 951 may store data under the control of the memory controllers 920, 930, 940, and 950.

The first to fourth decoders 960, 970, 980, and 990 acquire and acquire reference images stored in the memories 921, 931, 941, and 951 through the memory controllers 920, 930, 940, and 950. The current image may be decoded using the reference image.

In the first to fourth decoders 960, 970, 980, and 990 according to an embodiment of the present invention, areas of a current image to be decoded may be mapped, respectively. That is, the first to fourth decoders 960, 970, 980, and 990 may simultaneously and simultaneously decode regions of the mapped current image.

At this time, regions of the current image that can be mapped to the first to fourth decoders 960, 970, 980, and 990 may be determined according to each group to which the divided image processing unit of the reference image belongs. That is, the first to fourth decoders 960, 970, 980, 990 and the area of the current image may be determined according to each group belonging to a region of the reference image corresponding to the region of the current image.

For example, when the group to which the region of the reference image corresponding to the region of the current image belongs is the first group, the region of the current image may be decoded by the first decoder 960.

When performing motion prediction of an image, since a time interval between the reference image and the current image is often close to zero, a large difference between the current image and the reference image may hardly exist. Accordingly, the region of the reference image that can be used when the current image is decoded may correspond to an area almost corresponding to the area of the current image, that is, an area of the same location.

However, some areas of the reference picture that can be used when the current picture is decoded may be included in an area that does not correspond to the area of the current picture.

Also, the first to fourth decoders 960, 970, 980, and 990 may include the first to fourth memory controllers 920, according to each group to which the divided image processing unit of the reference image corresponding to the determined region of the current image belongs. 930, 940, and 950 may be mapped. The first to fourth decoders 960, 970, 980, and 990 may acquire reference images stored in the memories 921, 931, 941, and 951 through the mapped memory controllers 920, 930, 940, and 950. have.

On the other hand, when some areas of the reference picture that can be used when the current picture is decoded are included in an area that does not correspond to the area of the current picture, the first to fourth decoders 960, 970, 980, and 990 are mapped respectively. A reference image can be obtained from a memory other than the memory that has been created.

The first to fourth caches 961, 971, 981, and 991 are obtained through the memory controllers 920, 930, 940, and 950 by the first to fourth decoders 960, 970, 980, and 990, respectively. One reference image can be temporarily stored. The first to fourth decoders 960, 970, 980, and 990 may decode the current image using reference image data temporarily stored in the first to fourth caches 961, 971, 981, and 991.

In the image processing apparatus 900 according to an embodiment of the present invention, the first to fourth decoders 960, 970, 980, and 990 acquire reference images stored in the mapped memories 921, 931, 941, and 951, respectively. Thus, it can be stored in the first cache to the fourth cache (961, 971, 981, 991).

Meanwhile, as described above, when the first to fourth decoders 960, 970, 980, and 990 acquire reference images from memory other than the mapped memory, the obtained reference images are first to fourth cache. (961, 971, 981, 991).

In this case, according to an embodiment of the present invention, the first to fourth caches 961, 971, 981, and 991 connected to the first to fourth decoders 960, 970, 980, and 990, respectively, as well as the obtained reference The reference image obtained from the memory may be duplicated in the cache of the decoder in which the region of the current image corresponding to the region of the image is decoded. For example, when the first decoder 960 acquires a reference image from a memory 931 other than the memory 921 mapped to the first decoder 960, the obtained reference image is the first cache 961 only. In addition, the second cache 971 may be stored in duplicate.

This is because the region of the reference image obtained by the first decoder 960 is likely to be used by the second decoder 970, so that the second cache 971 of the reference image obtained by the first decoder 960 Areas can be stored. Therefore, the second decoder 970 may acquire the reference image from the second cache 971 without accessing the memory 931 through the second memory controller 930 to decode the current image.

In other words, when the reference image is obtained from a memory other than the memory mapped with the decoder, it is highly likely that the reference image obtained from the memory and the decoder mapped with the reference image is used. This is because there is a high possibility that the region of the reference image corresponding to the region of the current image is referred to as described above. Therefore, the obtained reference image may be stored in the cache of the decoder mapped to the memory from which the reference image was acquired.

10 is a flowchart illustrating a method of processing stored image data using a plurality of memory controllers in an embodiment of the present invention.

Referring to FIG. 10, in step S1001, the image processing apparatus 900 may map one or more decoders with one or more memory controllers, respectively. At this time, as described above in the description of FIG. 9, each decoder may be mapped to a memory controller according to each group to which a divided image processing unit of a reference image corresponding to a region of a current image to be decoded belongs.

For example, when the group to which the region of the reference image corresponding to the region of the current image belongs is the first group, the region of the current image is to be decoded by the first decoder 960 mapped with the first memory controller 920. Can. This is because the area of the reference picture that can be used when the current picture is decoded may correspond to an area that almost corresponds to the area of the current picture.

In step S1003, the image processing apparatus 900 may access the data stored in the memory controlled by the second memory controller by the first decoder. That is, when some areas of the reference picture that can be used when the current picture is decoded are included in an area that does not correspond to the area of the current picture, each decoder can obtain a reference picture from memory other than the mapped memory. .

In step S1005, the image processing apparatus 900 may record the data accessed in step S1003 in a cache of at least one of the first decoder and the second decoder. That is, the cache of the second decoder in which the region of the current image corresponding to the region of the obtained reference image is decoded may be stored as well as the caches respectively connected to the first decoder. For example, when the first decoder acquires a reference image from a memory other than the memory mapped to the first decoder, the obtained reference image may be stored in the second cache as well as the first cache.

11 is a block diagram illustrating an internal structure of an image processing apparatus for processing stored image data using a plurality of memory controllers in another embodiment of the present invention.

Referring to FIG. 11, the image processing device 1100 includes a control unit 1110, first to fourth memory controllers 1120, 1130, 1140, 1150, memory 1121, 1131, 1141, 1151, and first to first It may include 4 decoders (1160, 1170, 1180, 1190) and first to sixth caches (1161, 1162, 1171, 1181, 1182, 1191).

The controller 110 of FIG. 1, the first to fourth memory controllers 120, 130, 140, 150 and the memory 121, 131, 141, 151, and the first to fourth memory controllers 620 of FIG. 6, 630, 640, 650) and memory (621, 631, 641, 651), the control unit 910 of FIG. 9, the first to fourth memory controllers (920, 930, 940, 950) and memory (921, 931, 941, 951), the control unit 1110 of FIG. 11, the first to fourth memory controllers 1120, 1130, 1140, 1150, correspond to the memory 1121, 1131, 1141, 1151, overlapping description is omitted I will do it.

In addition, the first to fourth decoders 960, 970, 980, and 990 of FIG. 9 and the first cache to fourth caches 961, 971, 981, and 991 are the first to fourth decoders 1160 of FIG. 1170, 1180, 1190) and the first cache to the fourth cache (1161, 1171, 1181, 1191), and overlapping description will be omitted.

The controller 1110 may control the overall operation of the image processing apparatus 1100. For example, the controller 1110 may control the restored image to be stored in the memories 1121, 1131, 1141, and 1151 when encoding image data. In addition, the controller 1110 may control the restored image to be obtained from the memories 1121, 1131, 1141, and 1151 when decoding the image data.

The plurality of memory controllers 1120, 1130, 1140, and 1150 may store or acquire data in the memories 1121, 1131, 1141, and 1151 and transfer them to other devices. That is, the memory controllers 1120, 1130, 1140, and 1150 may control the memories 1121, 1131, 1141, and 1151 as a whole.

The memories 1121, 1131, 1141, and 1151 may store data under the control of the memory controllers 1120, 1130, 1140, and 1150.

The first to fourth decoders 1160, 1170, 1180, and 1190 acquire reference images stored in the memories 1121, 1131, 1141, and 1151 through memory controllers 1120, 1130, 1140, and 1150, and obtain The current image may be decoded using the reference image. The first to fourth decoders 1160, 1170, 1180, and 1190 may simultaneously decode regions of the mapped current image in parallel.

The first to fourth caches 1161, 1171, 1181, and 1191 are obtained through the memory controllers 1120, 1130, 1140, and 1150 by the first to fourth decoders 1160, 1170, 1180, and 1190, respectively. One reference image can be temporarily stored. The first to fourth decoders 1160, 1170, 1180, and 1190 may decode the current image using reference image data temporarily stored in the first to fourth caches 1161, 1171, 1181, and 1191.

Unlike the image processing apparatus 900 of FIG. 9, the image processing apparatus 1100 of FIG. 11 may further include a fifth cache 1162 and a sixth cache 1182.

The fifth cache 1162 and the sixth cache 1182 may be connected to two or more decoders, and may temporarily store some data among reference images obtained through a memory controller mapped to each connected decoder.

For example, when the fifth cache 1162 is connected to the first decoder 1160 and the second decoder 1170, the fifth cache 1162 is mapped to the first decoder 1160 and the second decoder 1170 Some of the reference images acquired through the first memory controller 1120 or the second memory controller 1130 may be temporarily stored.

In addition, when the sixth cache 1182 is connected to the third decoder 1180 and the fourth decoder 1190, the sixth cache 1182 is mapped to the third decoder 1180 and the fourth decoder 1190. Some of the reference images acquired through the 3 memory controller 1140 or the 4th memory controller 1150 may be temporarily stored.

Some of the reference images that may be temporarily stored in the fifth cache 1162 or the sixth cache 1182 may include regions that do not correspond to regions of the current image to be decoded. For example, some of the reference images that may be temporarily stored in the fifth cache 1162 include data obtained through the second memory controller 1130 among reference image data obtained by the first decoder 1160. can do. In addition, some of the reference images that may be temporarily stored in the fifth cache 1162 may include data obtained through the first memory controller 1120 among reference image data obtained by the second decoder 1170. have.

According to an embodiment of the present invention, the image processing apparatus 1100 may further include a cache connected to two or more decoders in addition to a cache connected to each decoder. Each decoder can temporarily store data acquired through a memory controller that is not mapped to itself in its cache. Accordingly, other decoders connected to the cache may acquire reference image data to be acquired by accessing the cache without having to acquire reference image data through a memory controller mapped to the cache.

That is, a cache connected to two or more decoders may temporarily store a region of a reference image that can be commonly used to decode the current image in each connected decoder. In this case, a region of the reference image that can be commonly used may include, for example, at least one adjacent region between image processing units belonging to each group.

Hereinafter, a method of processing stored image data using a plurality of memory controllers by the image processing apparatus 1100 described above with reference to FIG. 12 will be described in more detail.

12 is a flowchart illustrating a method of processing stored image data using a plurality of memory controllers in another embodiment of the present invention.

Referring to FIG. 12, in step S1201, the image processing apparatus 1100 may map one or more decoders with one or more memory controllers, respectively. At this time, as described above in the description of FIG. 9, each decoder may be mapped to a memory controller according to each group to which a divided image processing unit of a reference image corresponding to a region of a current image to be decoded belongs.

For example, when the group to which the region of the reference image corresponding to the region of the current image belongs is the first group, the region of the current image is decoded by the first decoder 1160 mapped with the first memory controller 1120. Can be. This is because the area of the reference picture that can be used when the current picture is decoded may correspond to an area that almost corresponds to the area of the current picture.

In step S1203, the first decoder included in the image processing apparatus 1100 may determine whether data desired by the first decoder is stored in a memory controlled by the second memory controller. That is, it is possible to determine whether data to be acquired by the decoder is stored in a memory controlled by a memory controller that is not mapped to itself. The first decoder and the second memory controller may refer to the first decoder 1160 and the second memory controller 1130 of the image processing apparatus 1100, but are not limited thereto. Each can mean.

In step S1203, when it is determined that the data to be acquired by the first decoder is stored in a memory controlled by the first memory controller, that is, a memory mapped to the first decoder, step S1205 may be performed. . In operation S1205, the first decoder may obtain data by accessing a memory or a first cache mapped with the first decoder.

In step S1203, when it is determined that the data to be acquired by the first decoder is stored in a memory controlled by the second memory controller, that is, a memory not mapped to the first decoder, step S1207 may be performed. have.

In step S1207, the first decoder may access the first decoder and a fifth cache connected to one or more decoders other than the first decoder. In this case, the fifth cache may be the fifth cache 1162 of the image processing apparatus 1100, but the image processing apparatus 1100 illustrated in FIG. 11 is only an example, and may mean a cache connected to two or more decoders. have.

In step S1209, the first decoder may determine whether there is data to be acquired by the first decoder in the fifth cache. That is, the first decoder may first determine whether data exists in a cache connected to the first decoder instead of accessing the memory through the second memory controller.

In step S1213, when the data to be acquired by the first decoder exists in the fifth cache, the first decoder may acquire the corresponding data from the fifth cache.

However, in step S1211, when the data to be acquired by the first decoder does not exist in the fifth cache, the first decoder may access the memory through the second memory controller to acquire the data.

Accordingly, according to an embodiment of the present invention, each decoder may temporarily store data obtained through a memory controller that is not mapped to itself in a corresponding cache. Therefore, other decoders connected to the cache can acquire reference image data to be acquired by accessing the cache without having to acquire reference image data through a memory controller mapped to the cache.

The present invention can be embodied as computer readable codes on a computer readable recording medium (including all devices having information processing functions). The computer-readable recording medium includes all kinds of recording devices in which data readable by a computer system is stored. Examples of computer-readable recording devices include ROM, RAM, CD-ROM, magnetic tape, floppy disks, and optical data storage devices.

Although the above description has been described with a focus on the novel features of the present invention applied to various embodiments, a person skilled in the art without departing from the scope of the present invention, the apparatus and method described above It will be understood that various deletions, substitutions, and modifications are possible in the form and details of the. Accordingly, the scope of the present invention is defined by the appended claims rather than in the above description. All modifications within the equivalent scope of the claims are covered by the scope of the present invention.

Claims (15)

Dividing the image into a plurality of image processing units;
Grouping the divided image processing units into a plurality of groups;
Mapping the plurality of groups to a plurality of memory controllers, respectively; And
And storing the image processing unit in different memories controlled by the mapped memory controller,
In the storing, the image processing unit included in the second group adjacent to at least one image processing unit included in the first group among the plurality of groups is identified, and the image processing unit of the identified second group is stored. And repeatedly storing in a memory corresponding to the second group and a memory corresponding to the first group. The method of claim 1, wherein the dividing step
And dividing each color component of the image into a predetermined image processing unit. delete According to claim 1,
And mapping at least one decoder to the at least one memory controller, respectively.
A method of storing image data in which data stored in a memory controlled by the at least one memory controller can be accessed by the mapped decoder. According to claim 4,
Accessing data stored in a memory controlled by a memory controller mapped to the second decoder by the first decoder;
And storing the data in a cache of at least one of the first decoder and the second decoder. According to claim 4,
Determining whether data to be acquired by the first decoder is data stored in a memory controlled by a memory controller mapped to the second decoder;
Accessing a cache that can be accessed by the first decoder and the second decoder according to the determination result;
And if the data can be obtained from the cache as a result of the access, obtaining the data from the cache. The method of claim 6,
As a result of the access, when the data cannot be obtained from the cache, accessing a memory controlled by a memory controller mapped with the second decoder to obtain the data;
And storing the data in the cache. A control unit for dividing an image into a plurality of image processing units, grouping the divided image processing units into a plurality of groups, and mapping the plurality of groups with a plurality of memory controllers, respectively;
A plurality of memories controlled by the plurality of memory controllers; And
And a plurality of memory controllers that store the image processing units in different memories controlled by the mapped memory controller,
The controller identifies an image processing unit included in a second group adjacent to at least one image processing unit included in a first group among the plurality of groups,
The plurality of memory controllers, the image processing apparatus for repeatedly storing the identified second group of image processing units in the memory corresponding to the second group and the memory corresponding to the first group. The method of claim 8, wherein the control unit
An image processing apparatus that divides each color component of the image into predetermined image processing units. delete The method of claim 8, wherein the image processing device
Further comprising at least one decoder,
The control unit
Mapping at least one decoder to each of the at least one memory controller,
An image processing apparatus in which data stored in a memory controlled by the at least one memory controller can be accessed by the mapped decoder. The method of claim 11,
The first decoder accesses data stored in memory controlled by a memory controller mapped to the second decoder,
The data is recorded in at least one cache of the first decoder or the second decoder. The method of claim 11,
The first decoder determines whether data to be acquired by the first decoder is data stored in a memory controlled by a memory controller mapped to the second decoder, and according to the determination result, the first decoder and the second decoder An image processing apparatus for acquiring the data from the cache when accessing the cache that can be accessed by and accessing the result, the data can be obtained from the cache. The method of claim 13,
The first decoder, if the data cannot be obtained from the cache as a result of the access, accesses the memory controlled by the memory controller mapped with the second decoder to obtain the data,
The data is recorded in the cache image processing apparatus. The computer-readable recording medium according to any one of claims 1 to 2 or 4 to 7, wherein a program for implementing the image data storage method is recorded.

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