KR102134605B1 - Antenna effect discharge circuit and manufacturing method - Google Patents

Abstract

An antenna effect discharge circuit is described for a substrate with patterned conductors that can be exposed to environments that induce charge during the manufacturing process. The antenna effect discharge circuit has a terminal connected to a node protected from charge accumulation on the device, a gate such as a gate of a field effect transistor in the circuit, and a terminal through which accumulated charge can be discharged to the substrate. A capacitor connects the gate in the antenna effect discharge circuit to the substrate. The voltage supply circuit is configured to provide a voltage that sufficiently biases the antenna effect discharge circuit in the off state during operation of the device. A patterned conductor in the top layer, preferably the top layer of the device, connects the gate in the antenna effect discharge circuit to the voltage supply circuit.

Description

ANTENNA EFFECT DISCHARGE CIRCUIT AND MANUFACTURING METHOD

The present invention relates to integrated circuit structures that handle charge accumulation during manufacturing.

In the manufacture of integrated circuits, some processes utilize activated ions. For example, backend processes, including metal etching, photoresist stripping, and deposition of an interlayer insulator, involve plasma that induces charge on structures within the die being processed. The charge of these structures during manufacture can be referred to as the antenna effect.

Antenna effect induced charges can damage structures in the device, including structures important to the performance of the device. For example, in memory devices, word lines or other relatively large conductive structures may suffer from significant charge accumulation due to the antenna effect. Accumulation of charges on the word lines may expose tunnel insulation layers, gate insulation layers, and interlayer polysilicon insulation layers used in flash memory devices to cause damage due to accumulated charges. In addition, charge storage structures utilized within dielectric charge storage cells can be particularly sensitive to this kind of damage.

One characteristic of the plasma induced charge can be positive or negative lice, and other types of damage can occur based on the type of this induced charge.

One treatment method to prevent or reduce the antenna effect is described in Chou et al., U.S. Pat. have. See also U.S. Patent No. 7,317,633 by Lusky et al. (name of invention: "PROTECTION OF NROM DEVICES FROM CHARGE DAMAGE") .

It has been reported that the plasma charge effect plays a significant role in SONOS charge-trapping devices. In most flash memory products, PN diode protection or poly fuse protection is applied. However, both methods have limitations. In order to protect the PN diode, the word line WL driving voltage is limited to only the reverse direction of the diode and must be lower than the breakdown voltage. Moreover, the PN diode only provides protection after the breakdown voltage, thus it does not protect the intermediate range voltages. In order to protect the poly fuse, it is necessary to blow the fuse before measurement. The fuse protection is suitable only for small test devices, but not for product design. Also, if the burst bias is too large, it also disturbs the device.

Electrostatic discharge (ESD) circuits have been deployed in probing pads in integrated circuits to prevent expanded external electrical pulses that damage the devices. However, ESD circuits are often activated at relatively high voltages and may not provide intermediate voltage protection.

Accordingly, it is desirable to provide a protection circuit for use in the manufacture of integrated circuits that protect against charge damage. In addition, the protective circuit should not affect the operation of the device after manufacture.

An antenna effect discharge circuit is described for a device having a plurality of layers of patterned conductors, such as patterned polysilicon layers and metal layers, which induce high energy plasma or other charges during the manufacturing process. Exposure to the environment. The antenna effect discharge circuit has a terminal connected to a node protected from charge accumulation on the device and a gate such as a gate of the field effect transistor in the circuit. A capacitor connects the gate in the antenna effect discharge circuit to the substrate. The voltage supply circuit is configured to provide a voltage that sufficiently biases the antenna effect discharge circuit in the off state during operation of the device. A patterned conductor in the top layer and preferably in the top layer of the device connects the gate in the antenna effect discharge circuit to the voltage supply circuit.

The antenna effect discharge circuit may include a field effect transistor including a channel and a source and a drain in the channel well region. The channel well region is connected to the gate via a patterned conductor in the upper layer or directly to the voltage supply circuit. In embodiments configured to discharge both positive and negative voltages on the protected node, the antenna effect discharge circuit is an n-channel field effect transistor (eg, as described in more detail below). , NMOS) and p-channel field effect transistors (eg, PMOS).

Utilizing a capacitor at the gate can prevent the voltage on the gate from following the voltage in the channel well region while exposed to the antenna effect charge. The antenna effect discharge circuit remains unconnected to the gate and the channel well until a layer on top of the plurality of patterned conductor layers is implemented.

Embodiments are described wherein the antenna effect discharge circuit is configured to be closed during operation of the device and includes a switch having first and second terminals. The first terminal is connected to the gate in the antenna effect discharge circuit by a first conductor, and the second terminal is connected to the voltage supply circuit by a second conductor. One or both of the first and second conductors include a patterned conductor in the top layer used to connect the gate to the voltage supply circuit. In embodiments with the switch, the antenna effect discharge circuit remains effective during the entire fabrication until the voltage supply circuit is enabled during operation of the device.

A method of manufacturing an integrated circuit device is described and includes forming an integrated circuit portion having a node protected from an antenna effect charge on a substrate. The method includes forming an antenna effect discharge circuit having a terminal and a gate connected to the node on the substrate. Further, the method includes forming a capacitor connecting the gate to the substrate. A voltage supply circuit is provided on the substrate to bias the gate during operation to turn off the antenna effect discharge circuit. As described herein, the method includes connecting the gate to a voltage supply circuit using a top or top patterned conductor layer on the device. In some embodiments, the method comprises providing a switch on the substrate between the gate and the voltage supply circuit, and the switch is closed during operation such that the gate is connected to the voltage supply circuit through the switch. It includes the steps to be configured.

Other aspects and advantages of the present technology will be understood through review of the following drawings, detailed description of the invention, and claims.

According to embodiments of the present invention, a protection circuit is provided for use in the manufacture of integrated circuits that are protected against charge damage. The protection circuit does not affect the operation of the device after manufacture.

1 is a schematic diagram of a conventional antenna effect discharge circuit based on dynamic threshold voltage MOSFETs.
2 is a perspective view of one exemplary prior art integrated circuit including multiple patterned conductor layers that may be protected using antenna effect discharge circuits as described herein.
3 is a schematic diagram of an antenna effect discharge circuit comprising a capacitor connected to the gate of a field effect transistor.
4 illustrates the configuration of a device substrate for an antenna effect discharge circuit comprising high voltage n-channel and p-channel field effect transistors as described herein.
5 is a schematic diagram of an antenna effect discharge circuit prior to the formation of the topmost patterned conductor layer, illustrating the discharge of negative voltage enhancement on the protected node.
6 is a schematic cross-sectional view of an antenna effect discharge circuit prior to formation of the topmost patterned conductor layer, illustrating the discharge of positive voltage buildup on the protected node.
7 is a schematic diagram of an alternative implementation of an antenna effect discharge circuit that includes a capacitor connected to the gate of a field effect transistor and a switch between the gate and the voltage supply circuit.
8 is a layout diagram of one exemplary antenna effect discharge circuit configured to protect multiple nodes on an integrated circuit.
9 is a simplified block diagram of an integrated circuit memory array including antenna effect discharge circuits as described herein.
10 is a simplified flow diagram of a method for manufacturing an integrated circuit utilizing antenna effect discharge circuits as described herein.
11 shows the drain current vs. drain voltage (Id-Vd) curve and drain voltage vs. body current (Ib) (Ib-Vd) curves of the CCFG NMOS device in the protection circuit.
12 shows experimental data including drain current vs. drain voltage (Id-Vd) curve and drain voltage vs. body current (Ib) (Ib-Vd) curves of the CCFG PMOS device in the protection circuit.
13 shows experimental data including discharge current of the completed CCFG CMOS protection circuit (when gates and wells are floating) as in the case of FIGS. 5 and 6.
Fig. 14 is a TEM photograph of the cross section of the measured 8-layer 3D VG device.
15 is a graph showing the initial threshold voltage distribution of a memory cell on multiple layers of a tested device.
16 shows the SSL Vt distribution of the tested device.
17 is a schematic diagram of a NAND string simplified for reference.
18 is a graph showing three SSL threshold voltage distributions (Vt ranges) with increasing sigma (σ).
19 is a graph of low and high threshold states in a tested device for testing a programming checkerboard window.
20 is a circuit diagram of an example of an antenna protection circuit applied for CMOS decoder design.

A detailed description of embodiments of the invention is provided with reference to FIGS. 1-20.

1 shows a conventional protection circuit for an antenna effect based on a pair of dynamic threshold voltage MOS transistors 10,11. The drain of the PMOS transistor 10 is connected to the substrate ground 12. Similarly, the drain of the NMOS transistor 11 is connected to the substrate ground 12. The channel well 13 in the channel region of the PMOS transistor 10 is connected to the gate of the PMOS transistor 10 using a lower patterned conductor such as a first metal layer. Similarly, the channel well 14 in the channel region of the NMOS transistor 11 is connected to the gate of the NMOS transistor 11 using a lower patterned conductor such as the first metal layer. The sources of the PMOS transistor 10 and the NMOS transistor 11 are connected to a node 15 protected from charge buildup caused by the antenna effect.

The terms "source" and "drain" are customarily commonly used to refer to the terminals of field effect transistors with reference to the direction of the dominant current flow in the transistor. This customary designation is ambiguous in some situations, such as when describing devices that maintain current flow in both directions and when the terminals describe devices with symmetric structures. The terms "source" and "drain" as used herein merely give distinctive markings for the two terminals of the field effect transistors without implying the dominant current flow direction or the structure of the terminals. As such, the terms "source" and "drain" are interchangeable herein.

The gate oxides for the MOS transistor pair 10, 11 are thick enough to maintain high voltage operation for flash memory devices or other high voltage integrated circuits. The thick gate oxide can be easily fabricated in a flash memory device using, for example, the same process steps used to fabricate thick oxides for charge pump transistors.

During manufacturing, positive charge is conducted through the PMOS transistor 10 to ground 12, and negative charge is conducted through the NMOS transistor 11 to ground at very low voltages. For example, the NMOS transistor 11 will operate at a voltage close to, for example, a junction forward turn on voltage of 0.6V. Likewise, the PMOS transistor 10 will operate at a voltage close to, for example, a junction forward turn-on voltage of -0.6V. For a discussion of the operation of dynamic threshold voltage MOS devices, see "IEEE ELECTRON DEVICES" (Vol. 38, No. 11, November, 1991). See also US Patent No. 7,196,369 issued March 27, 2007 (invention name: "PLASMA DAMAGE PROTECTION CIRCUIT FOR A SEMICONDUCTOR DEVICE").

During operation of the integrated circuit, the gate of the PMOS device 10 is connected by a line 16 to a high positive voltage VPP, which is the PMOS device 10 when the highest operating potential is applied to the protected node. ) Is high enough to turn off. Likewise, the gate of the NMOS device 11 is connected by a line 17 to a high magnitude negative voltage VNP, which is the NMOS device 11 when the largest negative operating potential is applied to the protected node. It has enough size to turn it off.

During fabrication, when the voltage on the node being protected quickly becomes high, the gate and substrate terminals on the transistors charge very quickly within the dynamic threshold structure shown in FIG. 1. As a result, gate potential can be generated for very low substrates that are difficult to turn on. Therefore, the protection circuits as in the case of FIG. 1 do not turn on completely quickly in some conditions. The protection provided thereby may not be very effective in rapidly discharging accumulated charge in protected nodes, such as word lines, which may be exposed to significant charge effects during manufacturing.

FIG. 2 is a three dimensional disclosed herein as an example of a device having multiple patterned conductor layers comprising patterned polysilicon layers and patterned metal layers, which can be used with the antenna effect discharge circuits described herein. (3D) An exemplary perspective view of a NAND flash memory array structure. See U.S. Patent No. 8,503,213. Of course, many other types of devices utilize multiple patterned conductors and may not be protected using the antenna effect discharge circuits described herein. In FIG. 2, the insulating material has been removed from the drawing to expose additional structures. For example, insulating layers are removed between semiconductor strips in ridge-shaped stacks, and between ridge-shaped stacks of semiconductor strips.

The multi-layer array is formed on an insulating layer and patterned to provide a plurality of word lines 425-1, ..., 425-n-1, 425-n conformal to a plurality of ridge-shaped stacks. Polysilicon layers. The plurality of ridge-shaped stacks include semiconductor strips 412, 413, 414, and 415. Semiconductor strips in the same plane are electrically connected together by stairstep structures.

The stepped structures 412A, 413A, 414A, 415A terminate semiconductor strips such as semiconductor strips 412, 413, 414, 415. As illustrated, these stepped structures 412A, 413A, 414A, 415A are electrically connected to other bit lines for connection to select planes in the array of decoding circuitry. These stepped structures 412A, 413A, 414A, and 415A can be patterned at the same time when the plurality of ridge-shaped stacks are defined.

The stepped structures 402B, 403B, 404B, 405B terminate semiconductor strips such as semiconductor strips 402, 403, 404, 405. As illustrated, these stepped structures 402B, 403B, 404B, 405B are electrically connected to other bit lines for connection to select planes in the array of decoding circuitry. These stepped structures 402B, 403B, 404B, and 405B can be patterned at the same time when the plurality of ridge-shaped stacks are defined.

Any given stack of semiconductor strips is connected to the stepped structures 412A, 413A, 414A, 415A, or the stepped structures 402B, 403B, 404B, 405B, but not all in this configuration. Does not. The stack of semiconductor strips has one of two opposing orientations: bit line end orientation at the bit line end, or bit line end orientation at the source line end. For example, the stack of semiconductor strips 412, 413, 414, 415 has a source line end orientation at the bit line end, and the stack of semiconductor strips 402, 403, 404, 405 has a source line end In the bit line has an end orientation.

The stack of semiconductor strips 412, 413, 414, 415 is terminated at one end by the stepped structures 412A, 413A, 414A, 415A, SSL gate structure 419, gate select line GSL ) 426, word lines WL 425-1 to 425-N, and gate select line GSL 427, terminated at the other end by a corresponding source line. The stack of semiconductor strips 412, 413, 414, 415 does not reach the stepped structures 402B, 403B, 404B, 405B.

The stack of semiconductor strips 402, 403, 404, 405 is terminated at one end by the stepped structures 402B, 403B, 404B, 405B, SSL gate structure 409, gate select line GSL ) 427, word lines WL (425-N to 425-1) and gate select line (GSL) 426, the other end by the source line (ambiguous by other parts of the figure) Ends in. The stack of semiconductor strips 402, 403, 404, 405 does not reach the stepped structures 412A, 413A, 414A, 415A.

A layer of memory material insulates the word lines 425-1 through 425-n from the semiconductor strips 412-415 and 402-405, as detailed in previous figures. Gate Select Lines (GSL) 426 and 427 are conformal to the plurality of ridge-shaped stacks, similar to the word lines.

Bit lines and string select lines are formed in the metal layers ML1, ML2 and ML3.

Transistors are formed between the stepped structures 412A, 413A, 414A and the word line 425-1. In the transistors, the semiconductor strip (eg, 413) functions as a channel region of the device. SSL gate structures (eg, 419, 409) are patterned during the same step in which the word lines 425-1 to 425-n are defined. A layer of silicide can be formed over the top surfaces of the word lines, along the ground select lines and over the gate structures 409 and 419. The layer of memory material can serve as a gate dielectric for the transistors. These transistors function as string select gates connected to the decoding circuitry to select specific ridge-shaped stacks in the array.

The first metal layer ML1 includes string selection lines having a longitudinal orientation with respect to the semiconductor material strips. These ML1 string select lines are connected to other SSL gate structures (eg, 409, 419) by interlayer connectors.

The second metal layer ML2 includes string selection lines having a longitudinal direction parallel to the word lines. These ML2 string select lines are connected to other ML1 string select lines by interlayer connectors.

In combination, these ML1 string select lines and ML2 string select lines cause the string select line signal to select a particular stack of semiconductor strips.

The first metal layer ML1 also includes two source lines having a widthwise orientation parallel to the word lines.

The third metal layer ML3 includes bit lines having a longitudinal orientation parallel to the semiconductor material strips. Other bit lines are electrically connected to the other steps of the stepped structures 412A, 413A, 414A, 415A and 402B, 403B, 404B, 405B by interlayer connectors. These ML3 bit lines allow the bit line signal to select a specific horizontal plane of semiconductor strips.

A fourth metal layer (not shown-may be referred to as ML4) can be included for connection of peripheral circuits such as drivers for the memory array, sense amplifiers, decoders, voltage supply generators and the like.

Interlayer connectors in vias between patterned layers (shown but not denoted) are between nodes and conductors in the multiple patterned conductor layers and other components on the device. It is provided to secure the connection.

3 is a circuit diagram for an antenna protective discharge circuit comprising field effect transistors having their gates connected to a semiconductor substrate via a capacitor. The antenna effect discharge circuit is a terminal (for example, a field effect transistor 50) connected to a gate such as a node 55 on the device protected from charge accumulation and a gate of the field effect transistor 50 in the circuit. And a terminal (for example, the source of the field effect transistor 50) through which the accumulated charge can be discharged to the substrate.

In the above circuit, the p-channel field effect transistor 50 and the n-channel field effect transistor 51 have drains connected to a node 55 protected from antenna effect charges. Sources of the field effect transistors 50 and 51 are connected to the substrate 52. The gate of the field effect transistor 50 includes a first terminal connected to the conductor 57 by a patterned conductor 57 (eg, polysilicon line) and a first terminal connected to or connected to the substrate 52. It is connected to a capacitor 65 having two terminals. The gate of the field effect transistor 51 is a first terminal connected to the conductor 60 by a patterned conductor 60 (eg, a polysilicon line) and a first terminal connected to or connected to the substrate 52. It is connected to a capacitor 66 having two terminals.

The p-channel field effect transistor 50 has a channel in the substrate in an n-type semiconductor region referred to herein as a channel well 53. The channel well 53 is connected to a conductor 56. The conductor 56 and conductor 57 are not connected during manufacture of the device until the upper patterned conductor layer, preferably the topmost patterned conductor layer, is formed. The upper patterned conductor layer includes a conductor 58 that provides a connection between the channel well 53 and the gate of the field effect transistor 50 via the conductors 57 and 56. Further, the conductor 58 is connected to the voltage supply circuit, which provides the bias voltage VPP.

The n-channel field effect transistor 51 has a channel in the substrate within a p-type semiconductor region referred to herein as a channel well 54. The channel well 54 is connected to the conductor 61. The conductors 61 and 60 are not connected during manufacture of the device until the upper patterned conductor layer, preferably the topmost patterned conductor layer, is formed. The upper patterned conductor layer includes a conductor 62 that provides connections between the channel well 54 and the gate of the field effect transistor 51 via the conductors 60 and 61. In addition, the conductor 62 is connected to the voltage supply circuit, which provides the bias voltage VNP.

FIG. 4 illustrates a substrate and well structure that can be used for the high voltage p-channel and high voltage n-channel field effect transistors (HV-PMOS and HV-NMOS) for the circuit of FIG. 3. In this example, the device is formed on a p-type substrate 100. The p-channel field effect transistor is formed in the n-type semiconductor well 103, which corresponds to the channel well 53 in FIG. The n-channel field effect transistor is formed in a p-type semiconductor well 102, which is sequentially isolated from the substrate 100 by a deep n-type well 101. The p-type semiconductor well 102 corresponds to the channel well 54 of FIG. 3.

4 illustrates source and drain regions 106, 107, gate 105 and gate insulator 108 of the p-type field effect transistor (HV-PMOS). In addition, an n-type contact region 104 is formed in the n-type well 103 to provide a connection to the bulk of the channel well. Further, source and drain regions 113 and 114 of the n-type field effect transistor (HV-NMOS), gate 112 and gate insulator 115 are illustrated. Also, a p-type contact region 111 is formed in the p-type well 102 to provide a connection to the bulk of the channel well. Additionally, an n-type contact region 110 is formed in the deep n-type well 101 to provide a connection of the deep n-well to biasing circuitry to help insulate the channel well 102. . To provide a substrate connection for the capacitors, although not shown, p-type contact regions 117 and 118 can be disposed within the substrate outside the wells 101 and 103. Shallow trench element isolation (STI) structures (eg, 119) may be disposed between doped regions as illustrated for improved isolation.

1, in a prior art DTMOS type antenna effect discharge circuit, the gate and channel well contacts (eg, 105, 104) are connected during manufacture. This connection causes a voltage between the gate and the channel well that remains close to zero during charge events that apply a positive voltage to the drain 107. In the circuit described herein with respect to FIG. 3, the gate and channel well contacts (eg, 105, 104) are not connected during all or most of the formation of the patterned conductor layers. Rather, the gate (eg, 105) is connected to a capacitor, while the channel well (eg, 104, 103) is floating. Thus, even while the channel well is boosted by an increase in voltage on the node being protected, the gate potential is gate coupled because the gate capacitance for the well of the capacitor and the transistor divides the voltage difference. It will only change by the factor of the gate coupling ratio. This causes the field effect transistor to turn on faster during an antenna effect charging event, thereby discharging unwanted voltages more effectively.

The capacitors 65 and 66 are formed by a patterned conductor, such as the same patterned conductor, having a source and a drain connected together and forming the gate of the corresponding field effect transistor (HV-PMOS or HV-NMOS). It can be implemented using a high voltage NMOS transistor in the p-type substrate connected to a capacitor having a gate. Optionally, the capacitors may be implemented by a single continuous well separated from the conductor by a dielectric layer, such as a layer of dielectric used to form the gate dielectric for the HV-NMOS and HV-PMOS devices of FIG. 3. In this implementation, there is no channel area under the conductor in this implementation. In order to achieve a high coupling ratio, the area of the conductor on the capacitor may be approximately larger than the area of the gate on the corresponding field effect transistors 50, 51. In one example, the area of the gate on the capacitor may be about 4 times larger than the area of the gate, so that a gate coupling ratio of about 0.8 can be implemented.

5 and 6 illustrate the antenna effect discharge circuit of FIG. 3 as generated during formation of lower patterned conductor layers on the device prior to forming the connection between the gate and channel wells. Reference numerals used in FIG. 3 are identical to corresponding elements, and will not be described again.

In the state shown in Fig. 5, a protected node, such as a word line, can be charged to a value of about -2V during the manufacturing stage. In this state, a p+ drain to n-type channel well junction is biased in the reverse direction within the p-channel field effect transistor 50. Therefore, the p-channel field effect transistor 50 remains off. However, an n+ drain to p-type channel well junction is biased forward in the n-channel field effect transistor 51. The capacitor 66 prevents the gate of the n-channel field effect transistor 51 from being charged to the same voltage as the p-type channel well 54. Thus, when the protected node reaches about 2 volts negative, the floating p-type channel well of the n-channel field effect transistor is rapidly charged through the forward junction to approximately the same voltage as the protected node. . When there is sufficient capacitance in the capacitor 66 to provide a relatively large gate coupling ratio, the p-type substrate (V _WL *(1-GCR)) is applied to the gate voltage by capacitive dividing (V _WL *(1-GCR)). It will move to a value greater than negative 1V (eg, >-1V) close to the zero voltage of 52). In this example, it maintains an amount of gate-to-channel well bias Vgb of a magnitude less than about 1V sufficient to turn on the n-channel field effect transistor that rapidly discharges unwanted charge on the node being protected during the fabrication step. .

In the state shown in Fig. 6, a protected node such as a word line is charged to a value of about +2V during the manufacturing step. In this state, the n+ drain to p-type channel well junction is reverse biased in the n-channel field effect transistor 51. Therefore, the n-channel field effect transistor 51 remains off. However, the p+ drain to n-type channel well junction is biased forward in the p-channel field effect transistor 50. The capacitor 65 prevents the gate of the p-channel field effect transistor 50 from moving at the same voltage as the n-type channel well 53. Thus, when the protected node reaches approximately positive 2 volts, the floating n-type channel wells of the p-channel field effect transistors are rapidly charged to approximately the same voltage by the forward junction. When there is sufficient capacitance in the capacitor 65 to provide a relatively large gate coupling ratio, the gate has a value less than about 1V close to the zero voltage of the p-type substrate 52 (eg, <+1V ). This is in this example a negative gate-to-channel well with a size less than about 1 V sufficient to turn on the p-channel field effect transistor 50 which rapidly discharges unwanted charges on the protected node during the fabrication step. Maintain the bias Vgb.

In the circuit of FIG. 3, after the upper patterned conductor layer, which can be the uppermost patterned conductor layer, is fabricated, the gate and channel wells are connected. In the processes in which charging may occur in a part, for example during passivation or other layers overlying the patterned conductor on the top, after connecting the gate and the channel well, the antenna effect discharge circuit The protection provided by can be less effective.

7 illustrates an alternative embodiment of an antenna effect discharge circuit capable of maintaining protection after formation of the patterned conductor layer used to connect the gate and the channel well. The same reference numerals as used in FIG. 3 are appropriately assigned to the circuit components. In this example, switches are added between the capacitors and the voltage supply circuit, which is applied to the field effect transistors 50 and 51 until the device receives operating voltages that may be close to the switches. It enables a process to keep the gates separated from the channel wells 53, 54. In this way, protection against the antenna effect can be maintained throughout the manufacturing process.

In this example, the switch for the p-channel field effect transistor 50 includes a first terminal (source or drain) and a second terminal connected to the gate via a conductor 57 by a first connector 70-1. A high voltage n-channel field effect transistor 70 having a second terminal (source or drain) connected to the voltage supply circuit by a connector 70-2 (for example, HV- as shown in FIG. 4) NMOS). One or both of the connectors 70-1, 70-2 may be formed in the top, preferably top, patterned conductor on the device. The gate of the n-channel field effect transistor 70 is connected to the voltage supply circuit to receive bias during an operation close to the switch, such as VPP.

In this example, the switch for the n-channel field effect transistor 51 includes a first terminal (source or drain) and a second terminal connected to the gate via a conductor 60 by a first connector 71-1. A high voltage p-channel field effect transistor 71 having a second terminal (source or drain) connected to the voltage supply circuit by a connector 71-2 (for example, HV- as shown in FIG. 4) PMOS). One or both of the connectors 71-1, 71-2 may be formed in the top, preferably top, patterned conductor layer on the device. The gate of the p-channel field effect transistor 71 is connected to the voltage supply circuit to receive a bias during operation close to the switch, such as VNP.

In this way, the antenna effect discharge circuit remains effectively until the switch transistors 70 and 71 are turned on at the closing switch.

8 is a layout diagram of an antenna protection circuit including capacitors connected to the gates of the high voltage field effect transistors. The layout in this example is formed on the p-type substrate 100. An n-type channel well 103 is formed in the substrate 100. In addition, deep n-type wells 101 are formed with p-type channel wells 102 therein. Substrate contacts (eg, 104, 110, 111 shown in FIG. 4) can be aligned around the wells to provide adequate bias during operation. In addition, guard rings (not shown) can be formed around the wells, for example using polysilicon layer conductors. The deep n-type well, the p-type substrate and the guard rings can be connected via the contacts and grounded during operation.

A set of high voltage n-channel field effect transistors is formed in the p-type channel well 102. In this example, three transistors are present in the well 102. The first transistor includes a drain terminal 202 and a source terminal 206. The second transistor includes a drain terminal 203 and a source terminal 207. The third transistor includes a drain terminal 204 and a source terminal 208. The drain terminals 202, 203, 204 are patterned conductors 210, 211, 212 in one of the lower patterned conductor layers, such as a first metal layer, by interlayer connectors indicated by small squares in the figure. Is connected to. The source terminals 206, 207, 208 are connected to patterned conductors 214, 215, 216 connected to corresponding nodes protected by the circuit. For example, the patterned conductor 214 may be a first metal layer conductor connected to common source lines 231 in the memory structure as in FIG. 2. The patterned conductor 215 may be a second metal layer conductor connected to string selection lines 232 in a memory structure as in the case of FIG. 2. The patterned conductor 216 may be a first metal layer conductor connected to one or more word lines 233 in a memory structure as in the case of FIG. 2.

The gates for the three transistors are a single patterned poly extending out of the region comprising the channel well 102 above the first n-type capacitor terminal diffusion 201 serving as the second terminal of the capacitor. It is formed by the silicon line 200. The area of the polysilicon line 200 above the capacitor terminal diffusion 201 provides the first terminal of the capacitor, and the p-type well 102 as described above to implement a high gate coupling ratio Must be larger than the areas of the gates of the transistors within.

The patterned conductors 210, 211, 212 are connected to the p-type substrate 100 as indicated by arrows in the figure.

The patterned conductor 258 is connected to the gate polysilicon line 200 by interlayer connectors. Likewise, the patterned conductor 250 is connected to the channel well 102 by interlayer connectors. The patterned conductors 258 and 250 can be formed in one of the lower portions of the patterned conductor layers on the device, such as in a first metal layer. The conductors 258 and 250 are connected to the conductor 260 in the upper patterned conductor layer, denoted ML4 in this example for a four metal process.

In addition, high voltage p-channel field effect transistors are formed in the n-type channel well 103. In this example, three transistors are present in the well 103. The first transistor includes a drain terminal 306 and a source terminal 302. The second transistor includes a drain terminal 307 and a source terminal 303. The third transistor includes a drain terminal 308 and a source terminal 304. The drain terminals 306, 307, 308 are connected by interlayer connectors to patterned conductors 314, 315, 316 in one of the lower patterned conductor layers, such as a first metal layer. The source terminals 302, 303, 304 are connected to patterned conductors 310, 311, 312 connected to corresponding nodes protected by the circuit. For example, the patterned conductor 310 can be connected to common source lines 231, and the patterned conductor 311 can be connected to string selection lines 232. The patterned conductor 312 may be connected to one or more word lines 233.

The gates for the three transistors are a single patterned poly extending outside the region comprising the channel well 103 above the second n-type capacitor terminal diffusion 301 serving as the second terminal of the capacitor. It is formed by the silicon line 300. The area of the polysilicon line 300 above the capacitor terminal diffusion 301 provides the first terminal of the capacitor, and as described above to implement a high gate coupling ratio, the n-type well 103 Within the area of the gates of the transistors.

The patterned conductors 314, 315, and 316 are connected to the p-type substrate 100 as indicated by the arrows in the figure.

The patterned conductor 358 is connected to the polysilicon line 300 by interlayer connectors. Likewise, the patterned conductor 350 is connected to the channel well 103 by interlayer connectors. The patterned conductors 358 and 350 can be formed in one of the lower portions of the patterned conductor layers on the device, such as in a first metal layer. The conductors 358 and 350 are connected to the conductor 360 in the upper patterned conductor layer, denoted ML4, for example for a four metal process in this example.

9 is a simplified block diagram of an integrated circuit having a flash memory array 510 that includes antenna effect discharge circuits 527. In some embodiments, the array 510 is a 3D memory and includes multiple levels of cells. A row decoder 511 is connected to a plurality of word lines, string select lines, and ground select lines 512 in the memory array 510. The level/column decoder in block 513 is connected to the set of page buffers 516 via data bus 517 in this example, with global bit lines and source lines. 514. Addresses are provided on the bus 515 to the level/column decoder (block 513) and row decoder (block 511). Data may be passed over a data-in line 523 to other processors on the integrated circuit, such as a general purpose processor or dedicated application circuitry or a combination of modules providing system-on-chip functionality supported by the array 510. Circuitry 524 (eg, including input/output ports). Data is supplied via data input line 523 to input/output ports or to other data destinations for the interior or exterior of the integrated circuit 525.

The controller implemented in this example as a state machine 519 is configured to provide bias array supply voltages generated or provided through the voltage supply circuit in block 518 to perform various operations including erase, program, and read. Provides signals that control the application. The controller can be implemented using a dedicated logic circuit known in the art. In alternative embodiments, the controller includes a general purpose processor that can be implemented on the same integrated circuit, which runs a computer program that controls the operations of the device. In still other embodiments, a combination of a dedicated logic circuit and a general purpose processor can be utilized for the implementation of the controller.

The antenna effect discharge circuits 527 with capacitors connected to gates, such as the circuits of FIGS. 3 and 7 are connected to the conductors represented by line 526 in the memory array in this example, which are word lines Field, bit lines, string select lines, ground select lines, or other conductive lines that can be charged during manufacturing. The antenna effect discharge circuits 527 are connected to the voltage supply circuit 518 by a topmost patterned conductor layer 528 on the device, here indicated as ML4, for a four metal device. The voltage supply circuit 518 has a voltage that provides circuits such as positive and negative voltage charge pumps, level shifters and voltage regulators. In an exemplary 3D NAND device, positive and negative voltage charge pumps can be included to generate operating voltages as high as +30 volts and -10 volts, for example. Of course, the largest positive and negative operating voltages specified here as VPP and VNP depend on the particular device.

The number of antenna effect discharge circuits provided in a particular integrated circuit will depend on manufacturing environments, available space and the needs of a particular product. In some example products, there may be one antenna effect discharge circuit per word line. In other example products, one protection device may be shared among a plurality of word lines. Other nodes in the integrated circuitry on the device may also be protected.

10 is a simplified flow diagram of a manufacturing process including plasma effect discharge circuits as described herein. The process includes forming 600 an integrated circuit on a substrate. The process also includes forming an antenna effect discharge circuit on the substrate (601) and connecting a gate in the antenna effect discharge circuit to the substrate using the capacitor (602). The process includes providing 603 a voltage supply circuit on or connected to the integrated circuit. Finally, the gate is connected 604 to the voltage supply circuit during the manufacturing process using an upper patterned conductor layer, preferably a top layer.

Although not shown in FIG. 10, the process may include providing a switch on the device between the gate and the voltage supply circuit as illustrated above with respect to FIG. The switch may be configured to close during operations in which the gate is connected to the voltage supply circuit via the switch. The switch can be implemented using high voltage field effect transistors with gates connected to the voltage supply circuits, such as HV-NMOS or HV-PMOS devices.

The step of forming the antenna effect discharge circuit may include forming n-type and p-type channel wells in the substrate and first and second capacitor terminal diffusions in the substrate. A p-channel field effect transistor has a gate, a source and a drain in the n-type channel well, and is formed in the n-type channel well. An n-channel field effect transistor has a gate, a source and a drain in the p-type channel well, and is formed in the p-type channel well. In addition, a first capacitor is formed having a first terminal within or connected to the first capacitor terminal diffusion and a second terminal connected to the gate of the p-channel field effect transistor. A second capacitor is formed having a first terminal in or connected to the second capacitor diffusion and a second terminal connected to the gate of the n-channel field effect transistor. The process comprises connecting one of the source and drain of the p-channel field effect transistor to the protected node using a patterned conductor and the other of the source and drain of the p-channel field effect transistor to the device substrate. It involves connecting to. In addition, the process may include connecting one of the source and drain of the n-channel field effect transistor to the protected node using a patterned conductor, and the other of the source and drain of the n-channel field effect transistor. And connecting to the device substrate.

In this example, the step of providing a voltage supply circuit passes through a first patterned conductor in the upper layer to the gate of the p-channel field effect transistor to turn off the p-channel field effect transistor during operation. A first voltage output providing a connected VPP; And a voltage having a first voltage output that provides a VNP connected to a gate of the n-channel field effect transistor via a second patterned conductor in the upper layer to turn off the n-channel field effect transistor during operation. And providing a supply circuit.

Providing a switch includes forming a first switch on the device having a first terminal connected to the first patterned conductor in the upper layer and a second terminal connected to the voltage supply circuit and the first Configuring the switch to be closed during operation; And forming a second switch on the device having a first terminal connected to the second patterned conductor in the upper layer and a second terminal connected to the second voltage supply circuit and the second switch. And configuring to close during operation.

A new antenna protection circuit and manufacturing method are described. In the example shown in FIGS. 3, 5 and 6, the gates of the n-channel and p-channel field effect transistors are connected to the first metal layer ML1 rather than connected as in the circuit of the prior art shown in FIG. It floats to separate later.

The gates are connected to large capacitors, allowing them to be connected to the p-type substrate. During antenna charging, the gate is closer to the p-type substrate potential due to the capacitor. This makes it easier to turn on the field effect transistors. Positive charge will discharge through the p-channel field effect transistor, while negative charge passes through the n-channel field effect transistor. Experimental data shows that the p-channel field effect transistor and the n-channel field effect transistor used in the new protection circuit are positively smaller than 2V, providing very good manufacturing process antenna protection for any new device. Or a point that can be activated at a negative voltage. It has also been demonstrated that a larger ratio of capacitor area to gate area results in higher discharge currents.

The gate coupling ratio (GCR) for higher substrates can make the gates closer to the substrate potential to provide even lower turn-on voltages (<2V) for good protection.

In the last patterned conductor layer, such as the topmost metal layer, the antenna protection circuit is connected to the VPP and VNP terminals of the voltage supply circuit, so that they are turned off during operation and do not affect the operation of the device.

To prevent any possible charging during the passivation process or other higher layer process, a switch of the buffer transistor can be added between the gate of the protection circuits and the voltage supply circuit.

The new antenna protection circuit can be applied to conventional flash memory arrays, other memory devices and logic circuits among different types of integrated circuits.

The very low protection voltage (<+/-2V) capability can be applied to advanced memory devices, such as programmable resistive ReRAM or phase change PCRAM, where very low voltages can cause device performance to degrade during charging of the manufacturing process. have.

The charging effect of the manufacturing process is known to degrade the initial Vt of 3D NAND flash memory integrated circuits. In the above examples, an antenna protection circuit using a capacitively coupled floating gate (CCFG) CMOS circuit can be applied to the word line WL and select transistor (SSL) decoder for the memory integrated circuit. The experimental results of this circuit show a very low turn-on voltage (<+/-2V) for discharge that provides protection for the memory devices. With this technique, a fully integrated 3D NAND flash device exhibits a good initial threshold voltage Vt distribution with no apparent charge effect across the memory array.

Moreover, the string selection line (SSL) transistor threshold voltage Vt distribution (variations) may affect the minimum Vdd bias. As an improved SSL Vt distribution implemented using the antenna protection circuit as in the case of Figures 3, 5 and 6, it has been proven that a 3D VG NAND flash can support Vdd as small as 1.6V with a successful programming window. do.

The antenna protection circuit described herein may be applied in the word line WL or string selection line SSL/ground selection line GSL decoder. Experimental results for 3D NAND flash integrated circuits are demonstrated.

S.H. including peripheral CMOS devices. Chen, H.T. Lue, et al., as described in "A highly scalable 8-layer vertical gate 3D NAND with split-page bit line layout and efficient binary-sum Minimal incremental layer cost (MiLC) staircase contacts" (IEDM pp. 21-24, 2012). The same fully integrated split-page 3D VG NAND flash was studied in these parts.

The protection circuit as in the case of Figs. 3, 5 and 6 is placed in the tested device.

FIG. 11 shows the drain current vs. drain voltage (Id-Vd) curve of the CCFG NMOS device in the protection circuit in the situation shown in FIG. 5 above when the gate and PWI are floating while the p-substrate, source and DNW are grounded And drain voltage versus body current (Ib) (Ib-Vd) curves. This does not discharge the positive bias, but the negative voltage can be easily turned on below -2V to discharge. At -7V, a significant body current Ib is observed. This is due to the parasitic bipolar turn-on through the N+-PWI-DNW parasitic BJT.

Fig. 12 shows the drain current vs. drain voltage (Id-Vd) curve and the drain voltage vs. body current (Ib) of the CCFG PMOS device in the protection circuit in the situation shown in Fig. 6 when the gate and N-well float. Ib-Vd). This shows a low turn-on voltage at <+2V. No parasitic bipolar turn-on mode is observed, thus no body current is observed. The turn-on voltage at positive bias is less than 2V, allowing good protection at low voltages. The body current Ib is small, indicating that there is no parasitic BJT mode.

13 shows experimental data including the discharge current of the completed CCFG CMOS protection circuit (when the gates and wells are floating) as in the case of FIGS. 5 and 6. It exhibits a very low turn-on voltage below +/-2V and provides ideal protection for these devices. The higher capacitance ratio above the FG area gives higher turn-on current. Note that both NMOS and PMOS can be high voltage (HV) devices that maintain very high operating voltages of WL, SSL or GSL.

14 is a photograph of a cross section of the 8-layer 3D VG device measured by TEM. 15 is a graph showing initial threshold voltage distributions of memory cells on multiple layers of the tested device. As the protection circuit, the initial state as shown in Fig. 15 is excellent and has a nearly normal Vt distribution. Certain deviations are observed between the eight layers, represented by PL1 to PL8, which is expected because there are process and dimensional deviations between memory layers.

16 shows the SSL Vt distribution. SSL's native sigma can be less than 250mV. With specific trimming performed by soft programming and verify, the sigma can be further reduced to almost 100 mV.

The effect of the SSL distribution is shown in FIGS. 17 and 18. 17 is a schematic diagram of a simplified NAND string for reference. During self-boosting programming, both BL bias and SSL gate bias are applied to Vdd. 18 is a graph showing three SSL threshold voltage distributions (Vt ranges) with increasing sigma (σ). The lower boundary of the Vt range should be higher than 0.4V to ensure sufficient punch-through margin to maintain self-boosting. On the other hand, the higher boundary of the Vt range limits the minimum Vdd of authorization in SSLs and BLs. A denser SSL distribution (lower σ) may enable lower Vdd.

The denser Vt distribution of the SSL can be important in reducing the minimum required Vdd. 19 is a graph of low and high threshold states in the tested device for programming a checkerboard window, showing an improved SSL Vt distribution, and the tested 3D VG NAND flash can operate under minimal Vdd=1.6V. The lower Vdd contributes to reducing power consumption.

In Fig. 20, an implementation of an antenna protection circuit applied for CMOS decoder design is shown. The antenna effect discharge circuit of a CMOS decoder comprising a p-channel field effect transistor 772 and n-channel field effect transistor 771 having drains connected to a node 755 connected to a word line driven by a decoder. It protects some of the circuitry. The gates of the transistors 771 and 772 are connected to decode signals according to the design of the decoder. The n-channel field effect transistor 771 is formed in the p-type well 773. The p-channel field effect transistor 772 is formed in the n-type well 774.

In the above circuit, a PMOS protection circuit including a p-channel field effect transistor 750 is connected to the p-channel transistor 772, and an NMOS protection circuit including an n-channel field effect transistor 751 is It is connected to an n-channel transistor 771. The p-channel field effect transistor 750 and the n-channel field effect transistor 751 are the p-channel field effect transistor 772 and the n-channel field effect transistor in the decoder circuit protected from antenna effect charges The drains are respectively connected to the n-type well 774 and the p-type well 773 of (771). Sources of the field effect transistors 750 and 751 are connected to the substrate 752. The gate of the field effect transistor 750 has a first terminal and a substrate 752 connected to the conductor 757 by a patterned conductor 757 (eg, a polysilicon line or a first metal layer line ML1). ) Is connected to a capacitor 765 having a second terminal connected to or connected to it. The gate of the field effect transistor 751 is a patterned conductor 760 (eg, polysilicon line or first layer metal line). Is connected to a capacitor 766 having a first terminal connected to the conductor 760 and a second terminal within or connected to the substrate 752.

The p-channel field effect transistor 750 has a channel in an n-type semiconductor region in the substrate referred to herein as a channel well 753. The channel well 753 is connected to a conductor 756. The conductor 756 and conductor 757 are not connected during manufacture of the device until an upper patterned conductor layer, preferably a topmost patterned conductor layer, is formed. The upper patterned conductor layer includes conductors 758 that provide connections between the channel wells 753 and the gates of the field effect transistor 750 via the conductors 757 and 756. Further, the conductor 758 is connected to the voltage supply circuit, which provides the bias voltage VPP.

The n-channel field effect transistor 751 has a channel in a p-type semiconductor region in the substrate referred to herein as a channel well 754. The channel well 754 is connected to a conductor 761. The conductors 761 and 760 are not connected during manufacture of the device until an upper patterned conductor layer, preferably a topmost patterned conductor layer, is formed. The upper patterned conductor layer includes a conductor 762 that provides a connection between the channel well 754 and the gate of the field effect transistor 751 via the conductors 760 and 761. In addition, the conductor 762 is connected to the voltage supply circuit, which provides the bias voltage VNP.

A single CCFG NMOS protection circuit as shown in FIG. 20 can be applied to protect the shared p-type well 773 PWI of a plurality of NMOS drivers (only one is shown), while a single CCFG PMOS multiple PMOS It is applied to a shared n-type well 774 of drivers (only one is shown). This greatly reduces the required area.

Although the present invention has been described with reference to preferred embodiments and examples in the foregoing, it will be understood that these examples are intended to be illustrative rather than limiting. It will be appreciated by those skilled in the art that changes and combinations may be easy and that the modifications and combinations fall within the spirit of the invention and the scope of the following claims.

10: PMOS transistor 11: NMOS transistor
12: Ground 13: Channel well
14: Channel well 15: Node
50: p-channel field effect transistor 51: n-channel field effect transistor
52: p-type substrate 53: channel well
54: Channel well 55: Node
56: Conductor 57: Conductor
58: Conductor 60: Conductor
61: Conductor 62: Conductor
65: Capacitor 66: Capacitor
70: n-channel field effect transistor 70-1: first connector
70-2: Second connector 71: p-channel field effect transistor
71-1: First connector 71-2: Second connector
100: p-type substrate 101: deep n-type well
102: p-type well 103: n-type well
105: gate 106: source area
107: Drain area 108: Gate insulator
110: n-type contact area 111: p-type contact area
112: Gate 113: Source area
114: Drain area 115: Gate insulator
200: Polysilicon line 201: First n-type capacitor terminal diffusion
202, 203, 204: Drain terminal 206, 207, 208: Source terminal
210, 211, 212: Patterned conductors 214, 215, 216: Patterned conductors
231: Common source line 232: String selection line
233: Word line 250: Patterned conductor
258: patterned conductor 260: conductor
300: Polysilicon line 301: Second n-type capacitor terminal diffusion
302, 303, 304: Source terminal 306, 307, 308: Drain terminal
310, 311, 312: Patterned conductors 314, 315, 316: Patterned conductors
350: patterned conductor 358: patterned conductor
360: Conductors 402, 403, 404, 405: Semiconductor strips
402B, 403B, 404B, 405B: Stepped structures
409: SSL gate structure 419: SSL gate structure
412, 413, 414, 415: Semiconductor strips
412A, 413A, 414A, 415A: Stepped structures
425-1 to 425-N: Word lines 426: Gate selection line
427: Gate selection line 510: Flash memory array
511: Low decoder 513: Level/column decoder
516: Page buffer 518: Voltage supply circuit
519: State machine 527: Antenna effect discharge circuit
528: Top patterned conductor layer 750: p-channel field effect transistor
751: n-channel field effect transistor 752: Substrate
755: Node 757: Patterned conductor
758: Conductor 760: Patterned conductor
761: Conductor 762: Conductor
765: Capacitor 766: Capacitor
771: n-channel field effect transistor 772: p-channel field effect transistor
773: p-type well 774: n-type well
ML1: First metal layer ML2: Second metal layer
ML3: Third metal layer

Claims (21)

In an integrated circuit device,
Device substrates;
Layers and interlayer connectors of a plurality of patterned conductors comprising an upper layer and one or more lower layers on the device substrate;
An antenna effect discharge circuit on the device substrate having a gate;
A capacitor having a first terminal in the device substrate or connected to the device substrate and a second terminal connected to the gate;
A voltage supply circuit configured to provide a voltage sufficient to bias the antenna effect discharge circuit in an off state during operation;
A patterned conductor in the upper layer connecting the gate to the voltage supply circuit; And
And a switch configured to be closed during operation of the device and including first and second terminals, the first terminal being connected to the gate by a first connector, and the second terminal being said by a second connector And connected to a voltage supply circuit, wherein one or both of the first and second connectors comprises the patterned conductor in the top layer. The integrated circuit device according to claim 1, wherein the upper layer is a topmost patterned conductor layer in the device. The integrated circuit device according to claim 1, further comprising a passivation layer over the upper layer. delete The method of claim 1, wherein the antenna effect discharge circuit,
On the substrate, a field effect transistor having a gate in one of the layers, a channel well connected to a conductor in one of the layers via one or more of the layers, and a source and drain in the channel well;
One of the source and drain of the field effect transistor is connected to a node having operating voltages applied during the operation of the device via one or more of the lower layers, and the source and drain of the field effect transistor The other is connected to the device substrate via one or more of the underlying layers. 6. The integration of claim 5, wherein the device substrate comprises a p-type semiconductor having an n-type well, the field effect transistor comprises a PMOS transistor, and the n-type well is the channel well. Circuit device. The device substrate of claim 5, wherein the device substrate comprises a p-type semiconductor having a p-type well in an n-type well,
The field effect transistor includes an NMOS transistor, wherein the p-type well is the channel well. 6. The integrated circuit device of claim 5, wherein the channel well is a doped well in the device substrate. The integrated circuit device according to claim 1, further comprising a memory array having a word line, wherein the antenna effect discharge circuit is connected to the word line. The integrated circuit device according to claim 1, wherein the voltage supply circuit comprises a charge pump circuitry on the device substrate. In an integrated circuit device,
Having a device substrate;
An integrated circuit portion having a plurality of patterned conductor layers on the device substrate, the plurality of patterned conductor layers comprising an upper layer and one or more lower layers, and the one or more lower layers are A node having an operating voltage applied thereto during operation;
A p-channel field effect transistor and an n-channel field effect transistor having respective gates, respective channel wells and respective sources and drains in the respective channel wells, on the device substrate;
A first capacitor having a first terminal in a region within the device substrate or connected to the region and a second terminal connected to the gate of the p-channel field effect transistor;
A second capacitor having a first terminal connected to or within the region within the device substrate and a second terminal connected to the gate of the n-channel field effect transistor;
One of the source and drain of each of the p-channel field effect transistor and the n-channel field effect transistor is connected to the node, and the source and drain of each of the p-channel field effect transistor and the n-channel field effect transistor The other is connected to the device substrate;
Providing a first voltage sufficiently biasing the p-channel field effect transistor in the off state during operation at the operating voltages, and sufficiently biasing the n-channel field effect transistor in the off state during the operation at the operating voltages And a voltage supply circuit configured to provide a second voltage;
A first patterned conductor in the upper layer connecting the gate and channel wells of the p-channel field effect transistor to the voltage supply circuit;
And a second patterned conductor in the upper layer connecting the gate and channel wells of the n-channel field effect transistor to the voltage supply circuit. 12. The integrated circuit device of claim 11, wherein the top layer is a topmost patterned conductor layer in the device. 13. The integrated circuit device of claim 12, further comprising a passivation layer over the top layer. The method of claim 12,
Configured to be closed during operation of the device, further comprising a first switch on the device having first and second terminals, the first terminal being connected to a gate of the p-channel field effect transistor by a first connector And the second terminal is connected to the voltage supply circuit by a second connector, and one or both of the first and second connectors includes the first patterned conductor in the upper layer;
Configured to be closed during operation of the device, further comprising a second switch having first and second terminals, the first terminal being connected to the gate of the n-channel field effect transistor by a first connector, the A second terminal is connected to the voltage supply circuit by a second connector, wherein one or both of the first and second connectors comprises the second patterned conductor in the upper layer. . 12. The method of claim 11, wherein the device substrate comprises a p-type semiconductor material;
The channel well of the p-channel field effect transistor is an n-type well in the device substrate;
The channel well of the n-channel field effect transistor is an integrated circuit device, characterized in that the p- type well in the n- type well in the device substrate. 12. The integrated circuit device of claim 11, wherein the integrated circuit portion has a memory array having a word line, and the node comprises the word line. A method of manufacturing an integrated circuit device,
Forming an integrated circuit portion having a node protected from plasma discharge on the device substrate;
Forming, on the device substrate, an antenna effect discharge circuit having a terminal connected to the node and a gate connected to the device substrate via a capacitor;
Providing, on the device substrate, a voltage supply circuit that biases the gate during operation to turn off the antenna effect discharge circuit;
Connecting the gate to the voltage supply circuit using a patterned conductor layer on top of the device substrate;
Providing a switch having first and second terminals on the device, the first terminal being connected to the gate by a first connector, and the second terminal supplying the voltage by a second connector Connected to a circuit, one or both of the first and second connectors comprising a conductor in the upper patterned conductor layer;
And configuring the switch to be closed during operation such that the gate is connected to the voltage supply circuit through the switch. delete The method of claim 17, wherein the step of forming the antenna effect discharge circuit,
Forming a p-channel field effect transistor having a gate, an n-type channel well, and a source and a drain in the n-type channel well on the device substrate;
Forming an n-channel field effect transistor having a gate, a p-type channel well, and a source and a drain in the p-type channel well on the device substrate;
Forming a first capacitor having a first terminal in the device substrate or connected to the device substrate and a second terminal connected to the gate of the p-channel field effect transistor;
Forming a second capacitor having a first terminal in the device substrate or connected to the device substrate and a second terminal connected to the gate of the n-channel field effect transistor;
Connecting one of the source and drain of the p-channel field effect transistor to the node using a patterned conductor, and the other of the source and drain of the p-channel field effect transistor to the device substrate; And
And connecting one of the source and the drain of the n-channel field effect transistor to the node using a patterned conductor, and connecting the other of the source and drain of the n-channel field effect transistor to the device substrate. A method of manufacturing an integrated circuit device, characterized in that. The method of claim 19, wherein the step of providing the voltage supply circuit,
Connected to a gate of the p-channel field effect transistor via a first patterned conductor in the upper layer to turn off the p-channel field effect transistor during operation; And providing a voltage supply circuit connected to a gate of the n-channel field effect transistor via a second patterned conductor in the upper layer to turn off the n-channel field effect transistor during operation. Method for manufacturing an integrated circuit device. 21. The method of claim 20, further comprising forming a first switch on the device having a first terminal connected to the first patterned conductor in the upper layer and a second terminal connected to the voltage supply circuit. Wherein the first switch is configured to close during operation;
Forming a second switch on the device having a first terminal connected to the second patterned conductor in the upper layer and a second terminal connected to a second voltage supply circuit, the second switch A method of manufacturing an integrated circuit device, wherein the switch is configured to be closed during operation.

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