KR102132394B1 - Memory device and encoding method thereof - Google Patents

Abstract

The present invention relates to a memory device, and more particularly, to a memory device including variable resistance memory cells. A memory device according to an embodiment of the present application includes a memory module including at least one charge pump; And a controller that controls the memory module, wherein the controller uses a hash to shuffle logic to generate a plurality of data candidates corresponding to write-requested data; A calculator configured to calculate the number of bit flips and power consumption for each of the plurality of data candidates based on a result of comparing the data stored in the memory module with the plurality of data candidates; And a candidate selector for selecting data to be stored in the memory module among the plurality of data candidates, based on the number of bit flips and the peak power consumption. A memory device according to an embodiment of the present application may have improved write performance and memory life.

Description

Memory device and encoding method of the memory device {MEMORY DEVICE AND ENCODING METHOD THEREOF}

The present invention relates to a memory device, and more particularly, to a memory device including variable resistance memory cells.

A semiconductor memory device is a storage device that stores data and can be read out when necessary. 2. Description of the Related Art Semiconductor memory devices are largely divided into volatile memory devices and nonvolatile mmory devices.

The volatile memory device is a memory device in which stored data is lost when power supply is cut off. Volatile memory devices include SRAM, DRAM, and SDRAM. The nonvolatile memory device is a memory device in which stored data does not disappear even when the power supply is cut off. Nonvolatile memory devices include ROM, PROM, EPROM, EEPROM, flash memory devices, PRAM, MRAM, RRAM, and FRAM.

An object of the present application is to provide a memory device capable of extending memory life while improving write performance and a method of operating the same.

A memory device according to an embodiment of the present application includes a memory module including at least one charge pump; And a controller that controls the memory module, wherein the controller uses a hash to shuffle logic to generate a plurality of data candidates corresponding to write-requested data; A calculator configured to calculate the number of bit flips and the peak power consumption for each of the plurality of data candidates, based on a comparison result of the data stored in the memory module and the plurality of data candidates; And a candidate selector for selecting data to be stored in the memory module among the plurality of data candidates, based on the number of bit flips and the peak power consumption.

In an embodiment, the shuffling logic generates the plurality of data candidates based on a bit position of the write-requested data and a logical operation result for the hash.

In an exemplary embodiment, the calculation unit may include a bit flip calculation unit calculating a number of bit flips based on a result of comparing the data stored in the memory module and the plurality of data candidates; And a peak power calculator for calculating peak power consumption for each of the plurality of data candidates based on the bit flip information.

In an embodiment, the memory module may include a plurality of chips; And a plurality of charge pumps corresponding to the plurality of chips, wherein the peak power calculation unit calculates power consumption for each of the plurality of chips, and the peak power consumption is the highest of the power consumption for each of the plurality of chips. It is a large power consumption.

In an embodiment, the memory module may include a plurality of chips; And a charge pump for supplying power to the plurality of chips, and the peak power calculator calculates the peak power consumption by summing the power consumption consumed by all of the plurality of chips.

In an embodiment, the candidate selector selects at least one data candidate among the plurality of data candidates based on the bit flip information.

In an embodiment, the candidate selector selects a data candidate having a minimum number of bit flips and a data candidate having a predetermined number of bit flips than a data candidate having the minimum number of bit flips among the plurality of data candidates.

In an embodiment, the candidate selector selects data to be stored in the memory module among the at least one data candidate based on the peak power consumption information.

In an embodiment, the candidate selector selects a data candidate having a smallest peak power consumption among the at least one data candidate as data to be stored in the memory module.

In an embodiment, the memory module includes phase change memory cells.

An encoding method of a memory device according to an embodiment of the present application may include generating a plurality of data candidates corresponding to data requested to be written using a hash; Calculating the number of bit flips and the peak power consumption for each of the plurality of data candidates, based on a result of comparing the data stored in memory cells in which write request data is to be stored and the plurality of data candidates; Selecting at least one data candidate among the plurality of data candidates based on the number of bit flips; And data to be written from among the at least one data candidate, based on the peak power consumption.

A memory device according to an embodiment of the present application may have improved write performance and memory life.

1 is a block diagram illustrating a memory device according to an embodiment of the present application.
FIG. 2 is a diagram showing a current level during a reset and set operation of a memory cell of the memory device of FIG. 1.
3 and 4 are diagrams for explaining the structure and operation of the shuffling logic of FIG. 1.
5 is a view for explaining the operation of the memory device of FIG. 1 in more detail.
FIG. 6 is a diagram illustrating an example of a method for determining an intermediate encoding candidate of the memory device of FIG. 1.
7 is a flowchart illustrating the operation of the memory device illustrated in FIGS. 1 to 6 in more detail.
8 is a block diagram illustrating a memory device according to another embodiment of the present application.
9 is a view for explaining the operation of the memory device of FIG. 8.
10 is a flowchart for explaining the operation of the memory device described in FIGS. 8 and 9 in more detail.

Hereinafter, the technical spirit of the present application will be described with reference to the accompanying drawings in order to explain in detail such that a person skilled in the art of the present application can easily understand the technical spirit of the present application.

1 is a block diagram illustrating a memory device 10 according to an embodiment of the present application. Referring to FIG. 1, the memory device 10 includes a memory module 100 and a memory controller 200.

The memory module 100 stores the write-requested data in response to the write request of the memory controller 200. The memory module 100 reads the read request data in response to the read request of the memory controller 200. The memory module 100 includes a plurality of chips 111-11N.

Each of the plurality of chips 111 to 11N includes at least one bank BANK 1 to BANK M. Each bank contains memory cells for storing data. For example, each bank may include a plurality of phase change memory cells. However, this is an example, and if the resistance can be varied, the type of memory cells included in each bank is not particularly limited.

The plurality of chips 111-11N may each include charge pumps 121-12N providing necessary power. For example, the first chip 111 includes a first charge pump 121, and the first charge pump 121 provides power required for a read and/or write operation to the first chip 111. Can. Likewise, the second to Nth charge pumps 122 to 12N may provide power required for driving the second to Nth chips 112 to 11N, respectively.

The memory controller 200 controls the overall operation of the memory device 10. For example, when a read operation is performed, the memory controller 200 will control the memory device 10 so that data requested to be read is read from the memory module 100. As another example, when a write operation is performed, the memory controller 200 will control the memory device 10 so that the write requested data is stored in the memory module 100.

In an embodiment according to the technical idea of the present application, the memory controller 200 generates a plurality of encoding candidates by shuffling the write-requested data, and corresponds to the number based on the number of bit flips and peak power consumption A write operation is performed by selecting an optimal encoding candidate among a plurality of encoding candidates. As described above, the write operation is performed by selecting the optimal encoding candidate based on the number of bit flips and the peak power consumption, thereby improving the write performance and extending the life of the memory.

In more detail, as shown in FIG. 1, in the case of the memory device 10 having a power budget limitation for each chip, a charge pump is provided for each chip to provide a voltage required for a write operation. And power. However, in the case of a variable change memory, the amount of power required to perform the write operation is large, and accordingly, the number of write requests that can be simultaneously performed within the power budget is limited.

Meanwhile, when a phase change memory is used as memory cells, a required power consumption amount may vary according to data stored in the memory cell. For example, as shown in FIG. 2, the amount of power consumed to reset the data of the phase change memory from "1" to "0" is to set the data from "0" to "1". It may be greater than the amount of power consumed. Thus, the power consumption required when performing the write operation on the data "0" and the strategy consumption required when performing the write operation on the data "1" may be referred to as "write asymmetry".

The memory device 10 according to an embodiment of the inventive concept may increase the number of write requests that can be simultaneously performed within a power budget by reducing the peak power consumption per write request in consideration of such write asymmetry. have. Moreover, the memory device 10 according to the technical spirit of the present application can improve the life of the memory by reducing the number of bit flips of data requested to be written and previously stored data.

To this end, the memory controller 200 according to an embodiment of the technical spirit of the present application includes a shuffling logic 210, a calculation unit 220, and a candidate selection unit 230.

The shuffling logic 210 generates encoding candidates by shuffling the write-requested data with a hash. For example, the shuffling logic 210 may perform an XOR operation with a hash candidate on each bit position of the write-requested data, and determine the result as a new bit position of the shuffled data. In this case, data changed by the new bit position is referred to as a "data candidate", and a hash corresponding to the data candidate may be referred to as a "hash candidate." In addition, data candidates and hash candidates may be collectively referred to as “encoding candidates”. The structure and operation of the shuffling logic 210 will be described in more detail in FIGS. 3 and 4 below.

The calculation unit 220 receives encoding candidates corresponding to data requested to be written from the shuffling logic 210. In addition, the calculator 220 stores existing data (hereinafter referred to as "group input data") stored in memory cells in which the data requested to be written is stored, and a hash corresponding to the corresponding group input data (hereinafter, "group input hash"). Receive information about.

The calculation unit 220 calculates the number of bit flips and peak power consumption by comparing data candidates and hash candidates with pre-input data and pre-input hash information. To this end, the calculator 220 includes a bit flip calculator 221 and a peak power calculator 222.

The bit flip calculator 221 calculates the number of bit flips by comparing data candidates and hash candidates with pre-input data and pre-input hash information. For example, assume that the group input data is "1101" and the corresponding group input hash is "00". And suppose that the data candidate of the encoding candidate is "0001", and the corresponding hash (hereinafter, "hash candidate") is "00". In this case, since the previously input data is changed from "1101" to "0001", and the hash is not changed to "00", the bit flip calculator 221 will calculate the number of bit flips to "2".

The peak power calculator 222 calculates a peak power consumption required for each of the plurality of encoding candidates based on the bit flip information. For example, the peak power calculator 222 takes into account that the write asymmetry, that is, the consumption required when the write operation for the data “0” is performed and the write operation for the data “1” is different, The peak power consumption required for each of the plurality of encoding candidates will be calculated.

The candidate selector 230 receives bit flip information for each encoding candidate from the bit flip calculator 221, and receives peak power information for each encoding candidate from the peak power calculator 222. The candidate selector 230 selects an encoding candidate to which a write operation is finally performed among a plurality of encoding posterior parts based on bit flip information and peak power information.

For example, the candidate selector 230 may first select at least one encoding candidate among a plurality of encoding candidates based on the bit flip information. For example, the candidate selector 230 may select encoding candidates having a minimum number of bit flips and encoding candidates having a bit number of bit flips slightly greater than the minimum number of pit Philips as intermediate encoding candidates. Thereafter, the candidate selector 230 may select an encoding candidate having the lowest power consumption among the intermediate encoding candidates as an encoding candidate to which a write operation is finally performed.

In this case, the finally selected encoding candidate has a small number of bit flips as well as a small peak power consumption. Thus, the life of the memory is extended, and as many write operations as possible can be performed simultaneously within the power budget.

3 and 4 are diagrams for explaining the structure and operation of the shuffling logic 210 of FIG. 1.

Referring to FIGS. 3 and 4, the shuffling logic 210 may generate a data candidate by performing an XOR operation with a hash candidate on the data requested to be written.

In more detail, it is assumed that the data requested to be written is “0001”. In addition, it is assumed that the bit positions b0 to b3 of the write-requested data "0001" are "00", "01", "10", and "11", respectively. Also, it is assumed that the hash candidate is "01".

In this case, a new bit position is first determined by performing an XOR operation on each bit position and hash candidate of the write-requested data. For example, among the original bit positions of the data requested to be written, the first bit position (b0) is the second bit position (b1), and the second bit position (b1) is the first bit position (b0). ), the third bit position b2 is changed to the fourth bit position b3, and the fourth bit position b3 is changed to the third bit position b2, respectively. In addition, bit data is also changed according to the changed bit position, and a data candidate of “0010” is generated.

5 is a diagram for explaining the operation of the memory device 10 of FIG. 1 in more detail.

For convenience of description, it is assumed that the data requested to be written is “0001”. Also, it is assumed that the pre-input data of the memory cell in which the write-requested data will be stored is "1101", and the pre-input hash corresponding to the pre-input data is "00". Also, it is assumed that two bits of data are stored in one chip. In addition, it will be assumed that 480 microwatts of power is consumed when the write operation for the data “0” is performed, and 90 microwatts of power are consumed when the write operation for the data “1” is performed.

Referring to FIG. 5, the shuffling logic 210 shuffles the write-requested data and hash candidates to generate encoding candidates. In this case, hash candidates may be determined in consideration of the bit width of the data requested to be written. For example, when the data requested to be written is L bits, the hash candidate may be determined as "0~(L-1)". That is, as illustrated in FIG. 5, when the data requested to be written is “4” bits, hash candidate candidates may be “0 to 3”, and accordingly, hash candidates are “00”, “01”, and “10”, respectively. "11".

For example, when the hash candidate is "00", the shuffling logic 210 logically combines the hash candidate of "00" with the data of "0001" requested to be written, so that the first encoding whose data candidate is "0001" It will generate a candidate (Encoding Candidate 1). In this case, since each chip stores two bits of data, "00" of the data of "0001" corresponds to the first chip (chip 1), and "01" corresponds to the second chip, The hash candidate “00” will correspond to the third chip (chip 3).

Similarly, when the hash candidate is "01", the shuffling logic 210 will generate a second encoding candidate (Data Encoding Candidate 2) of "0010". In addition, when the hash candidate is "10", the shuffling logic 210 generates a third encoding candidate of "0100" as the data candidate, and shuffling logic when the hash candidate is "11". In step 210, a fourth encoding candidate with a data candidate of “1000” (Encoding Candidate 4) will be generated.

Thereafter, the calculator 220 will calculate the number of bit flips and the peak power consumption for each of the plurality of encoding candidates.

More specifically, the bit flip calculator 221 will calculate the number of bit flips by comparing the data candidate of the encoding candidate with the pre-input data and comparing the hash candidate of the encoding candidate with the pre-input hash.

For example, in the case of the first encoding candidate, the first data candidate and the first hash candidate are "0001" and "00", respectively, and the previously input data and the previously input hash are "1101" and "00", respectively. Therefore, in this case, the bit flip calculator 221 will calculate the number of bit flips as "2". Similarly, in the case of the second encoding candidate, the number of bit flips is calculated as "5", in the case of the third encoding candidate, the number of bit flips is calculated as "3", and in the case of the fourth encoding candidate, the number of bit flips is The number will be counted as "4".

Also, the peak power calculator 222 may calculate per-chip peak power consumption based on bit flip information.

For example, in the case of the first encoding candidate, two bits corresponding to the first chip (chip 1) are flipped, and both bits correspond to “0”. In this case, since the power required for the write operation for the data "0" is 480 microwatts, the peak power consumption per chip of the first encoding candidate is calculated as 960 microwatts.

In addition, in the case of the second encoding candidate, both bits corresponding to the first chip are flipped to "0", and the two bits corresponding to the second chip are "1" and "0," respectively. ", and one bit corresponding to the third chip is flipped to "1". In this case, since the power required for the write operation for the data "0" is 480 microwatts, and the power required for the write operation for the data "1" is 90 microwatts, the first chip (chip 1) has 960 microwatts are required, the second chip (chip 2) requires 560 microwatts, and the third chip (chip 3) requires 90 microwatts. In this case, the peak power calculator 222 calculates the peak power consumption per chip of the second encoding candidate as 960 micros.

Similarly, peak power consumption per chip of the third encoding candidate and the fourth encoding candidate will be calculated as 480 microwatts and 480 microwatts, respectively.

The candidate selector 230 selects an encoding candidate to which the write operation is finally performed, based on the number of bit flips and the peak power consumption.

In more detail, the candidate selector 230 first selects encoding candidates having the minimum number of bit flips and encoding candidates having a greater number of bit flips as intermediate encoding candidates.

For example, if the encoding candidate having the minimum number of bit flips and the encoding candidate having the number of one or more bit flips are selected as intermediate encoding candidates, the candidate selector 230 has the number of bit flips of "2". The first encoding candidate and the third encoding candidate having a bit flip number of "3" are selected as intermediate encoding candidates.

Thereafter, the candidate selector 230 selects the encoding candidate having the lowest peak power consumption among the intermediate encoding candidates as the encoding candidate to which the write operation is finally performed.

For example, since the peak power consumption of the first encoding candidate is 960 microwatts and the peak power consumption of the third encoding candidate is 480 microwatts, the candidate selector 230 finally writes the third encoding candidate. It will select the encoding candidate to be performed.

As described above, the memory device 10 according to an embodiment of the present application generates a plurality of encoding candidates corresponding to the data requested to be written, and considers the peak power consumption per chip and the number of bit flips, thereby encoding the plurality of encoding candidates. Among them, an encoding candidate to which a write operation is finally performed is selected. Accordingly, the memory device 10 according to an embodiment of the present application may not only improve the memory life, but also improve the write performance.

Meanwhile, it will be understood that the above-described description is illustrative, and the technical spirit of the present application is not limited thereto. For example, in FIG. 5, it has been described that when determining an intermediate encoding candidate, one or N more encoding candidates than the minimum number of bit flips are determined as intermediate encoding candidates. However, it will be understood that this is an example, and a method of finding an intermediate encoding candidate may be changed by a designer. For example, when determining an intermediate encoding candidate, an encoding candidate having a number of bit flips that is 2 or N times less than the minimum number of bit flips may be determined as an intermediate encoding candidate.

In addition, in FIGS. 1 to 5, when selecting an encoding candidate to be finally written, it has been described as selecting at least two encoding candidates (that is, intermediate encoding candidates) among encoding candidates in consideration of the number of bit flips. However, this is exemplary, and according to a method of setting an intermediate encoding candidate, only one encoding candidate may be selected as the intermediate encoding candidate. This will be explained in more detail in FIG. 6 below.

6 is a diagram for explaining an example of a method for determining an intermediate encoding candidate of the memory device 10 of FIG. 1.

For convenience of description, it is assumed that the data requested to be written is “00111001”, and the pre-input data and pre-input hash are “00000110” and “001”, respectively.

Referring to FIG. 6, since the data requested to be written is 8 bits, 8 hash candidates are generated. Thereafter, eight encoding candidates (Candidate 0 to Candidate 7) are formed by a logical operation between a bit position of the data requested to be written and a hash candidate. At this time, the minimum number of bit flips is calculated as "2".

In this case, a method of finding an encoding candidate having a number of bit flips larger than the minimum number of bit flips and determining the intermediate encoding candidate may be variously set by a designer.

For example, an encoding candidate having one or X number of bit flips than the minimum number of bit flips may be determined as an intermediate encoding candidate (hereinafter, "+X technique").

In the case of "+X technique", if X is "1", there is no more one bit flip than the minimum bit flip "2", so only one encoding candidate (candidate 1) will be determined as the intermediate encoding candidate. As another example, if X is "2", as an intermediate encoding candidate, an encoding candidate (candidate 1) having a bit flip number of "2" and an encoding candidate (candidate 2) having a bit flip number of "4" are intermediate encoding. It will be decided as a candidate.

As another example, an encoding candidate having a bit flip that is 2nd or Yth less than the minimum number of bit flips may be determined as an intermediate encoding candidate (hereinafter, "+Yth technique").

In the case of "+Yth technique", if Y is "2", the encoding candidate having the minimum number of bit flips (candidate 1) and the encoding candidate having the second least number of bit flips (candidate 2) are the intermediate encoding candidates. Can be determined.

As described above, in the case of the "+X technique", there may not be an encoding candidate having the number of bit flips of +X depending on the value of X, but in the case of the "+Yth technique", the encoding candidate having the Y-th small bit flip It always exists.

7 is a flow chart for explaining the operation of the memory device 10 described in FIGS. 1 to 6 in more detail.

In step S110, the shuffling logic 210 generates a plurality of encoding candidates by performing a shuffling operation on the data requested to be written using the hash.

In step S120, the calculator 220 calculates the number of bit flips for each of the plurality of encoding candidates and the peak power consumption per chip.

In step S130, the selector 230 finds an encoding candidate having a bit more than the minimum number of bit flips. At this time, the encoding candidate having the minimum number of bit flips and the encoding candidate having a bit more than the minimum number of bit flips are determined as intermediate encoding candidates.

In step S140, the selector 230 selects an intermediate encoding candidate having a minimum peak power consumption among the intermediate encoding candidates as an encoding candidate to which a write operation is finally performed.

Meanwhile, it will be understood that the above-described description is illustrative, and the technical spirit of the present application is not limited thereto. For example, in FIGS. 1 to 7, a charge pump corresponding to each chip is provided, and thus it has been described that the power budget for each daughter chip is limited. However, this is exemplary, and a memory module may be implemented so that a plurality of chips share one charge pump. This will be described in more detail with reference to FIGS. 8 to 10 below.

8 is a block diagram illustrating a memory device 20 according to another embodiment of the present application. The memory device 20 of FIG. 8 is similar to the memory device 10 of FIG. 1. Therefore, identical or similar components are indicated using the same or similar reference numerals, and overlapping descriptions will be omitted below for a brief description.

Referring to FIG. 8, the memory device 20 includes a memory module 300 and a memory controller 400. The memory module 300 includes a plurality of chips 311 to 31N and a charge pump 320 that supplies power to the plurality of chips 311 to 31N. The memory controller 400 includes a shuffling logic 410, a calculation unit 420, and a candidate selection unit 430.

Unlike the memory device 20 of FIGS. 1 to 7, the memory module 300 of the memory device 20 of FIG. 8 uses one charge pump 320 that supplies power to a plurality of chips 311-31N. To be equipped. Therefore, the power budget of the memory device 20 is limited for each memory module.

Accordingly, the peak power calculator 422 of the memory controller 400 calculates the power consumption for each encoding candidate, and the candidate selector 430 finally determines the encoding candidate having the lowest power consumption among the plurality of encoding candidates. It is selected as an encoding candidate for which a write operation is performed.

9 is a diagram for explaining the operation of the memory device 20 of FIG. 8. The operation of the memory device 20 of FIG. 9 is similar to that of the memory device 10 of FIG. 5. Therefore, the same or similar elements are indicated using the same or similar reference numbers, and duplicate descriptions will be omitted for the sake of brevity.

Referring to FIG. 9, the shuffling logic 410 generates a plurality of encoding candidates (Encoding candidate 1 to Encoding candidate 4) by using the write request data and hash candidates.

The bit flip calculator 421 calculates the number of bit flips by comparing each of the plurality of encoding candidates with pre-input data and pre-input hash.

The peak power calculator 422 calculates power consumption for each of the plurality of encoding candidates.

For example, in the case of the first encoding candidate (Encoding Candidate 1), two bits are flipped, and both bits correspond to “0”. In this case, since the power required for the write operation for the data "0" is 480 microwatts, the power consumption of the first encoding candidate is calculated as 960 microwatts.

In addition, in the case of the second encoding candidate, five bits are flipped, three of which are flipped to "0" and two bits are flipped to "1". In this case, since the power required for the write operation for the data "0" is 480 microwatts, and the power required for the write operation for the data "1" is 90 microwatts, the peak power calculator 422 The power consumption of the second encoding candidate is calculated as 1620 microwatts.

Similarly, the power consumption of the third encoding candidate and the fourth encoding candidate will be calculated to be 1050 microwatts and 1140 microwatts, respectively.

Thereafter, the candidate selector 430 selects an encoding candidate to which the write operation is finally performed, based on the number of bit flips and power consumption.

For example, the candidate selector 430 selects the first encoding candidate having the minimum number of bit flips and the third encoding candidate having the number of one or more bit flips as intermediate encoding candidates, of which the power consumption is The smallest first encoding candidate will be finally selected as an encoding candidate for which a write operation will be performed.

10 is a flowchart for explaining the operation of the memory device 20 described in FIGS. 8 and 9 in more detail.

In step S210, the shuffling logic 410 generates a plurality of encoding candidates by performing a shuffling operation on the data requested to be written using the hash.

In step S220, the calculator 420 calculates the number of bit flips and power consumption for each of the plurality of encoding candidates.

In step S230, the selector 430 finds an encoding candidate having a bit more than the minimum number of bit flips. At this time, the encoding candidate having the minimum number of bit flips and the encoding candidate having a bit more than the minimum number of bit flips are determined as intermediate encoding candidates.

In step S240, the selector 430 selects an intermediate encoding candidate having the lowest power consumption among the intermediate encoding candidates as an encoding candidate to which a write operation is finally performed.

On the other hand, it is obvious to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or technical spirit of the present invention. In view of the foregoing, if the modifications and variations of the present invention fall within the scope of the following claims and equivalents, the present invention is considered to include the modifications and modifications of the present invention.

10, 20: memory device
100, 300: memory module
200, 400: memory controller
111, 112, 11N, 311, 312, 31N: Chip
210, 410: shuffling logic
220, 420: calculator
230, 430: candidate selection unit

Claims (16)

A memory module including at least one charge pump; And
It includes a controller for controlling the memory module,
The controller
Shuffling logic to generate a plurality of data candidates corresponding to the write-requested data using the hash candidates;
A calculator configured to calculate the number of bit flips and the peak power consumption for each of the plurality of data candidates based on a comparison result of the data stored in the memory module and the plurality of data candidates; And
And a candidate selector for selecting data to be stored in the memory module among the plurality of data candidates, based on the number of bit flips and the peak power consumption.
The candidate selector selects a first data candidate having the minimum number of bit flips and a second data candidate having the second least number of bit flips among the plurality of data candidates,
The candidate selector selects a data candidate having the lowest peak power consumption among the first and second data candidates as data to be stored in the memory module,
The at least one charge pump provides the peak power consumption differently according to write asymmetry of the phase change memory cells of the memory module. According to claim 1,
And the shuffling logic generates the plurality of data candidates based on a bit position of the write-requested data and a logical operation result for the hash. According to claim 1,
The calculation unit
A bit flip calculator for calculating the number of bit flips based on a comparison result between data stored in the memory module and the plurality of data candidates; And
And a peak power calculator configured to calculate the peak power consumption for each of the plurality of data candidates based on the information about the bit flip. According to claim 3,
The memory module
A plurality of chips; And
It includes a plurality of charge pumps corresponding to the plurality of chips,
The peak power calculator calculates power consumption for each of the plurality of chips, and the peak power consumption is the largest power consumption among power consumption for each of the plurality of chips. According to claim 3,
The memory module
A plurality of chips; And
It includes a charge pump for supplying power to the plurality of chips,
The peak power calculation unit calculates the peak power consumption by summing up the power consumption consumed in all of the plurality of chips. delete delete delete delete delete Generating a plurality of data candidates corresponding to the data requested to be written using the hash;
Calculating the number of bit flips and the peak power consumption for each of the plurality of data candidates based on a result of comparing the data stored in memory cells in which the write-requested data is to be stored and the plurality of data candidates;
Selecting a first data candidate having a minimum number of bit flips and a second data candidate having a second least number of bit flips among the plurality of data candidates; And
And selecting a data candidate having a smallest peak power consumption among the first and second data candidates as data to be written.
The peak power consumption is provided differently through at least one charge pump according to the write asymmetry of the phase change memory cells of the memory module, the encoding method of the memory device. The method of claim 11,
The plurality of data candidates are generated based on a bit position of the write-requested data and a logical operation result for the hash. The method of claim 11,
The write-requested data is distributed and stored in each of a plurality of chips,
The peak power consumption is the largest power consumption among the power consumption in each of the plurality of chips, the encoding method of the memory device. The method of claim 11,
The write-requested data is distributed and stored in each of a plurality of chips,
The peak power consumption is a sum of power consumption consumed in each of the plurality of chips, the encoding method of the memory device. delete delete

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