KR102113245B1 - Semiconductor device with epitaxial source/drain - Google Patents

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from the substrate, and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and sidewall spacers formed along sidewalls of the gate electrode. In some cases, a U-shaped recess is in the fin and adjacent the gate structure. A first source / drain layer is conformally formed on the surface of the U-shaped recess, and the first source / drain layer extends at least partially below the adjacent gate structure. A second source / drain layer is formed on the first source / drain layer. At least one of the first source / drain layer and the second source / drain layer comprises silicon arsenic (SiAs).

Description

Semiconductor device with epitaxial source / drain {SEMICONDUCTOR DEVICE WITH EPITAXIAL SOURCE / DRAIN}

This application is a continuation of part of U.S. Patent Application No. 14 / 987,509 filed on January 4, 2016 under the name " semiconductor device with epitaxial source / drain, " Is included in.

As the semiconductor industry advances to nanometer technology process nodes to pursue higher device densities, higher performance, and lower costs, challenges from both manufacturing and design challenges are pin field effect transistors (fin field). effect transistors (FinFETs). FinFET devices generally include semiconductor fins in which channel and source / drain regions of semiconductor transistor devices are formed and have high aspect ratios. To produce faster, more reliable, and better controlled semiconductor transistor devices, gates are formed along the sides of the fin structure and over the fin structure (eg surrounding the fin structure) to channel and source / drain regions Take advantage of their increased surface area. In some devices, source / drain of a FinFET using, for example, silicon germanium (SiGe), silicon phosphide (SiP) or silicon carbide (SiC) to improve carrier mobility ( Strained materials in source / drain (S / D) parts can be used.

The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.
1-5 illustrate an exemplary process for manufacturing a semiconductor device according to one embodiment of the present disclosure.
6 and 7 illustrate another process for manufacturing a semiconductor device.
8-10 show additional operations of an exemplary process for manufacturing a semiconductor device according to an embodiment of the present disclosure.
11 to 16 illustrate exemplary processes for manufacturing a semiconductor device according to another exemplary embodiment of the present disclosure.
17 and 18 show a semiconductor device according to another exemplary embodiment according to the present disclosure.
19 and 20 show a semiconductor device according to another exemplary embodiment according to the present disclosure.

It will be understood that the following disclosure provides a number of different embodiments or examples for implementing the different features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples, and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and / or desired properties of the device. Further, in the following description, the formation of the first feature over or on the second feature may include embodiments in which the first and second features are formed by direct contact, and also the first and second features. Additional features may include embodiments that may be formed intervening in the first and second features so that they do not directly contact. Various features can be arbitrarily shown at different scales for simplicity and clarity.

Also, spatial relative terms such as "below", "below", "below", "above", "above", etc., as illustrated in the figures, refer to other element (s) or feature (s). It can be used herein for ease of description to describe the relationship of one element or feature. Spatial relative terms are intended to cover different orientations of the device in use or in operation, in addition to the orientation shown in the figures. The device can be otherwise oriented (rotated in 90 ° or other orientation), and the spatial relative descriptors used herein can be interpreted similarly accordingly. Additionally, the term “manufactured” may mean either “comprising” or “consisting of”.

Various embodiments of the present disclosure relate to semiconductor devices and methods of forming the same. In various embodiments, the semiconductor device includes FinFET transistors. FinFET transistors are field effect transistors formed on fin structures formed on a substrate. In some embodiments, the pins are formed as an array.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming a fin structure including one or more fins 12 on a semiconductor substrate 10 as shown in FIG. 1. In one embodiment, the semiconductor substrate 10 is a silicon substrate. Alternatively, the semiconductor substrate 10 may include germanium, silicon germanium, gallium arsenide or other suitable semiconductor materials. Also alternatively, the semiconductor substrate may include an epitaxial layer. For example, a semiconductor substrate can have an epitaxial layer over a bulk semiconductor. In addition, the semiconductor substrate can be strained to increase performance. For example, the epitaxial layer may include a semiconductor material different from that of the bulk semiconductor, such as a silicon germanium layer over bulk silicon or a silicon layer over bulk silicon germanium. Such strained substrates can be formed by selective epitaxial growth (SEG). In addition, the semiconductor substrate may include a semiconductor-on-insulator (SOI) substrate. Also alternatively, the semiconductor substrate may include a buried dielectric layer, such as a buried oxide (BOX) layer formed by separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or other suitable method. . In other embodiments, the substrate is a group IV-IV compound semiconductors such as SiC and SiGe, GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP Compound semiconductors containing the same group III-V compound semiconductors; Or combinations thereof. In some embodiments, the semiconductor substrate 10 is, for example, a p-type silicon substrate having an impurity concentration within a range of about 1x10 ¹⁵ cm ^-3 to about 2x10 ¹⁵ cm ^-3 . In other embodiments, the semiconductor substrate 10 is an n-type silicon substrate having an impurity concentration in the range of about 1x10 ¹⁵ cm ^-3 to about 2x10 ¹⁵ cm ^-3 .

The pins 12 are disposed on the semiconductor substrate 10, and the pins 12 can be made of the same material as the semiconductor substrate 10 and can be continuously extended from the semiconductor substrate 10. The fins 12 may be formed by selectively etching the semiconductor substrate 10. Alternatively, the pins 12 can be formed using the EPI first method. In EPI first methods, an epitaxial layer is formed on the semiconductor substrate 10, and then the epitaxial layer is subsequently patterned to form fins 12.

A photolithography process can be used to define the fins 12 on the semiconductor substrate 10. In some embodiments, a hardmask layer is formed on the semiconductor substrate 10. The hard mask layer may include a bilayer of SiN and SiO ₂ . The photoresist layer is spin-on coated on a semiconductor substrate. The photoresist is patterned by selective exposure of the photoresist to actinic radiation. In general, patterning includes photoresist coating (e.g. spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g. hard baking), Other suitable processes, or combinations thereof. Alternatively, the photolithography exposure process can be applied to other suitable methods, such as maskless photolithography, electron beam writing, direct writing, ion beam writing, and / or nano-imprinting. Or are replaced by these.

Subsequently, the pattern of the photoresist layer is transferred to the hardmask layer by etching the exposed area of the hardmask layer. Subsequently, a hardmask layer is used as a mask during the etching of the semiconductor substrate. The semiconductor substrate can be etched by a variety of methods including dry etching, wet etching, or a combination of dry etching and wet etching. Dry etching processes include fluorine-containing gas (e.g. CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ , and / or C ₄ F ₈ ), chlorine-containing gas (e.g. Cl ₂ , CHCl ₃ , CCl ₄ , and / or BCl ₃ ), bromine-containing gas (eg, HBr and / or CHBr ₃ ), oxygen-containing gas, iodine-containing gas, other suitable gases and / or plasmas, or combinations thereof You can implement them. The etch process may include etch selectivity, flexibility and multi-step etch to obtain the desired etch profile.

In some embodiments, the semiconductor device includes an insulating material formed over the semiconductor substrate 10 along the bottoms of the fins 12. The insulating material forms shallow trench isolation (STI) regions 14 between the plurality of fins in embodiments that include a plurality of fins. The STI regions 14 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. The STI regions 14 can be formed by any suitable process. As in one embodiment, STI regions 14 are formed by filling the region between fins with one or more dielectric materials using chemical vapor deposition (CVD). In some embodiments, the filled region can have a multi-layer structure, such as a layer of thermal oxide liner filled with silicon nitride or silicon oxide. After formation of the STI region, an annealing process may be performed. The annealing process includes rapid thermal annealing (RTA), laser annealing processes, or other suitable annealing processes.

In some embodiments, STI regions 14 are formed using flowable CVD. In flowable CVD, flowable dielectric materials are deposited instead of silicon oxide. Flowable dielectric materials, as their name suggests, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemicals are added to the silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, are silicates, siloxanes, methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), MSQ / HSQ, perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), And silyl-amines such as tetraethyl orthosilicate (TEOS) or trisilylamine (TSA). These flowable silicon oxide materials are formed in a number of operating processes. The flowable film is deposited and then cured and then annealed to remove unwanted element (s) to form silicon oxide. When the unwanted element (s) are removed, the flowable membrane is densified and shrinks. In some embodiments, multiple annealing processes are performed. The flowable membrane is cured and annealed at least once for a long period of time, such as for a total of 1 hour or more, at temperatures within the range of about 600 ° C to about 1200 ° C.

A chemical mechanical polishing (CMP) operation is performed to remove excess material from the STI region and provide a substantially planar surface. Subsequently, a dopant is injected into the fins to form n-wells and p-wells and the device is subsequently annealed. The STI region is etched back to remove a portion of the STI region and expose the upper portions of the fins where the gate structure and source / drain regions are subsequently formed. Formation of the gate structure can include additional deposition, patterning, and etching processes. STI removal is a semi-isotropic etch using HF + NH _{3 as} plasma or NF ₃ + NH ₃ as plasma; Or by an appropriate etching process such as isotropic etching such as diluted HF.

In some embodiments, one or more gate structures 16 are formed over fin structures as shown in FIG. 2. The gate structure formation process may include depositing the gate dielectric 20, depositing the gate electrode material, and patterning the deposited gate material into the gate electrodes 18. Subsequently, sidewall spacers 22 are formed on the gate electrodes 18. FIG. 3 is a cross-section taken along line A-A of FIG. 2 showing the arrangement of fins 12 and gate structure 16. FIG. 4 is a cross-section taken along line B-B of FIG. 2 showing the arrangement of gate structures 16 over second regions 36 of fin 12. The dotted lines on the fins 12 in Figure 4 and subsequent figures show the projection of the gate electrode surrounding the fins. In order to simplify the drawings in subsequent drawings, a gate dielectric layer under the gate electrodes is not shown.

The gate dielectric 20 can include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. In some embodiments, the gate electrode 18 may be formed of polysilicon and include a hardmask formed over the gate electrode. The hardmask can be made of a suitable hardmask material including SiO ₂ , SiN, or SiCN. The gate electrode structure may include additional layers such as interfacial layers, capping layers, diffusion / barrier layers, dielectric layers, conductive layers, other suitable layers, and combinations thereof. The gate electrode 18 is made of aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloy instead of polysilicon Any other suitable material, such as, other suitable materials, or combinations thereof.

In some embodiments, FinFET can be fabricated using a gate first method or a gate last method. In embodiments using a high-k dielectric and a metal gate (high-k (HK) / metal gate), a gate-last method is used to form the gate electrode. In the gate last method, a dummy gate is formed, a dummy gate is subsequently removed in a later operation after a high temperature annealing operation, and a high k dielectric and metal gate (HK / MG) is formed.

According to embodiments of the present disclosure, the high k gate dielectric 20 is HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide alumina (HfO ₂ -Al ₂ O ₃ ) alloy, Other suitable high k dielectric materials, or combinations thereof. The metal gate material may include one or more layers of Ti, TiN, titanium aluminum alloy, Al, AlN, Ta, TaN, TaC, TaCN, TaSi, and the like.

In some embodiments, sidewall spacers 22 are used to offset subsequently formed doped regions, such as source / drain regions. Sidewall spacers 22 can also be used to design or modify the source / drain region (junction) profile. Sidewall spacers 22 may be formed by suitable deposition and etching techniques, and may include silicon nitride, silicon carbide, silicon oxynitride, other suitable materials, or combinations thereof. In some embodiments, sidewall spacers include a plurality of layers. The plurality of layers may include an oxide layer having a nitride or carbide layer thereon.

Turning to Figure 5, the pin 12 is anisotropically etched in the first region 24 to form a U-shaped recess 26. The etching operation is performed using suitable conventional anisotropic etching techniques.

To improve the performance of the FinFET, it is desirable to place the source / drain regions adjacent to the channel region below the gate electrode. To form the source / drain regions close to the gate electrode, the recess is further etched to undercut sidewall spacers. In embodiments of the present disclosure, etching of the recess continues to undercut the gate electrode. As shown in FIG. 6, isotropic etching is performed to undercut at least a portion of the sidewall spacers 22. In some embodiments, the etching operation continues to further etch a portion of fin 12 under gate electrode 18. The isotropic etching operation is performed using suitable conventional isotropic etchants and suitable etching techniques that are selective for the fin material. However, isotropic etching creates an extended recess 60 with non-uniform boundaries as shown in FIG. 6.

As shown in FIG. 7, the recess 60 in which the source or drain regions 62 including the lightly doped region 64 and the highly doped region 66 are expanded Subsequently formed within. The source or drain regions 62 may be formed by suitable epitaxy technology. For example, in at least some existing processes, the hardened region 64 is formed by epitaxial deposition of semiconductor materials such as Si or SiGe for the PMOS region, and Si, SiC, or SiCP for the NMOS region. Can be formed. The doped region 66 may be formed by epitaxial deposition of semiconductor materials such as SiGe or Ge for the PMOS region and SiP or SiCP for the NMOS region. The semiconductor materials can be doped with a suitable amount of known dopants depending on the desired function of the semiconductor device.

In order to improve control over the semiconductor manufacturing process and control over semiconductor operating parameters, it is desirable to form the source and drain regions at substantially uniform intervals from the gate electrode. Substantially uniform spacing of the source and drain regions can be achieved by forming uniformly doped regions in the recess and then etching the doped regions according to various embodiments.

8, a uniformly doped region 28 is formed on the surface of the recess 26. The doped region 28 can be formed by injecting a dopant into the fin 12 to a substantially uniform depth. Dopant implantation of a substantially uniform depth can be achieved by conformally doping the surface of the recess 26. The doped region 28 may be a layer on the fin 12 in the surface of the recess 26, having a thickness of about 0.5 nm to about 10 nm. In some embodiments of the present disclosure, the doped region 28 is formed by plasma doping.

Plasma doping is performed in some embodiments with a plasma doping device equipped with an inductively coupled plasma (ICP) source. The temperature of the semiconductor wafer can be maintained below 40 ° C during the doping operation in some embodiments. The dopant material gas can be a suitable dopant gas comprising AsH ₃ or B ₂ H ₆ combined with an inert carrier gas such as He or Ar. The dopant gas mass concentration ranges from about 0.01 mass% to about 5 mass% based on the total gas concentration (dopant gas + carrier gas) in some embodiments. The gas flow rate during the plasma doping operation ranges from about 5 cm ³ / min to about 2000 cm ³ / min in some embodiments. The pressure of the plasma doping device during the doping operation ranges from about 0.05 Pa to about 10 Pa in some embodiments. Plasma may be generated with power in the range of about 100 W to about 2500 W in some embodiments.

The conformally doped region 28 on the surface of the fin 12 can be selectively etched against the undoped portion of the fin 12, thereby leaving the recess 26 under the gate structure 16. It extends evenly to a portion of the pin 12 in to form a substantially uniform extended U-shaped recess 70 as shown in FIG. 9. In some embodiments, the width of the U-shaped recess 70 is between about 10 nm and 40 nm. Selective etching of the doped region 28 can be performed using isotropic etching techniques. In some embodiments, a liquid etchant that is selective for the doped region 28 is used. Suitable liquid etchants include a mixture of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) (also known as SPM or piranha etching).

As shown in FIG. 10, source or drain regions 30 including a hard-doped region 32 and a highly-doped region 34 are subsequently formed in the extended recess 70 to form a semiconductor device ( 100). The source or drain regions 30 are formed with Si features, SiGe features, Ge features, SiAs features, SiP features, SiCP features, combinations thereof, or other suitable features crystalline on the fins. Preferably, it can be formed by one or more epitaxy or epitaxial (epi) processes. Epitaxy processes include CVD deposition techniques (eg, vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), atomic layer deposition ; ALD), molecular beam epitaxy, and / or other suitable processes.

For example, the hardly-doped region 32 may be formed by epitaxial deposition of semiconductor materials such as Si or SiGe for the PMOS region, and SiAs or SiP for the NMOS region. The doped region 34 may be formed by epitaxial deposition of semiconductor material, such as SiGe or Ge for the PMOS region, and SiP, SiCP, SiAs, or a combination for the NMOS region. The semiconductor materials can be doped with an appropriate amount of known dopants by ion implantation depending on the desired function of the semiconductor device.

The ion implantation can be an n-type dopant such as arsenic or phosphorus for the NMOS device, or a p-type dopant such as boron for the PMOS device. Infusion energies and dosages for doping range from about 10 keV to 60 keV and about ¹ × 10 ¹³ dopants / cm ² to 5 × 10 ¹⁴ dopants / cm ^2, respectively, for doping the hardened region 32 in some embodiments. to be. Infusion energies and dosages for doping range from about 10 keV to 80 keV and about 8x10 ¹⁴ dopants / cm ² to 2x10 ¹⁶ dopants / cm ² for doping the doped region 34 in some embodiments, respectively. to be. Doping of the source / drain regions 30 amorphizes the semiconductor, which must then be recrystallized to activate the source / drain regions 30. After ion implantation of the dopant, semiconductor devices are annealed, such as by rapid thermal / millisecond / laser annealing to recrystallize the source and drain regions 30. In some embodiments, a capping layer 35 may be formed over the highly doped region 34. As an example, the capping layer 35 may include a nitride layer, Si layer, SiP layer, SiC layer, or other suitable capping material. In some embodiments, the capping layer 35 may comprise a SiP layer having a P dopant concentration of about 0.1x10 ²⁰ atoms / cm ³ to 9x10 ²⁰ atoms / cm ^3.

As mentioned above, embodiments of the present disclosure can use SiAs to form one or both of the hard-doped region 32 and the highly-doped region 34 for NMOS devices. For example, in some cases, the hard-doped region 32 can be formed of SiAs, and the highly-doped region 34 can be formed of SiP, SiCP, or a combination thereof. In some embodiments, both the hard-doped region 32 and the heavily-doped region 34 can be formed of SiAs. In some embodiments, the hard-doped region 32 can be formed of SiP and the highly-doped region 34 can be formed of SiAs. In some cases, the hardly-doped region 32 may be formed of SiAs, and the highly-doped region 34 may be formed of SiAs, SiP, or a combination thereof.

Using SiAs to form source or drain regions 30 for NMOS devices is attractive for several reasons. For example, dopant activation in SiAs can be achieved using, for example, a lower thermal budget (eg, lower activation annealing temperature and / or time) compared to dopant activation in SiP. . In some cases, the thermal budget used to achieve dopant activation in SiAs can be about 15% to 20% lower than the thermal budget used to activate dopant in SiP. Additionally and in some embodiments, the hardened region 32 formed using SiAs may be thinner than the hardened region 32 formed using SiP. In some cases, the hardened region 32 formed using SiAs may be about 0.5 to 0.8 times the thickness of the hardened region 32 formed using SiP. In some embodiments, the hardened region 32 formed using SiAs may have a thickness 'T' equal to about 0.1 nm to 5 nm, as shown in FIG. 10. In some embodiments, the doped region 34 may have a width “W” equal to about 5 nm to 20 nm, as shown in FIG. 10. Given the thickness 'T' of the longitudinally doped region 32, the width 'W' of the highly doped region 34, and the width of the U-shaped recess described above, various ratios between these three geometries Can be specified. For example, a ratio between the thickness 'T' and the width 'W' may be defined, and a ratio between the thickness 'T' and the width of the U-shaped recess 70 may be defined, and the width 'W' and The ratio between the widths of the U-shaped recesses 70 can be defined. In at least some embodiments that use SiAs for the hardly-doped region 32, due to the thinner layer thickness T, subsequently deposited doped regions 34 are formed from channels (eg, gate electrodes ( 18) pin region below], thereby improving device performance. In addition, because of the thinner layer thickness of SiAs used for the hardened regions 32, subsequently deposited doped regions 34 can be further extended into the distance 'D' into the fins thereby improving device performance. Improve. Also, because arsenic is less diffuse than phosphorus, the source or drain regions 30 formed of SiAs will have sharper and sharper junctions than the source or drain regions 30 formed of SiP. In addition, less arsenic diffusion means that the source or drain regions 30 formed of SiAs will reduce dopant diffusion into the device channel region and thereby improve device performance.

For embodiments using SiAs for one or both of doped region 32 and doped region 34 (e.g., for NMOS devices), arsenic (As) dopant concentration (e.g. For example, the dosage) can be equal to about 1.2 to 1.5 times the phosphorus (P) dopant concentration (eg, in a device using SiP to form source or drain regions 30). For example, considering a device using SiP for the hard-doped region 32 and the highly-doped region 34, the P dopant concentration for the hard-doped region 32 is about 1x10 ²⁰ atoms / cm ³ To 8x10 ²⁰ atoms / cm ³ , and the P dopant concentration for the doped region 34 is about 8x10 ²⁰ atoms / cm ³ to 5x10 ²¹ atoms / cm ³ . Thus, in some embodiments, a device that uses SiAs for the hard-doped region 32 and / or the highly-doped region 34, about 1.2 × ^{10 20} atoms / cm for the hard-doped region 32 ³ to 1.2x10 As for the dopant concentration in the range of ²¹ atoms / cm ^3, and the high-doped regions 34 have a dopant concentration of As in the range of about 9.6x10 ²⁰ atoms / cm ³ to about 7.5x10 ²¹ atoms / cm ³ Can be.

11 illustrates another embodiment of forming a CMOS device. The CMOS device has a plurality of regions including an NMOS region and a PMOS region. The PMOS and NMOS regions are generally separated by STI regions. The insulating layer 38 is conformally formed on the gate electrode 18 and the first region 24 of the fin 12. The insulating layer is a nitride layer 38 in some embodiments. Since the same operations that go through the removal of the doped region are performed on both the NMOS and PMOS regions, the operations are only described for one region (NMOS or PMOS).

Turning to FIG. 12, the insulating layer 38 is etched anisotropically to expose the first region 24 of the fin 12, and the first region 24 of the fin 12 is etched anisotropically. The recess 26 is formed. The etching operation is performed using suitable conventional anisotropic etching techniques.

13, a uniformly doped region 28 is formed on the surface of the recess 26. The doped region 28 may be formed by plasma doping, which implants a dopant into the fin 12 at a substantially uniform depth, as described herein. A substantially uniform depth of dopant injection can be achieved by conformally doping the surface of the recess 26. 14, the conformally doped surface of a portion of the fin 12 lining the recess 26 can be selectively etched against the undoped portion of the fin 12, thereby An extended recess 70 is formed that extends evenly into a portion of the fin 12 under the gate structure 16 as described herein.

The NMOS and PMOS regions are formed independently of each other. For example, in order to form source or drain regions 40 that include a hardened region 42 and a heavily doped region 44 as shown in FIG. 15, semiconductor materials are used in the PMOS region 110. The NMOS region may be blocked (eg, by a blocking layer) while being epitaxially deposited in the extended recess 70 of. The source or drain regions 40 may be formed by ion implantation of a suitable amount of known dopants following an appropriate epitaxy technique depending on the desired function of the semiconductor device. In some embodiments, the semiconductor material deposited to form the hardened region 42 is Si or SiGe, and the semiconductor material deposited to form the heavily doped region 44 is SiGe or Ge.

After forming the PMOS region 110, in some embodiments, the blocking layer over the NMOS region 120 is removed, and semiconductor materials are expanded recesses 70 of the NMOS region 120, as shown in FIG. ), The PMOS region 110 is blocked (eg, by a blocking layer) while being epitaxially deposited. The NMOS region 120 includes source or drain regions 46 that include a lightly doped region 48 and a highly doped region 50. The source or drain regions 46 may be formed by ion implantation of a suitable amount of known dopants following an appropriate epitaxy technique depending on the desired function of the semiconductor device. In some embodiments, the semiconductor material that is deposited to form the hardened region 48 is SiAs or SiP, and the semiconductor material that is deposited to form the heavily doped region 50 is SiAs, SiP, SiCP, or combinations thereof. . The operations for forming the PMOS and NMOS regions are interchangeable. The source and drain may be first formed in the NMOS while blocking the PMOS region, and then the source and drain are subsequently formed in the PMOS region while blocking the NMOS region.

The exemplary semiconductor devices 100 described so far in the present disclosure are high voltage threshold (HVT) devices. In other embodiments of the present disclosure, a standard voltage threshold (SVT) device 200 and a low voltage threshold (LVT) device 300 are formed.

17 and 18, an SVT device 200 is formed in some embodiments of the present disclosure. In the SVT device, the doped region 28 is formed with a thickness in the fin 12 that is larger than the doped region 28 in the HVT device 100. In some embodiments, the doped region 28 of the SVT device 200 is about 0.5 nm to 2 nm thicker than the doped region 28 of the HVT device 100. In the SVT device 200, the doped region 28 and subsequently formed source and drain regions 30 further extend below the gate electrode 18 into the second region 36 of the fin.

19 and 20, in some embodiments of the present disclosure, an LVT device 300 is formed. In the LVT device, the doped region 28 is formed with a thickness in the fin 12 that is larger than the doped region 28 in the SVT device 200. In some embodiments, doped region 28 of LVT device 300 is about 0.5 nm to 2 nm thicker than doped region 28 of SVT device 200. In LVT device 300, doped region 28 and subsequently formed source and drain regions 30 are below gate electrode 18 into second region 36 of the fin than when SVT device is formed. Is extended further.

In some embodiments of the present disclosure, source / drain electrodes are formed that contact respective source / drain regions. The electrodes can be formed of a suitable conductive material such as copper, tungsten, nickel, titanium, and the like. In some embodiments, a metal silicide is formed at the source / drain interface with the conductive material to improve conductivity at the interface. In one example, a damascene and / or dual damascene process is used to form copper based multilayer interconnect structures. In some embodiments, tungsten is used to form tungsten plugs.

Subsequent processing according to embodiments of the present disclosure may also be configured to connect various features or structures of the FinFET device, various contacts / vias / lines and multi-layer interconnect features (eg, on a semiconductor substrate). , Metal layers and interlayer dielectrics). For example, the multi-layer interconnect includes vertical interconnects such as conventional vias or contacts, and horizontal interconnects such as metal lines.

In one embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a fin extending in a first direction over the substrate and a gate structure extending in a second direction over the fin. The gate structure includes a dielectric layer over the fin, a gate electrode over the gate dielectric layer, and a first insulated gate sidewall on the first side of the gate electrode, extending along the second direction. Source / drain regions are formed in fins in regions adjacent to the gate electrode structure. A portion of the source / drain regions extend below the insulating gate sidewalls by a substantially constant distance along the first direction.

In another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes forming a fin extending in a first direction over the substrate, and forming a plurality of gate structures extending in a second direction over the fin. The gate structures include a gate dielectric layer over the fin, gate electrodes over the gate dielectric layer, and insulated gate sidewalls on both sides of the gate electrodes extending along the second direction. A portion of the fin in the first region between adjacent gate structures is removed to form a recess in the fin. A doped region is formed on the surface of the recess. The doped regions are removed to form extended recesses, and source / drain regions are formed on the surface of the extended recesses. The source / drain regions extend along the second direction below the insulating gate sidewalls of adjacent gate electrode structures.

In another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes forming one or more fins extending in a first direction over the substrate. The one or more pins include at least one second area along the first direction and first areas on one side of each second area along the first direction. The gate structure extends along the second direction over the second region of fins. The gate structure includes a gate dielectric layer over the fin, a gate electrode over the gate dielectric layer, and a pair of insulated gate sidewalls formed on both sides of the gate electrode, extending along the second direction. A portion of the pin in the first regions is removed to form recesses in the first regions. Doped regions are formed on the surface of the recesses. The doped regions are removed to form extended recesses, and source / drain regions are formed on the surface of the extended recesses. The source / drain regions extend along the second direction below adjacent insulating gate sidewalls.

In another embodiment, a semiconductor device including a fin extending from a substrate and a gate structure disposed over the fin is discussed. In some examples, the gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and sidewall spacers formed along the sidewalls of the gate electrode. In various embodiments, the semiconductor device further includes a U-shaped recess formed in the fin and adjacent to the gate structure, and a first source / drain layer conformally formed on the surface of the U-shaped recess. In some cases, the first source / drain layer extends at least partially below adjacent gate structures. In addition, the semiconductor device includes a second source / drain layer formed over the first source / drain layer. In various embodiments, at least one of the first source / drain layer and the second source / drain layer comprises silicon arsenide (SiAs).

In another embodiment, a semiconductor device is discussed that includes a first gate structure disposed over a first region of a fin, a second gate structure disposed over a second region of a fin, and a recess formed in the fin. In some embodiments, a recess is adjacent each of the first gate structure and the second gate structure. In some examples, the semiconductor device further includes a first layer formed on the surface of the recess and a second layer formed over the first layer. In some cases, the first layer extends a first distance down each of the adjacent first gate structure and the adjacent second gate structure. Additionally, in some embodiments, at least one of the first layer and the second layer comprises silicon arsenic (SiAs).

In other embodiments, a method of manufacturing a semiconductor device that includes forming a gate structure over a fin extending from a substrate is discussed. In some embodiments, the gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and sidewall spacers formed along sidewalls of the gate electrode. In various examples, the method includes etching a portion of the fin adjacent to the gate structure to form a recess, etching a portion of the fin, forming a conformally doped layer on the surface of the recess, The method further includes removing the formal doped layer to form an extended recess, and forming a source / drain region within the extended recess. In some cases, the source / drain regions include a first layer formed on the surface of the extended recess, and a second layer formed over the first layer. In some embodiments, the source / drain regions extend below the sidewall spacers of adjacent gate structures. Further, in some embodiments, at least one of the first layer and the second layer comprises silicon arsenic (SiAs).

The foregoing has outlined features of some embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Be aware that there is. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications of the present disclosure can be made without departing from the spirit and scope of the present disclosure.

Examples

Example 1 In a semiconductor device,

Pins extending from the substrate;

A gate structure disposed on the fin, the gate structure including a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along sidewalls of the gate electrode;

A U-shaped recess formed in the fin and adjacent to the gate structure;

A first source / drain layer conformally formed on the surface of the U-shaped recess, wherein the first source / drain layer extends at least partially below the adjacent gate structure; And

And a second source / drain layer formed on the first source / drain layer,

And at least one of the first source / drain layer and the second source / drain layer comprises silicon arsenide (SiAs).

Embodiment 2. The semiconductor device of embodiment 1, wherein both the first source / drain layer and the second source / drain layer comprise silicon arsenic (SiAs).

Example 3 The semiconductor of Example 1, wherein the first source / drain layer comprises silicon arsenic (SiAs), and the second source / drain layer comprises SiP, SiCP, or a combination thereof. device.

Embodiment 4 The semiconductor device of embodiment 1, wherein the first source / drain layer comprises SiP and the second source / drain layer comprises silicon arsenic (SiAs).

Example 5. The semiconductor of Example 1, wherein the first source / drain layer comprises silicon arsenic (SiAs), and the second source / drain layer comprises SiAs, SiP, or a combination thereof. device.

Embodiment 6. The semiconductor device of embodiment 1, further comprising a capping layer formed over the second source / drain layer.

Embodiment 7. The semiconductor device of embodiment 1, wherein the first source / drain layer has a thickness equal to 0.1 nanometers to 5 nanometers.

Example 8. In Example 1, the first source / drain layer comprises SiAs, and the first source / drain layer is an As dopant within the range of 1.2x10 ²⁰ atoms / cm ³ to 1.2x10 ²¹ atoms / cm ³ A semiconductor device having a concentration.

Example 9. In Example 1, the second source / drain layer comprises SiAs, and the second source / drain layer is an As dopant in the range of 9.6x10 ²⁰ atoms / cm ³ to 7.5x10 ²¹ atoms / cm ³ A semiconductor device having a concentration.

Example 10. In a semiconductor device,

A first gate structure disposed over the first region of the fin, and a second gate structure disposed over the second region of the fin;

A recess formed in the fin, wherein the recess is adjacent to each of the first gate structure and the second gate structure;

A first layer formed on the surface of the recess, the first layer extending by a first distance below each of the adjacent first gate structure and the adjacent second gate structure; And

A second layer formed on the first layer,

And at least one of the first layer and the second layer comprises silicon arsenic (SiAs).

Example 11. The semiconductor device of example 10, wherein both the first layer and the second layer comprise silicon arsenic (SiAs).

Example 12. The semiconductor device of example 10, wherein the first layer comprises silicon arsenic (SiAs), and the second layer comprises SiP, SiCP, or a combination thereof.

Example 13. The semiconductor device of example 10, wherein the first layer comprises SiP and the second layer comprises silicon arsenic (SiAs).

Example 14. The semiconductor device of example 10, wherein the first layer comprises silicon arsenic (SiAs), and the second layer comprises SiAs, SiP, or a combination thereof.

Embodiment 15. In Embodiment 10, the first gate structure includes a first gate electrode, and a first spacer having a first width formed along a first sidewall of the first gate electrode, and wherein the second gate structure is The gate structure includes a second gate electrode, and a second spacer having a second width formed along a second sidewall of the second gate electrode, wherein the recess is adjacent to each of the first sidewall and the second sidewall The semiconductor device that is done.

Embodiment 16. The semiconductor device of embodiment 15, wherein the first distance is equal to each of the first width and the second width or smaller than each of the first width and the second width.

Embodiment 17. The semiconductor device of embodiment 15, wherein the first distance is greater than each of the first width and the second width.

Example 18. A method for manufacturing a semiconductor device,

Forming a gate structure over a fin extending from the substrate, the gate structure including a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and sidewall spacers formed along sidewalls of the gate electrode. ;

Etching a portion of the fin to etch a portion of the fin adjacent to the gate structure to form a recess;

Forming a conformally doped layer on the surface of the recess;

Removing the conformally doped layer to form an extended recess; And

Forming a source / drain region in the extended recess, the source / drain region being a first layer formed on the surface of the extended recess, and a second layer formed over the first layer And wherein the source / drain regions extend below sidewall spacers of the adjacent gate structure, and at least one of the first layer and the second layer comprises silicon arsenic (SiAs). Manufacturing method.

Example 19. The method of example 18, further comprising forming a source / drain region within the extended recess, wherein both the first layer and the second layer comprise silicon arsenic (SiAs). , Semiconductor device manufacturing method.

Example 20. The method of Example 18 further comprising conformally forming the first layer on the surface of the extended recess, the first layer having a thickness equal to 0.1 nanometers to 5 nanometers. The method of having a semiconductor device.

Claims (10)

In a semiconductor device,
Pins extending from the substrate;
A gate structure disposed on the fin, the gate structure including a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along sidewalls of the gate electrode;
A first U-shaped recess formed in the fin and adjacent to the gate structure;
A first SiAs source / drain layer formed conformally on the surface of the first U-shaped recess such that a first silicon arsenide (SiAs) source / drain layer forms a second U-shaped recess- The first SiAs source / drain layer partially extends beneath the adjacent gate electrode, and the first SiAs source / drain layer is doped to a first concentration with a first dopant-; And
A second SiAs source / drain layer formed on the first SiAs source / drain layer and completely filling the second U-shaped recess, wherein the second SiAs source / drain layer is greater than the first concentration with the first dopant Doped to 2 concentrations-
A semiconductor device comprising a. The semiconductor device of claim 1, wherein the second SiAs source / drain layer extends up to a height higher than the fin. The second SiAs source / drain layer further comprises a capping layer formed of a different material from the second SiAs source / drain layer and physically contacting the upper surface of the second SiAs source / drain layer. The semiconductor device is a top surface of the drain layer facing away from the fin. 4. The semiconductor device of claim 3, wherein the second SiAs source / drain layer and the capping layer are in physical contact with the sidewall spacers of the gate structure. The method of claim 4, further comprising another gate structure disposed on the fin, the other gate structure being formed of another gate dielectric formed on the fin, another gate electrode formed on the other gate dielectric, and the other gate electrode. And other sidewall spacers formed along the sidewalls,
And the second SiAs source / drain layer and the capping layer continuously extend from sidewall spacers of the gate structure to sidewalls of the other gate structure. The semiconductor device of claim 1, further comprising a capping layer formed on the second SiAs source / drain layer. The semiconductor device of claim 1, wherein the first SiAs source / drain layer has a thickness equal to 0.1 nanometers to 5 nanometers. In a semiconductor device,
A first gate structure disposed over the first region of the fin, and a second gate structure disposed over the second region of the fin;
A first recess formed in the fin, wherein the first recess is adjacent to each of the first gate structure and the second gate structure;
A first silicon arsenic (SiAs) layer formed on the surface of the first recess, wherein the first SiAs layer extends a first distance down each of the adjacent first gate structure and the adjacent second gate structure, respectively , The first SiAs layer forms a second recess, and the first SiAs layer is doped to a first concentration with a first dopant-; And
A second SiAs layer formed over the first SiAs layer and completely filling the second recess, wherein the second SiAs layer is doped with the first dopant to a second concentration greater than the first concentration-
A semiconductor device comprising a. The method of claim 8, wherein the first gate structure comprises a first gate electrode, and a first spacer having a first width formed along a first sidewall of the first gate electrode, and the second gate structure comprises And a second spacer having a second width formed along a second sidewall of the second gate electrode and the second gate electrode, wherein the first recess is adjacent to each of the first sidewall and the second sidewall. Semiconductor device. A method for manufacturing a semiconductor device,
Forming a gate structure over a fin extending from the substrate, the gate structure including a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and sidewall spacers formed along sidewalls of the gate electrode. ;
Etching a portion of the fin to etch a portion of the fin adjacent to the gate structure to form a recess;
Forming a conformally doped layer within the surface of the recess;
Removing the conformally doped layer to form an extended recess; And
Forming a source / drain region in the extended recess, the source / drain region being a first silicon arsenic (SiAs) layer formed on the surface of the extended recess, and the first SiAs layer A second SiAs layer formed thereon, the first SiAs layer forming a second recess completely filled by the second SiAs layer, and the source / drain regions are adjacent sidewall spacers of the gate structure The semiconductor device, which extends downward, wherein the first SiAs layer is doped to a first concentration with a first dopant, and the second SiAs layer is doped to a second concentration greater than the first concentration with the first dopant. Manufacturing method.

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