KR102101419B1 - Method for routing table lookup and memory system implementing the same - Google Patents

Abstract

A memory system includes: a memory storing a routing table comprising a plurality of nodes for expressing next hop information in accordance with an IP address and a plurality of branches connecting the nodes; and a memory controller dividing an IP address of an input packet into at least one unit address, determining an end node, which does not have a child node, among target nodes related with the unit address by sequentially exploring the target nodes through an external display of the routing table, and determining the next hop information corresponding to the end node through an internal display of the routing table. The external display includes information about whether each of the nodes of the routing table includes a child node. The internal display includes next hop information corresponding to the end node if each of the nodes is the end node. Each of the nodes includes the external display and the internal display.

Description

METHOD FOR ROUTING TABLE LOOKUP AND MEMORY SYSTEM IMPLEMENTING THE SAME}

The present invention relates to an Internet protocol routing table search method and a high bandwidth memory system implementing the same.

IP traffic has grown exponentially over the years due to the development of Internet technology. In order to transmit a large amount of IP traffic smoothly, it is essential for the router to process packets reliably, which means that the router must have a high level of system availability.

On the other hand, most of the routers currently in use store routing tables in DRAM (Dynamic Random Access Memory, DRAM) for high routing performance. However, DRAM has a disadvantage in that data stored in memory is deleted when electricity is not supplied, and this causes a problem in that a large-capacity routing table must be rebuilt when power is lost due to a failure in the router.

To solve this problem, there is a method to improve the system availability of the router by storing the routing table in non-volatile memory, but in this case, the speed of accessing the memory to refer to the routing table is reduced due to the nature of the non-volatile memory. Occurs.

The problem to be solved by the present invention is to secure the high availability of the system by storing the routing table in a phase change memory (PCM), but to nodes other than the terminal node when the trie-based routing table is queried. It provides a technique to improve performance by only reading external indicators.

In addition, the problem to be solved by the present invention is to provide a technique for efficiently determining a memory bank to be accessed in order to quickly perform packet routing by granting the same number of dedicated memory banks for each copy when multiple routing table copies exist. Is to do.

In addition, a problem to be solved by the present invention is to provide a technique for designing a shared buffer so that buffers present in each memory bank can be efficiently used when a plurality of copies of routing tables exist in the memory system.

A memory system according to an embodiment of the present invention stores a routing table implemented with a plurality of nodes and a plurality of branches connecting the plurality of nodes to express next hop information according to an IP address. The terminal that does not have a child node among the target nodes by sequentially dividing the IP address of the memory and the input packet into at least one unit address and sequentially searching target nodes related to the unit addresses through an external indicator of the routing table And a memory controller for determining a node and determining next hop information corresponding to the end node through an internal indicator in the routing table, wherein the external indicator is information about whether each node in the routing table has a child node. Including, the internal indicator is that each of the nodes is the terminal node Right side includes next hop information corresponding to the end node, and the plurality of nodes includes the outer indicator and the inner indicator, respectively.

The memory is implemented as a phase change memory (PCM).

The memory is implemented as a non-volatile memory (Non-Volatile Memory).

The memory is a memory bank group that stores a copy of the routing table in a plurality of memory banks configured therein, a plurality of local buffers that are independently allocated to each memory bank, and is independently allocated to the memory bank group and the It includes a shared buffer interlocked with a plurality of local buffers.

The memory controller determines a target memory bank to access in order to determine the next hop information among the plurality of memory banks in consideration of the frequency of access to each memory bank.

The memory controller determines, as the target memory bank, a first memory bank storing a copy of a routing table whose buffer hit value is less than a threshold buffer hit value among the plurality of memory banks.

When the first memory bank does not exist, the memory controller determines a second memory bank that stores a copy of the routing table in an idle state as the target memory bank.

When the second memory bank does not exist, the memory controller determines the third memory bank that stores a copy of the previously bound routing table as the target memory bank.

When the third memory bank does not exist, the memory controller determines the fourth memory bank storing the copy of the least bound routing table as the target memory bank.

A method for a memory controller according to an embodiment of the present invention to search for a routing table stored in memory includes receiving an IP address of an input packet and access frequency to a plurality of memory banks each storing a copy of the routing table. Considering, determining a target memory bank to access to determine next hop information corresponding to the IP address, dividing the IP address into at least one unit address, and outside the routing table stored in the target memory bank Sequentially searching for target nodes related to the unit addresses through an indicator to determine an end node without a child node among the target nodes, and a next hop corresponding to the end node through an internal indicator of the routing table Determining information, and the routing table In order to express next hop information according to the IP address, a plurality of nodes and a plurality of branches connecting the plurality of nodes are implemented, and the external indicator indicates whether each node of the routing table has a child node. Information, and the internal indicator includes next hop information corresponding to the terminal node when each node is the terminal node, and the plurality of nodes each include the external indicator and the internal indicator.

In the determining of the target memory bank, among the plurality of memory banks, a first memory bank storing a copy of a routing table having a buffer hit value less than a threshold buffer hit value is determined as the target memory bank. .

In the determining of the target memory bank, when the first memory bank does not exist, the second memory bank storing a copy of the routing table in an idle state is determined as the target memory bank.

In the determining of the target memory bank, when the second memory bank does not exist, the third memory bank storing a copy of the previously bound routing table is determined as the target memory bank.

In the determining of the target memory bank, when the third memory bank does not exist, the fourth memory bank storing a copy of the least bound routing table is determined as the target memory bank.

The memory is implemented as a phase change memory (PCM).

The memory is implemented as a non-volatile memory (Non-Volatile Memory).

According to the present invention, when an arbitrary tri-node is approached to perform packet routing, if a child node requiring additional discovery is preferentially determined in memory through external indicators, the internal indicator only exists when it does not exist Because (Internal Indicators) additional hop search of the hop information in the node, the search performance of the phase change memory-based routing table can be improved.

In addition, according to the present invention, memory bandwidth efficiency can be improved by determining a memory bank for performing packet routing in consideration of an expected processing speed.

Further, according to the present invention, buffer accessibility of memory banks can be improved by storing a routing table node in which multiple accesses are attempted and a node requiring modification in a shared buffer.

1 is a diagram illustrating a memory system according to an embodiment.
2 is a routing table implemented with a binary tri structure according to an embodiment.
3 is a diagram illustrating an internal indicator and an external indicator according to an embodiment.
FIG. 4 is a diagram illustrating a method for a memory controller to determine a memory bank to be accessed from among a plurality of memory banks.
5 is a diagram illustrating a method for a memory controller to search a routing table stored in memory.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains may easily practice. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. In addition, in order to clearly describe the present invention in the drawings, parts irrelevant to the description are omitted, and like reference numerals are assigned to similar parts throughout the specification.

Throughout the specification, when a part “includes” a certain component, it means that the component may further include other components, not to exclude other components, unless otherwise stated.

1 is a diagram illustrating a memory system according to an embodiment, FIG. 2 is a routing table implemented with a binary tri structure according to an embodiment, and FIG. 3 is a diagram illustrating an internal indicator and an external indicator according to an embodiment It is a drawing.

Referring to FIG. 1, the memory system 1000 includes a memory 100 and a memory controller 200.

Specifically, the memory 100 is implemented as either a phase change memory (PCM) or a non-volatile memory (Non-Volatile Memory).

Here, the nonvolatile memory includes a nonvolatile memory having a read asymmetric property. Specifically, even in the same transaction, when the memory is a nonvolatile memory having an asymmetric read attribute, a part of the transaction may be latched in a buffer first, and the present invention can also be applied to a nonvolatile memory having such an asymmetric read attribute. .

For example, as illustrated in FIG. 1, a module of the memory 100 may be implemented as a dual in-line memory module (DIMM), in which case the memory 100 includes a plurality of phases. It can be any one of change memories. The memory 100 may include memory bank groups composed of memory banks, local buffers, shared buffers, and a bit checker, which will be described later in detail.

On the other hand, the memory 100 stores a routing table implemented with a plurality of nodes and a plurality of branches connecting a plurality of nodes to express next hop information according to an IP address.

Each node of the routing table stored in the memory 100 includes an external indicator including information on whether each node of the routing table has a child node, and next hop information corresponding to the terminal node when each node is an end node. Each includes an internal indicator.

Hereinafter, the routing table stored in the memory 100 will be described with reference to FIGS. 2 and 3.

2 is a routing table implemented with a binary tri structure according to an embodiment, and FIG. 3 is a diagram illustrating an internal indicator and an external indicator according to an embodiment.

Referring to FIG. 2, a routing table is composed of a plurality of nodes and a plurality of branches connecting a plurality of nodes. The part corresponding to "0" in the IP address moves through the left branch of the node, and the part corresponding to "1" in the IP address moves through the right branch of the node. When a specific IP address is input, the process moves to a terminal node without a child node and determines a value corresponding to the terminal node as the next hop information of the specific IP address.

For example, when the IP address "101111111" is input, it moves to the end node 20 along the nodes 10, 12, 14, 15, 16, 18 and 19 determined through the corresponding process, and the end node Since the next hop information "G" is mapped to (20), the next hop information for the IP address "101111111" is determined as "G".

3 illustrates an internal indicator and an external indicator included in each node of the routing table of FIG. 2.

Referring to FIG. 3, a routing table implemented through a tree bitmap algorithm includes an internal indicator 30 and an external indicator 40.

The internal indicator 30 manages next hop information according to the IP address, and the external indicator 40 manages the existence of child nodes.

For example, in FIG. 3, when each node constituting the internal indicator 30 has a value of “0” to “7” when expressed in decimal notation, the external indicator 40 includes 8 fields And, if a node corresponding to a specific field has a child node, the field value may be displayed as "1", and if the node corresponding to a specific field does not have a child node, the field value may be displayed as "0".

If the IP address "101111111" is input, the IP address "101111111" may be divided into three unit addresses "101", "111" and "111".

If "101" is written in decimal notation, "5", and referring to the external indicator 40, the field value of "5" is "1", so a child node exists. Therefore, since a child node exists, it moves to the next unit address "111" through a child pointer.

If "111" is written in decimal notation, "7", and referring to the external indicator 40, the field value of "7" is also "1", so a child node exists. Therefore, even in this case, it moves to the next unit address "111" through the child pointer.

Referring to the external indicator 40 for the decimal notation "7" for "111", the field value of "7" is "0". In this case, since the child node does not exist, the next hop information " G " corresponding to this is determined by referring to the internal indicator 30 and the next hop pointer.

That is, when determining the next hop information corresponding to the IP address using the internal indicator 30 and the external indicator 40, the external indicator 40 is not accessed without accessing the internal indicator 30 until the end node is determined. You can use it to make decisions.

When the IP address is input, the memory controller 200 determines the next hop information corresponding to the input IP address using the routing table stored in the memory 100.

For example, when the memory 100 is a phase change memory, the memory controller 200 includes a binder unit 210, query information 220, a DDR3 interface unit 230, and an address determining unit (ADU). The next hop information corresponding to the IP address input through the 240 and the next hop information determination unit 250 may be determined.

Since the general method for determining the next hop information through the above units by the memory controller for the phase change memory is a well-known technique, a detailed description is omitted herein, and the function of the memory controller 200 differentiated from the known technique is described below. Explain.

The memory controller 200 divides the IP address of the input packet into at least one unit address.

For example, when the extracted IP address is "101111111", the memory controller 200 may generate unit addresses "101", "111" and "111" by dividing the IP address by 3 bits.

The memory controller 200 determines the next hop information corresponding to the IP address using the external indicator and the internal indicator of the routing table stored in the memory 100.

Specifically, the memory controller 200 sequentially searches target nodes related to unit addresses through an external indicator to determine an end node that does not have a child node among target nodes, and then corresponds to the end node through an internal indicator. Determine hop information.

For example, when the external indicator 40 is implemented as illustrated in FIG. 3, the memory controller 200 determines that the decimal notation of the first unit address “101” is “5”, and the external indicator 40 ), The field value of "5" corresponding to the unit address "101" is "1" (the child node exists), and the same process is performed for the second unit address "111".

Even in the case of the second unit address "111", since the field value of "7" in the external indicator 40 is "1" (there is a child node), the same process is performed for the third unit address "111".

In the case of the third unit address "111", the child node does not exist because the field value of "7" in the external indicator 40 is "0".

Therefore, the memory controller 200 may determine the node corresponding to the third unit address "111" as the end node, and determine the next hop information "G" corresponding to the end node with reference to the internal indicator 30.

In the above process, the memory controller 200 determines the end node using only the external indicator 40 without accessing the internal indicator 30, and accesses the internal indicator 30 to determine the IP address after the end node is determined. Since the corresponding next hop information is determined, the time to access the memory 100 is reduced, and as a result, query performance of the routing table can be improved.

Specifically, if the end node is not determined using only the external indicator 40, the presence or absence of next hop information is also determined for nodes other than the end node. In this case, all memory transactions are requested. For example, if you want to process a transaction of 64 bytes, both the outer 32 bytes and the inner 32 bytes must be fetched for nodes that are not end nodes.

However, if the end node is determined using only the external indicator 40 and the end node is determined, then the internal indicator 30 is accessed to determine the next hop information corresponding to the IP address. As for the node, the internal indicator 30 is selectively accessed, and thus, the access waiting time may be close to half of the original access waiting time.

To implement this, the internal indicator 30 is mapped to the least significant bit (LSB), the external indicator 40 is mapped to the MSB (Most Significant Bit), and in this case, the external indicator 40 is the internal indicator 30 It is latched earlier. For example, if the node address is provided with an additional 7 bit stride through the address pin, the 7 bit stride is decoded into a 128 bit vector while the MSB is being read from memory 100. Thereafter, a bit AND operation is performed on the 128-bit vector and the 128-bit external indicator 40 extracted from the MSB by the bit checker 140 on all chips. If the target chip indicates that it is not an end node, a second read disable signal is broadcast to all chips and the rest of the reads from the LSB are cancelled. After fetching the node, the address determination unit 240 of the memory controller 100 requests the address of the next node. When the next hop information determination unit 250 determines the next hop information through the above process, the search of the routing table is ended.

Meanwhile, the memory 100 includes a plurality of memory bank groups 110 and 111, a plurality of local buffers 120 and 121, and a plurality of shared buffers 130 and 131.

The plurality of memory bank groups 110 and 111 respectively store a copy of the routing table in a plurality of memory banks configured therein.

In this case, the memory banks included in the same memory bank group store a copy of the same routing table. For example, the memory banks 110a to 110d of the first memory bank group 110 may store a copy of the same routing table.

The plurality of local buffers 120 and 121 are allocated independently to each memory bank.

For example, the first local buffers 120a to 120d are allocated to the memory banks 110a to 110d of the first memory bank group 110, respectively.

The plurality of shared buffers 130 and 131 are independently allocated to the plurality of memory bank groups 110 and 111, respectively, and are interlocked with the plurality of local buffers 120 and 121, respectively.

For example, the first shared buffer 130 is independently allocated to the first memory bank group 110 and interlocks with the first local buffers 120a to 120d.

By constructing a plurality of shared buffers 130 and 131 in the memory 100, the memory 100 stores duplicate contents of a duplicate of a routing table stored in the plurality of memory bank groups 110 and 111 by a plurality of locals Since it is possible to avoid loading the buffers 120 and 121, it is possible to efficiently use a plurality of local buffers 120 and 121.

Specifically, when a write request occurs more than a preset threshold frequency in the plurality of local buffers 120 and 121, the write request is likely to damage the consistency of the copies of the routing table. That is, since a write request must be immediately committed to all copies of the routing table, all copies of the routing table must be evicted from the plurality of local buffers 120 and 121 prior to the write request.

In this process, a buffer omission may occur. When a plurality of shared buffers 130 and 131 are constructed, a write request is provided to the plurality of shared buffers 130 and 131, and excessively a plurality of local buffers 120 And 121) can be prevented from being removed.

On the other hand, when a write request to the plurality of local buffers 120 and 121 occurs below a preset threshold frequency, the plurality of shared buffers 130 and 131 are victim buffers of the plurality of local buffers 120 and 121 (victim buffer). In this case, instead of removing the plurality of local buffers 120 and 121 after satisfying the threshold buffer hit value, a routing table is provided to the plurality of shared buffers 130 and 131 to satisfy a buffer hit equal to or greater than the threshold buffer hit value. Make a copy of it.

Meanwhile, the plurality of local buffers 120 and 121 and the plurality of shared buffers 130 and 131 may all be managed by a Least Recently Used Algorithm (LRU algorithm).

The memory controller 200 determines a memory bank to be accessed in order to determine next hop information among a plurality of memory banks in consideration of the frequency of access to each memory bank, and the contents thereof will be described with reference to FIG. 4.

FIG. 4 is a diagram illustrating a method for a memory controller to determine a memory bank to be accessed from among a plurality of memory banks.

Referring to FIG. 4, the memory controller 200 determines a buffer hit value of a copy of a routing table stored in each of a plurality of memory banks (S100), and the buffer hit value is less than a threshold buffer hit value It is checked whether a copy of the table exists (S110).

If there is a copy of the routing table with a buffer hit value less than the critical buffer hit value, the memory controller 200 accesses a first memory bank that stores a copy of the routing table with a buffer hit value less than the critical buffer hit value. Next hop information is determined using a copy of the routing table stored in the memory bank (S111).

If there is no copy of the routing table whose buffer hit value is less than the threshold buffer hit value, the memory controller 200 checks whether a copy of the routing table in the idle state exists (S120).

If a copy of the routing table in the idle state exists, the memory controller 200 accesses a second memory bank storing a copy of the routing table in the idle state and stores the copy in the second memory bank. Next hop information is determined using a copy of the routing table (S121).

If there is no copy of the routing table in the idle state, the memory controller 200 checks whether a copy of the previously bound routing table exists (S130).

If a copy of the previously bound routing table exists, the memory controller 200 accesses a third memory bank storing a copy of the previously bound routing table and uses a copy of the routing table stored in the third memory bank. To determine next hop information (S131).

If a copy of the previously bound routing table does not exist, the memory controller 200 determines the number of bindings of the copy of the routing table stored in each of the plurality of memory banks (S140), and of the least bound routing table. Next hop information is determined by accessing the fourth memory bank storing the copy and using the copy of the routing table stored in the fourth memory bank (S141).

That is, the memory controller 200 prevents binding an excessive hit to a specific memory bank in consideration of buffer hit values, idle state information, and binding information of a copy of the routing table. Through the method shown in FIG. 4, the buffer hit value is less than the threshold buffer hit value, and a high buffer hit ratio is induced in the copy of the previously bound routing table, and the number of idle and low-usage routing table copies can be minimized. have.

5 is a diagram illustrating a method for a memory controller to search a routing table stored in memory.

In FIG. 5, the same contents as in FIGS. 1 to 4 are omitted.

Referring to FIG. 5, the memory controller 200 receives the IP address of the input packet (S200).

The memory controller 200 determines a target memory bank to be accessed in order to determine next hop information corresponding to an IP address in consideration of the frequency of access to a plurality of memory banks each storing a copy of the routing table (S210). .

Specifically, the memory controller 200 determines, as a target memory bank, a first memory bank storing a copy of a routing table in which a buffer hit value is less than a threshold buffer hit value among a plurality of memory banks.

If the first memory bank does not exist, the memory controller 200 determines a second memory bank that stores a copy of the routing table in an idle state as a target memory bank.

If the second memory bank does not exist, the memory controller 200 determines a third memory bank that stores a copy of the previously bound routing table as the target memory bank.

If the third memory bank does not exist, the memory controller 200 determines a fourth memory bank that stores a copy of the least bound routing table as a target memory bank.

When determining the target memory bank, the memory controller 200 divides the IP address into at least one unit address (S220).

Meanwhile, in FIG. 5, after determining the target memory bank, the IP address is divided into unit addresses, but the memory controller 200 may determine the target memory bank through the above method after dividing the IP address into unit addresses.

The memory controller 200 sequentially searches target nodes related to unit addresses through an external indicator stored in the target memory bank to determine a terminal node having no child nodes among the target nodes (S230).

The memory controller 200 determines next hop information corresponding to the end node through an internal indicator stored in the target memory bank (S240).

According to the present invention, when an arbitrary tri-node is accessed to perform packet routing, if a child node requiring additional search is preferentially determined in memory through external indicators, the internal indicator is only present when it does not exist. Because (Internal Indicators) additional hop search of the hop information in the node, the search performance of the phase change memory-based routing table can be improved.

In addition, according to the present invention, memory bandwidth efficiency can be improved by determining a memory bank for performing packet routing in consideration of an expected processing speed.

Further, according to the present invention, buffer accessibility of memory banks can be improved by storing a routing table node in which multiple accesses are attempted and a node requiring modification in a shared buffer.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (16)

As a memory system,
Memory for storing a routing table implemented with a plurality of nodes and a plurality of branches connecting the plurality of nodes to express next hop information according to an IP address,
The IP address of the input packet is divided into at least one or more unit addresses, and the target nodes associated with the unit addresses are sequentially searched through an external indicator in the routing table to identify a terminal node having no child node among the target nodes. And a memory controller for determining next hop information corresponding to the end node through an internal indicator of the routing table,
The external indicator includes information on whether each node of the routing table has a child node, and the internal indicator includes next hop information corresponding to the terminal node when each node is the terminal node, and the A memory system in which a plurality of nodes each include the external indicator and the internal indicator. In claim 1,
The memory
Memory system implemented with phase change memory (PCM). In claim 1,
The memory
Memory system implemented as a non-volatile memory (Non-Volatile Memory). In claim 1,
The memory
A memory bank group that stores a copy of the routing table in a plurality of memory banks configured therein, a plurality of local buffers independently allocated to each memory bank, and a plurality of locals independently allocated to the memory bank group A memory system including a shared buffer interlocked with buffers. In claim 4,
The memory controller
A memory system that determines a target memory bank to be accessed to determine the next hop information among the plurality of memory banks in consideration of the frequency of access to each memory bank. In claim 5,
The memory controller
A memory system that determines, as the target memory bank, a first memory bank storing a copy of a routing table whose buffer hit value is less than a threshold buffer hit value among the plurality of memory banks. In claim 6,
The memory controller
When the first memory bank does not exist, the memory system determines the second memory bank storing a copy of the routing table in an idle state as the target memory bank. In claim 7,
The memory controller
If the second memory bank does not exist, the memory system determines the third memory bank storing a copy of the previously bound routing table as the target memory bank. In claim 8,
The memory controller
If the third memory bank does not exist, the memory system determines the fourth memory bank storing the copy of the least-bound routing table as the target memory bank. A method for a memory controller to search a routing table stored in memory,
Receiving the IP address of the input packet,
Determining a target memory bank to access to determine next hop information corresponding to the IP address, considering the frequency of access to a plurality of memory banks that respectively store a copy of the routing table,
The IP address is divided into at least one or more unit addresses, and the target nodes associated with the unit addresses are sequentially searched through an external indicator of the routing table stored in the target memory bank to not have a child node among the target nodes. Determining an end node, and
And determining next hop information corresponding to the end node through an internal indicator of the routing table,
The routing table is implemented with a plurality of nodes and a plurality of branches connecting the plurality of nodes to express next hop information according to the IP address, and the external indicator indicates that each node of the routing table is a child node. Information on whether or not to have it, and the internal indicator includes next hop information corresponding to the terminal node when each node is the terminal node, and the plurality of nodes respectively include the external indicator and the internal indicator How to search. In claim 10,
Determining the target memory bank is
Among the plurality of memory banks, a search method for determining a first memory bank for storing a copy of a routing table having a buffer hit value less than a threshold buffer hit value as the target memory bank. In claim 11,
Determining the target memory bank is
When the first memory bank does not exist, a search method for determining a second memory bank that stores a copy of an idle state routing table as the target memory bank. In claim 12,
Determining the target memory bank is
When the second memory bank does not exist, a search method for determining a third memory bank storing a copy of a previously bound routing table as the target memory bank. In claim 13,
Determining the target memory bank is
When the third memory bank does not exist, a search method for determining a fourth memory bank that stores a copy of the least bound routing table as the target memory bank. In claim 10,
The memory
A search method implemented in phase change memory (PCM). In claim 10,
The memory
A search method implemented as a non-volatile memory.

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