KR102086019B1 - 이종 프로세서를 사용하여 애플리케이션에 낮은 레이턴시를 제공하는 시스템 및 방법 - Google Patents

이종 프로세서를 사용하여 애플리케이션에 낮은 레이턴시를 제공하는 시스템 및 방법 Download PDF

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KR102086019B1
KR102086019B1 KR1020157000272A KR20157000272A KR102086019B1 KR 102086019 B1 KR102086019 B1 KR 102086019B1 KR 1020157000272 A KR1020157000272 A KR 1020157000272A KR 20157000272 A KR20157000272 A KR 20157000272A KR 102086019 B1 KR102086019 B1 KR 102086019B1
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memory
requests
processors
values
gpu
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KR20150024884A (ko
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알렉산더 랴세브스키
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • G06F16/24569—Query processing with adaptation to specific hardware, e.g. adapted for using GPUs or SSDs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/901—Indexing; Data structures therefor; Storage structures
    • G06F16/9014—Indexing; Data structures therefor; Storage structures hash tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5033—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering data affinity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—Three-dimensional [3D] image rendering
    • G06T15/005—General purpose rendering architectures

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Computer Graphics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Retry When Errors Occur (AREA)
  • Multi Processors (AREA)
KR1020157000272A 2012-06-08 2013-06-07 이종 프로세서를 사용하여 애플리케이션에 낮은 레이턴시를 제공하는 시스템 및 방법 Active KR102086019B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261657404P 2012-06-08 2012-06-08
US61/657,404 2012-06-08
PCT/US2013/044682 WO2013185015A2 (en) 2012-06-08 2013-06-07 System and method for providing low latency to applications using heterogeneous processors

Publications (2)

Publication Number Publication Date
KR20150024884A KR20150024884A (ko) 2015-03-09
KR102086019B1 true KR102086019B1 (ko) 2020-04-14

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KR1020157000272A Active KR102086019B1 (ko) 2012-06-08 2013-06-07 이종 프로세서를 사용하여 애플리케이션에 낮은 레이턴시를 제공하는 시스템 및 방법

Country Status (6)

Country Link
US (1) US9495718B2 (cg-RX-API-DMAC10.html)
EP (1) EP2859448A2 (cg-RX-API-DMAC10.html)
JP (1) JP6170553B2 (cg-RX-API-DMAC10.html)
KR (1) KR102086019B1 (cg-RX-API-DMAC10.html)
CN (1) CN104395890B (cg-RX-API-DMAC10.html)
WO (1) WO2013185015A2 (cg-RX-API-DMAC10.html)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG11201606302TA (en) * 2014-02-04 2016-08-30 Tactual Labs Co Low-latency visual response to input via pre-generation of alternative graphical representations of application elements and input handling on a graphical processing unit
US9342384B1 (en) 2014-12-18 2016-05-17 Intel Corporation Function callback mechanism between a central processing unit (CPU) and an auxiliary processor
US9711194B2 (en) * 2015-01-28 2017-07-18 Xilinx, Inc. Circuits for and methods of controlling the operation of a hybrid memory system
KR102352756B1 (ko) 2015-04-29 2022-01-17 삼성전자주식회사 애플리케이션 프로세서, 시스템 온 칩, 및 이를 포함하는 컴퓨팅 장치
KR101923210B1 (ko) * 2016-01-14 2018-11-28 서울대학교산학협력단 이종 멀티코어 프로세서를 활용한 암호화 처리 장치 및 암호화 처리 방법
US11513805B2 (en) * 2016-08-19 2022-11-29 Wisconsin Alumni Research Foundation Computer architecture with synergistic heterogeneous processors
US10929944B2 (en) * 2016-11-23 2021-02-23 Advanced Micro Devices, Inc. Low power and low latency GPU coprocessor for persistent computing
US10795840B2 (en) 2018-11-12 2020-10-06 At&T Intellectual Property I, L.P. Persistent kernel for graphics processing unit direct memory access network packet processing
CN111447561B (zh) * 2020-03-16 2023-04-18 阿波罗智联(北京)科技有限公司 车辆的图像处理系统
US20240220446A1 (en) * 2022-12-30 2024-07-04 Intel Corporation Methods, systems, and apparatuses for dynamic simultaneous multi-threading (smt) scheduling to maximize processor performance on hybrid platforms

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272612B1 (en) 1997-09-04 2001-08-07 Bull S.A. Process for allocating memory in a multiprocessor data processing system
US7554959B1 (en) 1999-12-02 2009-06-30 Cisco Technology, Inc. Apparatus and method for cluster network device discovery
US20110057937A1 (en) 2009-09-09 2011-03-10 Ren Wu Method and system for blocking data on a gpu
US20110210982A1 (en) * 2010-02-26 2011-09-01 Microsoft Corporation Low latency rendering of objects

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0285927A (ja) * 1988-09-22 1990-03-27 Hitachi Vlsi Eng Corp 記憶装置
US8269793B2 (en) * 2003-02-18 2012-09-18 Serverside Group Limited Apparatus and method for manipulating images
US8484647B2 (en) * 2009-07-24 2013-07-09 Apple Inc. Selectively adjusting CPU wait mode based on estimation of remaining work before task completion on GPU
US8937622B2 (en) * 2010-09-20 2015-01-20 Qualcomm Incorporated Inter-processor communication techniques in a multiple-processor computing platform
RU2013125719A (ru) * 2010-12-16 2015-01-27 Ити Интернэшнл, Инк. Архитектура распределенных вычислений

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272612B1 (en) 1997-09-04 2001-08-07 Bull S.A. Process for allocating memory in a multiprocessor data processing system
US7554959B1 (en) 1999-12-02 2009-06-30 Cisco Technology, Inc. Apparatus and method for cluster network device discovery
US20110057937A1 (en) 2009-09-09 2011-03-10 Ren Wu Method and system for blocking data on a gpu
US20110210982A1 (en) * 2010-02-26 2011-09-01 Microsoft Corporation Low latency rendering of objects

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Jeff A. Stuart 외 2명. ‘GPU-to-CPU Callbacks’. Euro-Par 2010 Workshops, LNCS 6586, pp.365-372, 2011.*

Also Published As

Publication number Publication date
CN104395890B (zh) 2018-12-07
JP6170553B2 (ja) 2017-07-26
EP2859448A2 (en) 2015-04-15
WO2013185015A3 (en) 2014-01-30
US9495718B2 (en) 2016-11-15
WO2013185015A2 (en) 2013-12-12
US20130328891A1 (en) 2013-12-12
JP2015522878A (ja) 2015-08-06
KR20150024884A (ko) 2015-03-09
CN104395890A (zh) 2015-03-04

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