KR102065667B1 - Display driver integrated circuit and display device having the same - Google Patents

Abstract

According to one embodiment of the present invention, a display driver circuit includes a pattern generator for generating a reference pattern, a logic circuit for receiving the reference pattern, and an image summing checker for calculating a result for the reference pattern from the logic circuit for verification. Wherein the calculated result adds a log file for determining a pass or fail of the logic circuit or analyzing a failed block in the logic circuit. .

Description

DISPLAY DRIVER INTEGRATED CIRCUIT AND DISPLAY DEVICE HAVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driver integrated circuit, and more particularly, to a display device including a display driving circuit which can test internal logic itself or analyze a generated defect. .

In general, the development of display driver ICs proceeds to the stages of IC design, fabrication, EDS test, and IC sample, and IC (Wafer), ECOF (Film Assembly), Display Module (On Glass), Display driving, testing, verification and failure analysis are carried out in the form of a mobile set. In the case of DDI, the number of input / output pins is much larger than that of other integrated circuits, and there is a limit in reducing the size of input / output pads in order to reduce resistance. That is, the number of pads for test is extremely limited except for the pads for basic driving. If there is a functional or operational problem in the data path in the DDI through these limited test pads, check the design database one by one unless the state of the internal signal is checked. It will take a long time and effort to identify the cause of the problem until you find it.

In addition, data input pads for basic display driving also have a lot of limitations in driving high speed according to input / output (I / O) performance, and the actual speed in increasing display resolution and driving speed over Full HD (high-density) Real Speed) is reaching the untestable area.

It is an object of the present invention to provide a display driving circuit which can test internal logic circuits by itself or analyze the generated defects.

Further, another object of the present invention is to provide a display device including the display driving circuit.

In order to achieve the above object, a display driver circuit according to an embodiment of the present invention receives image data from a host, and includes a logic circuit including a plurality of intellectual properties (IP) and a result for the image data from the logic circuit. And an image summing checker for calculating a; and, as a result of the calculation, the image summing checker is a log file for determining a pass or fail of the logic circuit or analyzing a failed IP among a plurality of IPs. Provide a (log file).

The image generator may further include a pattern generator configured to generate a reference pattern for verifying the logic circuit, wherein the image summing checker calculates a result of the reference pattern from the logic circuit.

According to an embodiment, the display device may further include a selection circuit configured to output one of the image data and the reference pattern, wherein the selection circuit is implemented as a multiplexer.

According to an embodiment, the pattern generator may include an all black pattern, an all white pattern, a 1X1 check pattern, a 2X2 check pattern, a 4X4 check pattern, an 8X8 check pattern, and a column rainbow. Pattern, page rainbow pattern, 0-255 gray page pattern, 0-239 gray column pattern, 20% black & 80% white pattern, 1 (line) X1 (line) pattern, 2 (line) X2 (line) pattern, crosstalk A pattern, crosstalk B pattern, crosstalk C pattern, and flicker pattern.

The memory device may further include a memory device that stores the image data, wherein the memory device is implemented as a graphic random access memory.

According to an embodiment, the logic circuit includes an image processor for processing the image data into image information, and the image processor includes an image processing unit A, an image processing unit B, and an image processing unit C.

According to an embodiment, each of the image processing unit A, the image processing unit B, and the image processing unit C may receive one of the image signal or the reference pattern, and the image summing checker may include the image processing unit A, An output is computed from each of the image processing unit B and the image processing unit C, and a look-up table is compared with the calculated result.

According to an embodiment, the lookup table includes simulated results of each of the image processing unit A, the image processing unit B, and the image processing unit C.

A display apparatus according to another embodiment of the present invention includes a display panel and a display driver circuit for driving the display panel, wherein the display driver circuit receives image data from a host and receives a plurality of IPs (Intellectual Property). And an image summation checker for calculating a result for the image data from the logic circuit, wherein the computed result, the image summation checker, passes a pass or fail of the logic circuit. Provide a log file for determining or analyzing a failed IP among a plurality of IPs.

The display driver may further include a pattern generator that generates a reference pattern for verifying the logic circuit, and the image sum checker calculates a result for the reference pattern from the logic circuit.

The display device according to an embodiment of the present invention can increase fault coverage.

1 is a block diagram illustrating a display apparatus 100 according to an exemplary embodiment.
2A and 2B are block diagrams illustrating a typical display data path.
3A and 3B are block diagrams illustrating the display driver circuit shown in FIG. 1.
4 is a block diagram illustrating the ISCU shown in FIG. 3.
5A through 5Q are block diagrams illustrating test patterns stored in the RPG shown in FIG. 3.
6 is a flowchart illustrating an operation of a display driver circuit according to a second exemplary embodiment of the present invention.
7 is a flowchart illustrating an operation of a display driver circuit according to a third exemplary embodiment of the present invention.
FIG. 8 illustrates an embodiment of a computer system 210 including the display apparatus 100 shown in FIG. 1.
FIG. 9 illustrates another embodiment of a computer system 220 including the display apparatus 100 shown in FIG. 1.
FIG. 10 illustrates another embodiment of a computer system 230 including the display device 100 shown in FIG. 1.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing the embodiments of the present invention, the embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the described embodiments.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that the disclosed feature, number, step, operation, component, part, or combination thereof exists, but one or more other features or numbers, It is to be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment may be implemented differently, a function or operation specified in a specific block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a display apparatus 100 according to an exemplary embodiment.

Referring to FIG. 1, a display apparatus 100 according to an exemplary embodiment of the present invention includes a display driver integrated circuit 10 and a display panel 20. The display driver circuit 10 may receive image data transmitted from the host 50 (eg, an application processor) through the host interface 30. The display driver circuit 10 may drive the display panel 20 based on the input image data to display a 2D image corresponding to the image data input on the display panel 20. The display driver circuit 10 may also communicate with the host 50 for input and output of image data through the host interface 30.

The display panel 20 is a display unit for displaying an actual image, and includes a thin film transistor-liquid crystal display (TFT-LCD), an organic light emitting diode (OLED), and a field emission display The display device may be one of a display device that displays an 2D image by receiving an image signal that is electrically transmitted, such as a filed emission display and a plasma display panel (PDP).

The display driver circuit 10 may include a logic circuit 11, a memory device 12, a source driver 13, a gate driver 14, a power supply 15, and a regulator 16. The logic circuit 11 may include an image processor, a memory controller for controlling the memory device 12, and a plurality of intellectual properties (IPs) implementing the controller. The logic circuit 11 according to the embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

The image data may be stored and utilized in the memory device 12. In addition, the image data is transmitted to the source driver 13 and the gate driver 14, so that the display panel 20 will display the image signal.

The source driver 13 will apply a signal voltage to each pixel. That is, when the gate driver 14 applies a pulse to the gate of the display panel 20 to turn on the source driver 13, the source driver 13 receives the voltage required by the pixel on the display panel 20 through the data line. Would approve. In general, an analog source driver for directly applying an analog voltage is mainly used, whereas in recent years, a digital source driver 13 will be mainly used. The digital source driver 13 may have an advantage of minimizing the influence of noise during signal processing, easily modifying a signal using a logic gate, and the like, and easily storing a signal in a memory. The digital source driver 13 converts the digital image signal into a corresponding gray voltage and applies it to each pixel electrode of the display panel 20. That is, the source driver 13 converts the image data in the digital format into the image pixel voltages and applies them to the signal wiring.

The gate driver 14 generates a voltage to be applied to the gate electrode corresponding to each pixel of the display panel 20 and applies it to the gate wiring. The wiring to which the turn-on signal should be applied to the gate is sequentially selected to apply the corresponding voltage. The gate driver 14 may be implemented as a circuit having a plurality of output terminals, and in general, the number of the output terminals will be determined according to the resolution of the display panel 20. As the resolution of the display panel 20 increases, the gate driver 14 may be implemented by connecting a plurality of drivers in parallel. The output signal will be in the form of a pulse that is made up of two levels of voltage: turn-on voltage and turn-off voltage.

At any point in time, the output state of each of the output terminals may be output at the turn-on voltage only at one output terminal, and at the other output terminals. That is, at any point in time, only the image pixels of the display panel 20 connected to one gate line will be turned on and the image pixels of the display panel 20 connected to the other gate lines will be turned off. That is, the gate driver 14 sequentially selects the gate wiring and applies the scan scan signal. When the gate driver 14 turns the image pixel on by selecting the scan line and applying a scan pulse, the source driver 13 will apply a signal voltage to each image pixel through the signal line.

The memory device 12 may be implemented as a random access memory as a memory device for storing image data input to the source driver 13. In an embodiment, the memory device 12 may be implemented with a graphic RAM. The size of the memory device 12 will vary depending on the resolution of the display device and the number of colors that can be represented per pixel.

The logic circuit 11 accesses the memory device 12, and the image data stored in the memory device 12 may be input / output to the host 50 through the host interface 40. The display driver circuit 10 will be in data communication with the host 50 via the host interface 40.

The display driver circuit 10 and the display panel 20 will be mounted on a flexible printed circuit board (FPCB) 30.

The display driver circuit 10 will transmit the first level interface signal LV1 to the host 50. Alternatively, the host 50 may transmit the first level interface signal LV1 to the display driver circuit 10. In addition, the display driver circuit 10, the display panel 20, and the FPCB 30 will transmit and receive a second level interface signal LV2.

In general, the display driver IC (DDI) is limited to about 3 to 4 for monitoring internal signals such as backlight control (BC), serial data output (SDO), display tearing effect monitor (TE), and internal oscillator clock (OSC). Through the two output pins, the required signal could be monitored. In addition, due to the limited output, a signal monitor in byte units or a large amount of signals could not be monitored in real time.

Even if the number of output pads for the internal signal monitor is increased, the information of the data path operating at 100 MHz or more inside the DDI in real time by the output I / O performance of the output stage is real time. Can't monitor In addition, even if expensive equipment such as a logic analyzer is used, the limitation of output pin number for the internal signal monitor is limited in verifying the driving and analyzing the failure.

The DDI has a register read function, but the register read will be read at a low speed through the serial interface. In addition, read data is output only in the vertical porch section of the display driving section, so there is a limit to the real-time monitor in horizontal units. In the process of failure analysis during mass production, it is difficult to determine whether the problem is a logic circuit or a gamma and source block.

During test, verify or failure analysis, the engineer will check the internal state of the display driver circuit 10 in real time without expensive read-related equipment. The status of the IC internal display data path can be checked at each development step of the IC unit, the ECOF film, the display module, the mobile set, and the like.

The display driver circuit 10 according to an embodiment of the present invention includes an image pattern generator function therein, and compares each image IP output result value according to previously determined image patterns with a previously known expected value. Will be verified. That is, the display driver circuit 10 may include a built-in self test (BIST) for testing the internal circuit itself.

2A and 2B are block diagrams illustrating a typical display data path.

1, 2A, and 2B, in general, data DL and clock CL signals transmitted from an application processor AP are converted into a vertical sync (VS), a horizontal sync (HS), a HSSI block, and the like. It will be changed to DD (Display Data [n: 0]), and DE (Data Enable) signals, and transferred to the source driver via an interface control block, a graphics memory block, an image processor, and a source data shift register (SDSR).

The image processor will include an image processing unit A, an image processing unit B, and an image processing unit C.

3A and 3B are block diagrams illustrating the display driver circuit shown in FIG. 1.

1, 3A, and 3B, the logic circuit 11 may include an HSSI block 111, a reference pattern generator (RPG) 112, an interface control block 114, a graphic memory block 115, and an image processing unit. A 116, image processing unit B 117, image processing unit C 118, source data shift register (SDSR) 119, and image suspension check unit (ISCU) 120.

The data and clock transmitted from the application processor 50 are transferred by the HSSI block 111 into VS (Vertical Sync), HS (Horizontal Sync), Display Data [n: 0], and DD (Data Enable) signals. Will change.

The RPG 112 will generate a reference vertical sync (RVS), a reference horizontal sync (RHS), a reference display data [n: 0] (RDD), and a reference data enable (RD).

The selection circuit 113 will output one of the output signals of the HSSI block 111 and the RPG 112.

The output signals selected from the selection circuit 113 are the interface control block 114, the graphics memory block 115, the image processing unit A 116, the image processing unit B 117, the image processing unit C 118 and the SDSR ( It will be sent to the source driver 13 via 119.

The ISCU 120 includes a selection circuit 113, an interface control block 114, a graphics memory block 115, an image processing unit A 116, an image processing unit B 117, an image processing unit C 118, and an SDSR. Will receive output signals from 119. ISCU 120 according to an embodiment of the present invention will be described in detail with reference to FIG.

In addition, the ISCU 120 will receive an EDSV (Expected Data Sum. Value) value, which is a data sum value expected from the RPG 112. In addition, the ISCU 120 may receive a reference pattern gen. Enable (RPGE), a reference pattern selection (RPS), a reference pattern mode (RPM), and a reference pattern period (RPP).

That is, the test pattern generated by the RPG 112 will be passed to the blocks 114-119 within the logic circuit 11. In addition, the output of each of blocks 111-119 will be received by ISCU 120. Thus, blocks 111-119 in logic circuit 11 will be tested. Due to this, the fault coverage of the logic circuit 11 will be improved.

The display driver circuit 10 according to an exemplary embodiment of the present invention transmits and receives data or a clock from the host 50, that is, an application processor. The display data (DD) input from the host 50, that is, the HSSI block 111 by the high speed serial I / F from the application processor, and the reference display data (RDD) input from the RPG 112 are It will be selected by the user according to the test condition.

4 is a block diagram illustrating the ISCU shown in FIG. 3.

3 and 4, the ISCU 120 includes a Test Pattern Sum Calculation (TPSC) 121, a first selection circuit 122, a second selection circuit 123, a third selection circuit 124, and a SEC ( Summation Enable Controller (125), Data Summation Unit (DAU) 126, and XOR gate 127.

The TPSC 121 will output ERDS (expected reference data sum [m: 0]).

The first selection circuit 122 includes a selection circuit 113, an interface control block 114, a graphics memory block 115, an image processing unit A 116, an image processing unit B 117, and an image processing unit C 118. ) And one of the outputs of SDSR 119. The second selection circuit 123 receives red data DR, green DG, and blue of the outputs (Input Data [N: 0]) of the first selection circuit 122 in response to a SCS signal. Will print either (DB). The third selection circuit 124 may output one of an output ID of the first selection circuit 122 and an output of the second selection circuit 123 in response to the control of the SEC 125. .

The DSU 126 will calculate the data sent from the third selection circuit 124. The XOR gate 127 will compare the output of the DSU 126 with the expected reference data sum [m: 0] (ERDS) from TPSC 121. As a result of the comparison, if it is the same, there is no error, otherwise, an error occurs in a specific block in the logic circuit 11. That is, the ISCU 120 will output a valid output comparison flag (VOCF) indicating the pass or fail of the logic circuit 11. In addition, the ISCU 120 will output SRD (Summation Result Data [m: 0]) which is the output of the DSU 126.

The DD input to the ISCU 120 is selected by one of the outputs of each IP Block (e.g., image processing unit A 116, image processing unit B 117, image processing unit C 118) by the user. (Image Block Signal Selection), and data corresponding to one color among DR (Red), DG (Green), and DB (Blue) Data may be selected in the selected DD. (Summation Color Selection).

The selected data may be operated for data summation according to a set Data Summation Period such as VS (Vertical Sync) (Frame unit) and HS (Horizontal Sync) (Line unit).

In addition, while the DSU 126 calculates the data transmitted from the third selection circuit 124, the calculated summation result data (SRD) is transmitted to the HSSI block 111 and read by the user as needed. You will see the display running. In addition, ETSD (Expected Test Sum.Data [m: 0]) generated according to a reference pattern generation condition input from the RPG 112 may be each of the image processing unit A 116 and the image processing unit B 117. And corresponding to the display data passed through the image processing unit C (118) to be compared with SRD (Summation Result Data [m: 0]) to generate one Valid Output Comparison Flag (VOCF). The user reads a Sum Result Result Data [m: 0] (VRD) or a Valid Output Comparison Flag (VOCF) on a set (eg, a display module) to drive a state inside the display driver circuit 10. Can be identified.

The first embodiment of the present invention will also support a built-in self test (BIST) function for image IPs in conjunction with a test pattern generation function.

5A through 5Q are block diagrams illustrating test patterns stored in the RPG shown in FIG. 3.

Referring to FIG. 5A, an all black pattern is shown.

Referring to FIG. 5B, an all white pattern is shown.

Referring to FIG. 5C, a 1 × 1 check pattern is shown.

Referring to FIG. 5D, a 2 × 2 check pattern is shown.

Referring to FIG. 5E, a 4 × 4 check pattern is shown.

Referring to FIG. 5F, an 8 × 8 check pattern is shown.

5G, a column rainbow pattern is shown.

Referring to FIG. 5H, a page rainbow pattern is shown.

Referring to FIG. 5I, a 0 to 255 gray page pattern is shown.

Referring to Figure 5J, 0-239 gray column pattern is shown.

Referring to FIG. 5K, a 20% black, 80% white pattern is shown.

Referring to Figure 5L, a 1 (line) X 1 (line) pattern is shown.

Referring to FIG. 5M, a 2 (line) X2 (line) pattern is shown.

Referring to FIG. 5N, a crosstalk A pattern is shown.

Referring to FIG. 5O, a crosstalk B pattern is shown.

Referring to FIG. 5P, a crosstalk C pattern is shown.

Referring to FIG. 5Q, a flicker pattern is shown.

6 is a flowchart illustrating an operation of a display driver circuit according to a second exemplary embodiment of the present invention.

Referring to FIG. 6, an image processor of the present invention will include an image processing unit A 116, an image processing unit B 117, and an image processing unit C 118.

In step S11, the image processing unit A 116, the image processing unit B 117, and the image processing unit C 118 will all be driven. That is, image processing unit A 116, image processing unit B 117, and image processing unit C 118 will receive an image signal or test pattern.

In step S12, the ISCU 120 will receive the output of each of the image processing unit A 116, the image processing unit B 117, and the image processing unit C 118. The ISCU 120 will then compute each of the received outputs.

In operation S13, a calculation operation to be executed in the ISCU 120 is performed through simulation.

In step S14, the result calculated through the simulation is compared with the result calculated from the ISCU 120.

In step S15, the comparison result is analyzed. That is, as a result of the comparison, if identical, each of the image processing unit A 116, the image processing unit B 117, and the image processing unit C 118 are all verified. Otherwise, a failure has occurred in any one of the image processing unit A 116, the image processing unit B 117, and the image processing unit C 118. If a fail occurs, it will find the block where the fail occurred and perform debugging.

In addition, in order to alleviate this inconvenience, it may be extended in a manner that is associated with a test pattern generation function inside the IC (ie, the display driver circuit 10).

7 is a flowchart illustrating an operation of a display driver circuit according to a third exemplary embodiment of the present invention.

Referring to FIG. 7, in step S21, the image processing unit A 116, the image processing unit B 117, and the image processing unit C 118 will all be driven. That is, image processing unit A 116, image processing unit B 117, and image processing unit C 118 will receive an image signal or test pattern.

In step S22, the RPG 112 will be executed. That is, the RPG 112 will generate a reference test pattern. In an exemplary embodiment, the RPG 112 may include an all black pattern, an all white pattern, a 1 × 1 check pattern, a 2 × 2 check pattern, a 4 × 4 check pattern, an 8 × 8 check pattern, and a column rainbow. Pattern, page rainbow pattern, 0-255 gray page pattern, 0-239 gray column pattern, 20% black & 80% white pattern, 1 (line) X1 (line) pattern, 2 (line) An X2 (line) pattern, a crosstalk A pattern, a crosstalk B pattern, a crosstalk C pattern, and a flicker pattern will be generated.

In step S23, the ISCU 120 will receive the output of each of the image processing unit A 116, the image processing unit B 117, and the image processing unit C 118. The ISCU 120 will then compute each of the received outputs.

In operation S24, a calculation operation to be executed in the ISCU 120 is executed through simulation, and the result is stored in a look-up table.

In operation S25, the result calculated from the ISCU 120 is compared with the lookup table.

In step S26, the comparison result is analyzed. That is, as a result of the comparison, if identical, each of the image processing unit A 116, the image processing unit B 117, and the image processing unit C 118 are all verified. Otherwise, a failure has occurred in any one of the image processing unit A 116, the image processing unit B 117, and the image processing unit C 118. If a fail occurs, it will find the block where the fail occurred and perform debugging.

That is, by using the test pattern generator RPG 112 inside the display driver circuit, each IP (Intellectual Property) output of specific patterns (for example, an image processor, among a plurality of IPs) is output in the form of a look-up table (LUT). Will save to IC in advance.

In the analysis step, the test pattern function and the image summation check function can be turned on at the same time to automatically compare the image IP output values in the display driver circuit and check only the result.

As a result checking method, a method of reading a 1 bit register value from the host 50 (ie, an application processor) may be possible. It would also be possible to monitor via an output pad such as TE. In other words, when the BIST (Built-in Self Test) function is used, a separate simulation time is not required, so the state inside the display driving circuit can be checked quickly and immediately.

When the EDS test is performed in the unit state of the display driver circuit 10, the mobile device may be configured by predefined patterns output from the RPG 112 regardless of the external input / output (I / O) state or performance. Set It will be possible to verify the data path beyond the actual operating speed at the level.

In the display module state, it is possible to quickly and easily determine in which part of the display module a problem occurs when analyzing a screen defect or a driving circuit defect.

Built-in self test (BIST) is possible through the built-in RPG 112, and this enables at least a data path in a digital circuit even without performing a single digital logic simulation for failure analysis. Path will automatically check if there is a problem.

FIG. 8 illustrates an embodiment of a computer system 210 including the display device 100 shown in FIG. 1.

Referring to FIG. 8, the computer system 210 may include a memory device 211, a memory controller 212 controlling a memory device 211, a wireless transceiver 213, an antenna 214, an application processor 215, and an input. Device 216 and display device 217.

The radio transceiver 213 may transmit or receive a radio signal through the antenna 214. For example, the wireless transceiver 213 may convert the wireless signal received through the antenna 214 into a signal that can be processed by the application processor 215.

Accordingly, the application processor 215 may process a signal output from the wireless transceiver 213 and transmit the processed signal to the display device 217. In addition, the wireless transceiver 213 may convert a signal output from the application processor 215 into a wireless signal and output the changed wireless signal to an external device through the antenna 214.

The input device 216 is a device capable of inputting a control signal for controlling the operation of the application processor 215 or data to be processed by the application processor 215. The input device 216 may include a touch pad and a computer mouse. It may be implemented as a pointing device, a keypad, or a keyboard.

According to an embodiment, the memory controller 212 capable of controlling the operation of the memory device 211 may be implemented as part of the application processor 215 and may be implemented as a chip separate from the application processor 215. .

According to an embodiment, the display device 217 may be implemented with the display device 100 shown in FIG. 1.

FIG. 9 illustrates another embodiment of a computer system 220 including the display apparatus 100 shown in FIG. 1.

Referring to FIG. 9, a computer system 220 includes a personal computer, a network server, a tablet PC, a net-book, an e-reader, a PDA. (personal digital assistant), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The computer system 220 may include a memory controller 222, an application processor 223, an input device 224, and a display device 225 that may control data processing operations of the memory device 221 and the memory device 221. Include.

The application processor 223 may display the data stored in the memory device 221 through the display device 225 according to the data input through the input device 224. For example, the input device 224 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The application processor 223 may control the overall operation of the computer system 220 and may control the operation of the memory controller 222.

According to an embodiment, the memory controller 222 that can control the operation of the memory device 221 may be implemented as part of the application processor 223, or may be implemented as a chip separate from the application processor 223.

According to an embodiment, the display device 225 may be implemented with the display device 100 shown in FIG. 1.

FIG. 10 illustrates another embodiment of a computer system 230 including the display device 100 shown in FIG. 1.

Referring to FIG. 10, the computer system 230 may be implemented as an image processing device, such as a digital camera or a mobile phone with a digital camera, a smart phone, or a tablet. .

The computer system 230 includes a memory controller 232 that can control data processing operations, such as a write operation or a read operation, of the memory device 231 and the memory device 231. In addition, the computer system 230 further includes an application processor 233, an image sensor 234, and a display device 235.

Image sensor 234 of computer system 230 converts the optical image into digital signals, and the converted digital signals are sent to application processor 233 or memory controller 232. Under the control of the application processor 233, the converted digital signals may be displayed through the display device 235 or stored in the memory device 231 through the memory controller 232.

In addition, the data stored in the memory device 231 is displayed through the display device 235 under the control of the application processor 233 or the memory controller 232.

According to an embodiment, the memory controller 232 capable of controlling the operation of the memory device 231 may be implemented as part of the application processor 233 or may be implemented as a separate chip from the application processor 233. .

According to an embodiment, the display device 235 may be implemented with the display device 100 shown in FIG. 1.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The present invention is applicable to a display device including a display driver integrated circuit that can test the internal logic circuit itself.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

10: display driver integrated circuit
20: display panel
30: FPCB
40: host interface
100: display device
210, 220, 230: computer system according to an embodiment of the present invention

Claims (10)

A logic circuit that receives image data from a host and includes a plurality of Intellectual Properties (IP);
A pattern generator for generating a reference pattern for verifying the logic circuit; And
Computing a result for the reference pattern from the logic circuit, and comparing the calculated result with the simulation result for the reference pattern to determine the pass or fail of the logic circuit or a plurality of IPs. Display driver circuitry comprising an image summing checker that provides a log file for analyzing the failed IP. The method of claim 1,
The simulation result is stored in advance in a look-up table,
And the image sum checker compares the calculated result with the simulation result stored in the look-up table. The method of claim 1,
A selection circuit for outputting any one of the image data or the reference pattern,
And the selection circuit is implemented as a multiplexer. The method of claim 1,
The pattern generator includes an all black pattern, an all white pattern, a 1X1 check pattern, a 2X2 check pattern, a 4X4 check pattern, an 8X8 check pattern, a column rainbow pattern, a page ) Rainbow Pattern, 0 ~ 255 Gray Page Pattern, 0 ~ 239 Gray Column Pattern, 20% Black & 80% White Pattern, 1 (line) X1 (line) Pattern, 2 (line) X2 (line) Pattern A display driver circuit comprising a crosstalk A pattern, a crosstalk B pattern, a crosstalk C pattern, and a flicker pattern. The method of claim 3, wherein
Further comprising a memory device for storing the image data,
The memory device is a display driver circuit implemented with a graphic random access memory (RAM). The method of claim 3, wherein
At least one of a plurality of IPs (Intellectual Property) of the logic circuit is an image processor for processing the image data as image information,
And the image processor includes an image processing unit A, an image processing unit B, and an image processing unit C. The method of claim 6,
Each of the image processing unit A, the image processing unit B, and the image processing unit C receives one of the image data or the reference pattern,
And the image sum checker computes an output from each of the image processing unit A, the image processing unit B, and the image processing unit C, and compares the calculated result with a look-up table. The method of claim 7, wherein
And the lookup table includes simulated results of each of the image processing unit A, the image processing unit B, and the image processing unit C. Display panel; And
A display driver circuit for driving the display panel,
The display driver circuit
A logic circuit that receives image data from a host and includes a plurality of Intellectual Properties (IP);
A pattern generator for generating a reference pattern for verifying the logic circuit; And
Computing a result for the reference pattern from the logic circuit, and comparing the calculated result with the simulation result for the reference pattern to determine the pass or fail of the logic circuit or a plurality of IPs. A display device comprising an image summation checker that provides a log file for analyzing failed IPs. The method of claim 9,
The simulation result is stored in advance in a look-up table,
And the image sum checker compares the calculated result with the simulation result stored in the look-up table.

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