KR102060358B1 - Method and system for timing synchronization at sub-sampled rate for sub-sampled wideband systems - Google Patents

Abstract

A method and system for synchronizing timing at a sub-sampled rate of a sub-sampled wideband system is disclosed. This method provides a high synchronization probability timing synchronizer to obtain a better channel estimate. Synchronizers provide a mixed mode solution by providing precision estimation with coarse estimation in the digital domain and correction in the analog domain. The method also provides a design of a training sequence that enables parameter estimation at a sub-sampled rate.

Description

METHOD AND SYSTEM FOR TIMING SYNCHRONIZATION AT SUB-SAMPLED RATE FOR SUB-SAMPLED WIDEBAND SYSTEMS}

The description below relates to broadband wireless communication, and more particularly to estimating the timing of a wideband signal at a sub-sampled rate in a low power ultra wideband (UWB) system.

Broadband communications are becoming important in future wireless communications because of the possibility of supporting extremely high data rates of gigabytes per second. Considering the wide bandwidth involved, power consumption is a very important issue in broadband systems. The development of low power, low cost and low interference wideband transceivers has enormous commercial demands. The concept of sub-banding has recently been developed for broadband systems. This concept can save power in ultra wideband (UWB) systems.

Some technologies based on personal area networks (PANs) use this band to make applications that can achieve high data communication rates. In the method of sub-banding, a given 500 MHz (or higher) bandwidth is equally divided into 'N' sub-bands. These 'N' sub-bands allow multiple users access to the channel bandwidth, use different sub-bands for different data streams being transmitted, increase data communication rates, and Other sub-bands can be used to improve communication performance.

In a sub-band ultra wideband (S-UWB) system, the transmitting device comprises a plurality of sub-band signal generators and based on a plurality of determined parameters. Generate a band signal, where each of the plurality of sub-band signals comprises a modulated bit stream spread using a spreading code. Also, at the receiver side, the receiving device of the sub-band ultra wideband (S-UWB) communication system receives an analog front to receive an S-UWB signal comprising a plurality of sub-band signals from the transmitting device over the UWB channel. An analog front end, where each of the plurality of sub-band signals includes a modulated bit stream spread using a spreading code. The receiving apparatus also includes a sampler to sample the S-UWB signal at a rate of sub-band bandwidth. Energy savings are due to base-band processing at a sub-sampling rate that eliminates the need for higher sampling rate ADCs used in full band systems.

According to one side, a method for timing synchronization in a sub-band based ultra wideband (UWB) system, comprising: obtaining a coarse estimate of an offset in the time domain at a sub-sampled rate It may include. The method can also obtain a precise estimate of the offset in the analog domain. The method can then correct the timing in the analog domain by converting the coarse and fine estimates in the equivalent phase for correction.

According to one side, the receiver for timing synchronization in a sub-band based ultra wideband (UWB) system, a phase locked loop (PLL) circuit, an analog-to-digital converter (ADC) a digital converter and an analog delay circuit. In addition, the receiver may further include an integrated circuit. The integrated circuit may include a processor and a memory having computer program code. The computer program code and the at least one memory in conjunction with the at least one processor allow the receiver to obtain a coarse estimate of the offset in the time domain at a sub-sampled rate. The receiver allows to obtain a precise estimate of the offset in the analog domain. The receiver then corrects the timing in the analog domain by converting the coarse and fine estimates in the equivalent phase for correction.

Many aspects of the embodiments will be better understood upon consideration of the following description and the annexed drawings. However, while the following description describes various embodiments and many specific details, the following description is presented for purposes of illustration and should not be construed as limiting. Many changes and modifications may be made without departing from the technical spirit described by the embodiments, and the embodiments include all such changes and modifications.

Hereinafter, the embodiments will be described with the accompanying drawings using reference numerals indicating corresponding components in various drawings. Embodiments described herein may be better understood from the following description with reference to the drawings.
1 is a block diagram illustrating a method of synchronizing timing according to one embodiment.
2 illustrates a block diagram for fine timing synchronization according to one embodiment.
3 illustrates an example analog delay circuit for fine timing synchronization, according to one embodiment.
4 is a graph showing a comparison of the bit error rate and signal to noise ratio of an OFDM based S-UWB system for timing synchronization at 100 MHZ and 1 GHZ over a UWB channel, according to one embodiment.
FIG. 5 is a graph illustrating a comparison of a bit error rate and a signal-to-noise ratio of an OFDM-based S-UWB system for timing synchronization at 1GHZ and 100MHZ over a UWB channel according to an embodiment.
6 illustrates a method of training sequence design for timing synchronization with sub-sampled bandwidth according to one embodiment.
7 illustrates a frame format diagram of an OFDM-based S-UWB according to an embodiment.

The embodiments and the various configurations of the embodiments are more fully described with reference to the non-limiting embodiments described in detail in the accompanying drawings and the description below. Descriptions of well-known components and processing techniques have been omitted so as not to unnecessarily obscure the embodiments. The examples used herein are intended to enable embodiments to be practiced, and also to enable those skilled in the art to practice the embodiments. Accordingly, the examples should not be construed as limiting the scope of the embodiments.

Embodiments described herein achieve a method and system for synchronizing timing at a sub-sampled rate of a sub-sampled ultra wideband system (UWB). This method and system provide a high synchronization probability synchronizer to obtain a better channel estimate.

The method of timing synchronization follows a mixed mode design. Initially, the estimation is performed in the digital domain at a sub-sampled rate (100 MHZ) after the analog-to-digital converter (ADC) and the compensation is performed via a 500 MHZ real-time analog signal. In addition, the estimated timing information is fed back into a fractional phase locked loop (PLL) to control the phase of the ADC sampling clock as a result of the correction of the sampling time. The method of timing synchronization requires a suitable training sequence to take care of rate mismatch between estimation and compensation in the digital and analog domains, respectively.

According to one embodiment, the training sequence is a band limited to the sub-sampled bandwidth.

1 is a block diagram illustrating a method of synchronizing timing according to one embodiment. The synchronization method includes two steps. In the first step, the estimation of the offset is completed and in the next step the compensation of the signal in the estimation is performed. The method of timing synchronization follows a mixed mode design as described herein.

Estimation of the offset is performed in the digital domain at a sub-sampled rate (100 MHZ) after the analog-to-digital converter (ADC) and compensation is performed via a real-time analog signal of 500 MHZ.

The mixed mode design of timing synchronization is based on a typical training sequence pattern, where silent periods are added to other sub-bands. In addition, a training sequence for timing synchronization is added to the desired band in a preamble section dedicated to the frequency synchronization sequence of the frame. Training sequences for different sub-bands are protected from overlapping each other because of the aliasing effect of sub-sampling.

The receiver system is also assumed to be free from frequency offset errors. The method of timing synchronization involves compensation techniques including mixed mode estimation and processing in both the digital and analog domains. For this reason this involves processing at full rate and sub-sampled rate. The mixed mode design of the timing synchronizer involves estimating the coarse timing offset 101 in each sub-band at a sub-sampled rate, using the analog signal received in the analog domain at full rate. Obtaining three precision timing estimates 102 from the coarse estimate and finally compensating the signal in the analog domain and generating equivalent parameters corresponding to the estimated timing error inputs.

The method of estimating the coarse timing offset 101 in each sub-band separately at the sub-sampled rate is described herein. Initially, coarse estimation 101 is performed in the sub-sampled domain. Consider the following parameters described here.

{S} denotes a transmitted modulated sequence over a time-dispersive UWB fading channel and is given by Equation (1).

{h _b } is called a complex base band equivalent to the UWB channel coefficient applied to the band 'b' of the P order, and is given by Equation 2 below.

}는 UWB 수신기 프론트 엔드로 수신되는 컴플렉스 샘플 시퀀스(complex sample sequence)에 대응하는 것을 나타내고, 수학식 3과 같이 나타난다.
{

} Corresponds to a complex sample sequence received at the UWB receiver front end, and is represented by Equation 3 below.

'N _S ' is also the total number of samples in each OFDM symbol in the transmitted preamble. Then, after the sub-sampling, the nth received sample of the first OFDM symbol duration is expressed as Equation (4).

Where w (l, n) is the additive white Gaussian noise (AWGN) associated with the nth sample of the first OFDM symbol, D is the total number of sub-bands, and 'L' is the timing The number of training symbols of length 'N _S ' dedicated to synchronization, q _b is the timing offset associated with the 'b th' sub-band channel. The timing offset q _b is different from other sub-band channel responses.

Assuming packet detection is complete, the timing synchronization method aims to estimate the start of the first frequency synchronization sequence of the preamble, in particular the start of its FFT window.

Equation 4 shows that each sub-band signal is shifted in a fast fourier transform (FFT) window depending on the corresponding timing delay " q _b " contributed by the sub-band channel. To experience a different amount of). However, the sample y (l, n) received because of the sub-sampling experiences some equivalent offset effect of all the sub-bands.

This embodiment estimates the timing offset of a full band channel from the estimation of each band offset at a sub-sampled rate. This requires proper design of the training sequence to avoid overlapping of sub-bands in the sub-sampled domain. This is confirmed by the silent period based training design. For this reason, with the training part of the preamble, with the first sub-sampled OFDM symbol transmitted over sub-band 1, equation (4) is modified to equation (5).

, 과 크로스 코릴레이트 된다. 서브-밴드 'b' C_b(l,n) 에 대응하는 1번째 OFDM 심볼 n번째 샘플의 크로스 코릴레이트된 출력은 수학식 6과 같이 획득된다.
The received sample of Equation 5 in the digital domain is a known training sequence, e.g. a preamble pattern which is a band limited to the sub-band bandwidth.

, And cross correlated. The cross correlated output of the 1 st OFDM symbol n th sample corresponding to the sub-band 'b' C _b (l, n) is obtained as shown in Equation (6).

은 아래의 수학식 7을 사용하는 모든 서브-밴드를 통해 코릴레이션 피크(correlation peak)를 지적하는 최대 지연을 찾음으로써 획득된다.
* Indicates a complex conjugate operation. Inaccurate estimation

Is obtained by finding the maximum delay that points to the correlation peak through all sub-bands using Equation 7 below.

Equation 7 above determines the instant of maximum delayed multipath with significant energy of the full band channel as shown by the sub-sampled window.

내에 놓여 있다.The main part of the full band channel energy is an equivalent extended version of the coarse estimation

Lies within.

The method of precision estimation 102 by a timing synchronizer is described herein. The synchronizer estimates the fine timing offset at high sampling rates in the analog domain. The precision estimator block receives the coarse timing estimation feedback from the digital domain and the received analog signal delayed from the analog delay circuit after proper scale up. The analog signal is delayed to introduce delay due to coarse timing estimation, extension, and latency in the feedback path. The delayed signal is stored in a buffer. The method of fine timing estimation is described in FIG.

When the coarse estimation 101 and the fine estimation 102 have been made, the timing correction 103 is performed by a synchronizer in the steps described herein. Timing offset correction 103 is performed in the analog domain at a higher rate once the rest of the preamble begins to arrive.

The timing correction 103 is obtained by changing the sampling clock phase of the analog-to-digital converter ADC as a result of the change in the sampling time for the next portion of the frame.

The estimated fine timing offset is input to a fractional phase locked loop (PLL) to produce an equivalent phase. The timing buffer controls the switching of the ADC clock from the initial phase to the estimated phase in accordance with a predefined timing delay. The flow of signals at the receiver during estimation and compensation is controlled by two switches. In the figure, the switch at position 1 shows the corresponding position of the switch during the estimation and correction phase.

The switch is coupled to position 1 until coarse 101 and fine timing estimation 102 and the equivalent ADC clock phase are estimated. Both switches are then moved to position 2 to compensate for the timing offset and feed the signal to the FFT after sub-sampling.

According to one embodiment, the method of timing synchronization can also be achieved by sufficiently obtaining coarse and precise estimates in the digital domain. There are some applications of sub-sampled orthogonal frequency division multiplexing (OFDM) based S-UWB systems, where synchronization can only be performed in the digital domain by avoiding the complexity of the analog domain. have. Embodiments for achieving timing synchronization in the digital domain are described in the following case herein.

In one case, Quality of Service (QoS) is achieved by on-the-fly code diversity instead of frequency, and the same data of the user is sent to another orthogonal code in one sub-band to achieve diversity gain. And for this reason QoS performance (eg BER performance) is improved.

Sub-bands are used to improve the data rate for one user in a network or to support multiple users. In this scenario, all signals of a particular sub-band will experience the same timing offset and for this reason the same amount of shift in the FFT window estimated in the coarse estimate 101.

This estimation can be improved by putting the threshold at the correlation output. The predefined threshold may be a function of root mean square (RMS) delay spread of the full band channel. The correction can be performed immediately in the sub-sampled domain in digital by shifting the sequence. This method eliminates the need for precise time estimation 102 and correction 103. This method also provides fast estimation compared to mixed mode solutions for timing synchronization.

If the signal is transmitted in a diversity order of 1 along the sub-band, the signal is not automatically added up after de-spreading by the orthogonal code. Orthogonal codes cancel the effect of interference of all other codes assigned to the unwanted sub-bands.

Similarly, at a diversity order of two, along the frequency axis, precise estimation can be performed entirely in the digital domain and the compensation can be performed in the analog domain according to the method described in Case 1.

Also in another case, in parallel processing for diversity along frequency, the digital solution is provided by providing precise timing estimation and timing correction, channel estimation and individual correction for each sub-band signal. Then, the sub-band signal involved to achieve diversity is added after de-spreading and input to the demodulator. This process increases complexity in proportion to diversity orders.

2 illustrates a block diagram for fine timing synchronization according to one embodiment. The delayed signal is cross correlated with the analog template of the same training sequence, which is used for coarse timing estimation in digital after appropriate expansion. In analog, a correlation operation is performed in two steps as described below.

Initially, the buffered signal is passed through analog delay circuits and analog integrators that give a 1 / B (B = full bandwidth) delay resolution. At a channel bandwidth of 500 MHz, 2 nsec delay resolution is required.

The input, which is a delayed analog signal, is multiplied by the training sequence and input to the analog integrator to obtain a correlated output as shown in Equation (8).

Normalized correlation peaks in the low delay spread channel give a precise estimate. In high delay spread channels, initial correlation peaks may be utilized to correct timing errors in the incoming signal.

은 코릴레이터 출력(correlator output)

와 임계치를 비교함으로써 획득된다.

은

≥λ 일 때의 순간을 나타낸다.After channel estimation in the digital domain, the channel delay spread is calculated and fed back to a threshold selector block. Because of the delay spread of the other UWB channel models, the predefined threshold λ is fed back to the analog domain in the precision estimation block and selected. Precision estimation

Is the correlator output

Is obtained by comparing the threshold with.

silver

It represents the moment when ≥λ.

3 illustrates an example analog delay circuit for fine timing synchronization, according to one embodiment. The compact circuit shown in the figure provides a controllable analog delay that can be accurately predicted if an OPAMP of wide bandwidth is selected. With a given value of resistance (95.3 ohms) and capacitor (63 picofarads), a delay of (63 × 10 ⁻¹² ) * (95.3 × 2) equivalent to nearly 12 nsec can be generated. OPAMP integrators that can handle 500MHz wide signals are also possible by using ICs such as the AD 8045 and AD 8099.

4 is a graph illustrating a comparison of the bit error rate and the signal-to-noise ratio of an OFDM-based S-UWB system for timing synchronization at 100MHZ and 1GHZ over a UWB channel according to one embodiment. The system's BER performance is shown in the figure for timing synchronization of diversity orders ranging from 1 to 5.

The performance of the disclosed timing synchronization method is evaluated through simulation of BER performance or OFDM based SUWB system. The simulation parameters considered for simulation analysis are tabulated in Table 1. The performance of the 100 MHz synchronizer is also compared with the 1 GHz synchronizer to calculate the estimated loss in the sub-sampled domain. Performance is obtained through the IEEE 802.15.4 channel model CM3, which is considered a low delay spread channel for an effective delay spread of 11 nsec.

Sr. No Simulation parameters Value / type One UWB Bandwidth (B) 500 MHz 2. Number of sub-bands (N) 5 3 Sub-sampling rate 100 MHz 4 Chip Duration / Sampling Time 10 ns 5 FFT size 32 6 CP length 10 7 OFDM code duration 420 ns 8 Data subcarriers 32 9 Spreading code Walsh Hadamard (WH) 10 Spread Cord Length (P) 8 11 Modulation type BPSK 12 Coding Uncoded 13 Payload 350 OFDM symbols / frame 14 Data rate 54 Mbps (with diversity 5) 15 channel IEEE 802.15.4,
CM3 (RMS delay = 11nsec)

The basic training sequence contemplated for the simulation is a 31 length m-sequence and a 42 length complex chirp sequence padded to 1 to create an even sequence. Only one basic sequence for the sub-band is transmitted to aid in timing estimation at the receiver. Performance has been demonstrated through comparison of both sequences. Both sequences are simulated in various frequency diversity orders from 1 to 4.

The time synchronized signal is input to the despread block after the frequency domain transformation. After despreading, channel estimation is performed with a least square method. The signal is detected after equalization.

The simulation assumes perfect frequency synchronization. The symbol information is spread by the 8 length Walsh-Hadamard code. To support diversity, different orthogonal codes are arranged in each sub-band to distinguish the data. The simulation is performed with a single user transmitting the same data across multiple sub-bands to improve BER performance (diversity order ≧ 2) or across other sub-bands that maximize the data rate. Decoding is also performed on subband one. To obtain a sampling rate conversion from 100 MHz to 500 MHz, the training sequence is upsampled, while the data section is interpolated.

The performance of the 100 MHz synchronizer is compared with the performance of peak synchronization to 1 GHz to analyze the estimated loss due to the sub-sampled estimates. For a diversity order of 1, the performance of both rises very closely in performance, matching almost zero errors. As the diversity order increases, the mismatch between 100 MHz and 1 GHz performance also increases. For zero diversity orders, the synchronizer eliminates the dispersion effect because of either sub-band channel and satisfactorily arranges the orthogonal codes before adding in the method of despreading. In the diversity case, SNR loss is observed because of the loss in orthogonality between the same codes associated with different sub-bands. Another reason for SNR loss is contributing to poor filter design in terminal filters. Since the training sequence is designed in the silence period of the domain and precise estimation of timing is performed at higher sampling rates in analogue, it is very unlikely that the major loss in SNR is contributed by the estimation error variance ( unlikely). For this reason, BER performance is confirmed by up sampling instead of interpolation of data sections through analysis of the effect of pulse shaping filters on system performance in the same way as timing synchronization.

FIG. 5 is a graph illustrating a comparison of a bit error rate and a signal-to-noise ratio of an OFDM-based S-UWB system for timing synchronization at 1GHZ and 100MHZ over a UWB channel according to an embodiment. BER performance is shown in the figures when the data portion of the training sequence and frame is up sampled with diversity order 1 and 5. Significant improvement in the SNR is 10dB order 1GHz and 10 compared to the interpolator (interpolator) for the diversity order of the performance 100MHz 1 ^- are observed in the BER of ^3. SNR improvement is even higher compared to BERs <10 ^-3 . In addition, an SNR improvement of 2 dB is also observed in the same BER compared to 100 MHz performance with an interpolator for a diversity order of five. The performance of the 100MHz synchronizer now closely matches that of the 1GHZ performance.

6 illustrates a method of training sequence design for timing synchronization with sub-sampled bandwidth according to one embodiment. Training sequences for the mixed mode timing synchronization method are described herein. Good auto correlation and cross correlation characteristics. The side lobes of the correlation function are in the range 60-70 dB lower than the peak. In addition, the correlation characteristics of the sequence are preserved at both the full rate and the sub-sampled rate.

In addition, the training sequence can be used to calculate the equivalent parameters from the latency period of the coarse estimation in the digital domain, digital and / or analog circuitry on the feedback path from digital to analog, and precision estimation and precision estimation in analog. It is designed in such a way that it can accommodate the analog circuitry it generates.

The base training sequence is transmitted at different timing epochs for estimating the associated timing offset of different sub-bands. In addition, the base training sequence occupies a period of one OFDM symbol. In the entire time period of five OFDM symbols, training symbols of a particular sub-band appear for the duration of one OFDM code and for the remaining time padded to zero.

The training sequences of different bands are designed not to overlap each other in a particular OFDM symbol period, over the entire period of five OFDM symbols. This ensures that the training sequences of each sub-band do not overlap with each other even after sub-sampling at the receiver.

According to one embodiment, a chirp sequence of length 42 is used as a basic sequence in the design of the training sequence. This complex chirp sequence shows good automatic correlation with cross correlation near lag 0 and other lag zeros.

The training sequence is designed to ensure the provision of an accurate estimate of each of these offsets. The design also ensures a means of avoiding inter band interference and inter carrier interference due to timing errors in certain channels.

Furthermore, in terms of high data rate transmission, the training sequence is designed as presenting an efficient bandwidth.

According to one embodiment, to create an efficient bandwidth design, each band's training sequence is transmitted for one OFDM symbol period without any repetition.

When a training sequence has been sent on any particular sub-band, accurate offset estimation in each sub-band is ensured by the silence period of the other band. In addition, another type of cyclically shifted version of the chirp sequence (which confirms orthogonality to the shifted delay), in order to reduce inter sub-band interference due to timing estimation. It can be transmitted with better estimation in high delay spread channels.

According to one embodiment, the same chirp sequence can be utilized for all subbands over a low delay spread channel.

In order to preserve the correlation characteristics of the training sequence at both the full rate and the sub-sampled domains, the bandwidth consuming basic sequence is upsampled to produce a sequence at 500 MHz.

7 illustrates a frame format diagram of an OFDM-based S-UWB according to an embodiment. The training sequence for timing synchronization is added to the desired band in the preamble section dedicated to the frequency synchronization sequence of the frame. When a training sequence is sent on some particular sub-band, accurate offset estimation in each sub-band is ensured by the silence period on the other band.

To make an efficient bandwidth design, each band's training sequence is transmitted in one OFDM symbol period without any repetition. To reduce inter-band interference due to timing estimation, another cyclically shifted version of the chirp sequence (which confirms orthogonality to the shifted delay) can be sent with a better estimate in the high delay spread channel.

The training sequence accommodates the latency of the electrical circuitry that feeds back to the coarse estimate from digital to analog, precise estimates, generation of equivalent phase information, and a silent period of four OFDM symbol periods as shown in the figure to adjust the ADC clock. Followed by. However, the duration of the silent period can be reduced as the latency of the associated electrical circuit in the future decreases due to the development of device characteristics.

The method of timing synchronization saves power, price and chip area. In addition, this method achieves good performance because of the silent period based on the training sequence design.

The processor, functions, methods, and / or software described above may be recorded on one or more computer-readable recording media including program instructions implemented by a computer to cause a processor to execute or execute program instructions. It can be stored or fixed. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and ROMs, RAMs. Hardware devices specifically configured to store and execute program instructions, such as, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments have been described by the limited embodiments and the drawings as described above, various modifications and variations are possible to those skilled in the art from the above description. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than the described method, or other components. Or even if replaced or substituted by equivalents, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are within the scope of the claims that follow.

Claims (20)

A method for timing synchronization in a sub-band based ultra wideband (UWB) system,
Performing cross correlation of the received sub-sampled signal with the sub-sampled training sequence in the digital domain to obtain a coarse estimate of the offset in the time domain at the sub-sampled rate. step;
Obtaining a fine estimate of the offset in the analog domain; And
Correcting the timing in the analog domain by transforming the coarse estimate and the fine estimate in an equivalent phase for correction
A timing synchronization method in a sub-band based ultra wideband system comprising a. delete The method of claim 1,
Obtaining the coarse estimate separately for each sub-band using a frequency diversity order of the user
The timing synchronization method in a sub-band based ultra wideband system further comprising. The method of claim 3,
A final coarse estimate is obtained from each sub-band by determining the maximum of estimates of the sub-bands.
Timing synchronization method in sub-band based ultra wideband system. The method of claim 4
The final coarse estimate is,
Provided as an input for obtaining the precise estimate in the analog domain
Timing synchronization method in sub-band based ultra wideband system. The method of claim 1,
The precise estimation in the analog domain,
Obtained by performing cross correlation of a delayed signal and a training sequence,
The training sequence for the precision estimation is designed to be a silence period
Timing synchronization method in sub-band based ultra wideband system. The method of claim 6,
The length of the training sequence is,
Equal to the number of orthogonal subcarriers present on the bandwidth of the delayed signal
Timing synchronization method in sub-band based ultra wideband system. The method of claim 6,
The training sequence for obtaining the precise estimate in the analog domain,
An up-sampled version of the base training sequence
Timing synchronization method in sub-band based ultra wideband system. The method of claim 6,
The training sequence of the sub-band,
Orthogonal to the lag gap of an integer,
The lag gap indicates a shift of the sub-bands by the value of the integer.
Timing synchronization method in sub-band based ultra wideband system. The method of claim 6,
The silence period of at least four orthogonal frequency division multiplexing (OFDM) symbols following the training sequence.
Timing synchronization method in sub-band based ultra wideband system. A timing synchronization system for timing synchronization in a sub-band based ultra wideband (UWB) system,
At least one phase locked loop (PLL) circuit;
At least one analog-to-digital converter (ADC); And
At least one analog delay circuit
Including,
The timing synchronization system,
By performing a cross correlation of the received sub-sampled signal with the sub-sampled training sequence in the digital domain, a coarse estimate of the offset in the time domain is obtained at the sub-sampled rate. ,
Obtain a fine estimate of the offset in the analog domain,
Correcting the timing in the analog domain by transforming the coarse estimate and the fine estimate in an equivalent phase for correction
Timing Synchronization System in Sub-Band Based Ultra-Wideband Systems. delete The method of claim 11,
The precise estimation in the analog domain,
Obtained by performing cross correlation of a delayed signal and a training sequence,
The training sequence for the precision estimation is designed to be a silence period
Timing Synchronization System in Sub-Band Based Ultra-Wideband Systems. A receiver for timing synchronization in a sub-band based ultra wideband system,
At least one phase locked loop circuit;
At least one analog-to-digital converter;
At least one analog delay circuit; And
integrated circuit
Including,
The integrated circuit,
At least one processor; And
At least one memory for storing computer program code
Including,
The computer program code and the at least one memory together with the at least one processor are configured to
By performing cross correlation of the received sub-sampled signal with the sub-sampled training sequence in the digital domain, to obtain a coarse estimate of the offset in the time domain at the sub-sampled rate,
Obtain a precise estimate of the offset in the analog domain,
Correcting the timing in the analog domain by transforming the coarse estimate and the fine estimate in an equivalent phase for correction
Receiver for timing synchronization in sub-band based ultra wideband systems. delete The method of claim 14,
Obtaining the coarse estimate separately for each sub-band using a user's frequency diversity order
Receiver for timing synchronization in sub-band based ultra wideband systems. The method of claim 16,
Obtaining a final coarse estimate from each sub-band by determining a maximum of the estimate of the sub-band.
Receiver for timing synchronization in sub-band based ultra wideband systems. The method of claim 17,
The final coarse estimate is,
Provided as an input for obtaining the precise estimate in the analog domain
Receiver for timing synchronization in sub-band based ultra wideband systems. The method of claim 14,
The precise estimation in the analog domain,
Obtained by performing cross correlation of a delayed signal and a training sequence,
The training sequence for the precision estimation is designed to be a silence period
Receiver for timing synchronization in sub-band based ultra wideband systems. The method of claim 19,
The length of the training sequence is,
Equal to the number of orthogonal subcarriers present on the bandwidth of the delayed signal
Receiver for timing synchronization in sub-band based ultra wideband systems.

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