KR102057105B1 - Semiconductor device and operating method thereof - Google Patents

Abstract

The present technology provides a semiconductor device and a method of operating the same that can simultaneously satisfy the opposite characteristics, the semiconductor device according to the present embodiment includes a substrate including a plurality of transistors; And a piezoelectric body formed in contact with the substrate, wherein the piezoelectric body may be formed in a direction parallel to the transistor. In the present technology, by attaching a piezoelectric element to an element, it is possible to form an element that satisfies a low power mode and a high speed mode at the same time depending on whether the piezoelectric material is applied.

Description

Semiconductor device and its control method {SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF}

The present embodiment relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device including a piezoelectric body and a control method thereof.

Generally, when an application such as high speed operation or low power driving is determined, the semiconductor device also needs to have an optimized characteristic corresponding thereto.

For example, even within the same technology, the threshold voltage Vt and the current of the main device may be used for general purpose (GP), low power (LP, low power), or high speed operation (LV, high). device characteristics can be controlled. Also, within each characteristic, the classification is further subdivided into low, medium, standard, high, and ultra high according to threshold voltages, thereby forming devices.

That is, each of the semiconductor devices has a threshold voltage and a current determined according to a required use. When the low power characteristic is selected, the performance drops, and the power consumption is increased to increase the operation speed.

As described above, the semiconductor device according to the related art has a problem in that it is difficult to satisfy all of the characteristics in a trade off relationship.

This embodiment provides a semiconductor device and an operation method thereof that can simultaneously satisfy opposite characteristics.

A semiconductor device according to the present embodiment includes a substrate including a plurality of transistors; And a piezoelectric body formed in contact with the substrate, wherein the piezoelectric body may be formed in a direction parallel to the transistor.

In particular, the substrate may include a semiconductor chip having a packaging process completed. In addition, the substrate may include any one selected from the group consisting of SRAM, Flash, DRAM, Digital Logic, and Converter.

In addition, the substrate may include a device in which the gate electrode of the transistor is fixedly arranged in one direction.

Also, the piezoelectric body may include one material selected from the group consisting of ferroelectric ceramics, piezoelectric single crystal and zinc oxide, the piezoelectric body PZT (Pb (Ti, Zr) O 3, titanate zirconate sanyeon), PbTiO ₃ (Lead titanate) and BaTiO ₃ (barium titanate) may include any one ferroelectric ceramic selected from the group consisting of.

In addition, the substrate may be configured as an element including a control unit and a comparison unit, and the substrate may be configured as an element including a control unit, a comparison unit, and a sensing unit.

In an embodiment, a semiconductor device may include: a substrate including a plurality of NMOS transistors and a PMOS transistor; And a piezoelectric body formed in contact with the substrate, wherein the piezoelectric body may be formed at least in a direction parallel to the PMOS transistor.

In particular, the NMOS transistor may include a pull-down transistor and a pass transistor, and the PMOS transistor may include a pull-up transistor.

In addition, the substrate may include an I-type active region, wherein the pull-down transistor, the pull-up transistor, and the pass transistor may be disposed in the same direction.

In addition, the substrate may include an active region of type O, the pull-down transistor and the pull-up transistor may be disposed in the same direction, and the pass transistor may be disposed in a direction perpendicular to the pull-down transistor and the pull-up transistor.

A method of controlling a semiconductor device according to the present embodiment includes forming a semiconductor device including an element, a controller, a comparator, and a piezoelectric body; Inputting an external command to the controller; Applying a voltage to the piezoelectric body in the control unit; Applying a stress to the device in the piezoelectric body; Comparing operating speeds of the devices; And transmitting a signal to the controller.

In particular, the semiconductor device may further include a sensing unit measuring a temperature of the device, and comparing the operating speed of the device and simultaneously measuring the temperature of the device.

In the present technology, by attaching a piezoelectric element to an element, it is possible to form an element that satisfies a low power mode and a high speed mode simultaneously depending on whether or not a voltage is applied to the piezoelectric body.

1 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.
2A to 2C are state diagrams of piezoelectric bodies according to voltage.
3A and 3B are layout views illustrating a cell array layout of an SRAM.
4A and 4B are graphs illustrating changes in characteristics of each device according to gate and stress directions.
5A and 5B are block diagrams illustrating a method of operating a semiconductor device according to an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present embodiment.

1 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention. 2A to 2C are state diagrams of piezoelectric bodies according to voltage.

As shown in FIG. 1, the piezoelectric body 11 is attached to a substrate 12 including a plurality of transistors (or gates). Then, a voltage is applied to both ends of the piezoelectric body 11. Strain occurs in the piezoelectric body 11 according to the applied voltage, and stress is applied to the substrate 12 through deformation of the piezoelectric body 11. The operating characteristics of the substrate 12 are changed by stress, and the stress in the direction perpendicular to the gate acts in opposite directions in NMOS and PMOS, and the stress in the direction parallel to the gate is It works the same in both Moss and Pymos. The PMOS gate may be disposed in a direction parallel to the piezoelectric body 11.

Accordingly, the substrate 12 may include a device in which the direction of the gate is fixed to one side. The substrate 12 may include a semiconductor chip in which a packaging process is completed. The substrate 12 is selected from the group consisting of SRAM, Flash, DRAM, Digital Logic, and a converter (eg, a DC-DC converter with power transistors arranged in the same direction). It may include any one device. In particular, any one device selected from the group consisting of flash, DRAM, digital logic, and converter may include a device having a gate direction fixed to one side. The SRAM may include an I type or an O type SRAM. The relationship between the gate direction and the strain direction will be described in detail with reference to FIGS. 3A and 3B.

The piezoelectric body 11 may include a material in which a voltage is generated when a mechanical strain is applied, and a mechanical change such as expansion or contraction occurs when the piezoelectric body is applied. The piezoelectric body 11 may include a ferroelectric ceramic. For example, the ferroelectric ceramic may include any one selected from the group consisting of PZT (Pb (Ti, Zr) O ₃ , lead zirconate titanate), PbTiO ₃ (lead titanate), and BaTiO ₃ (barium titanate). In addition, the piezoelectric body 11 may include a piezoelectric single crystal (eg, quartz) or a zinc oxide film (ZnO). In addition, the piezoelectric body 11 is not limited thereto, and may include all piezoelectric materials having a large output dynamic energy with respect to the input electricity.

The piezoelectric body 11 may be in a normal state in which no voltage is applied, as shown in FIG. 2A, and may be mechanically compressed as shown in FIG. 2B or stretched as shown in FIG. 2C by applying the voltage.

When a voltage is applied to the piezoelectric body 11 and a tensile stress is applied to the substrate 12 in a direction parallel to the gate, the current increases in both the NMOS and the PMOS, thereby improving the operation speed of the device. On the other hand, if a voltage is not applied to the piezoelectric body 11, since no stress is applied to the substrate 12, a small current flows in the device, thus reducing leakage current.

As a result, even in the case of manufacturing a chip using the same device depending on whether or not a voltage is applied to the piezoelectric body 11, the high speed operation and the low current mode can be operated respectively. Furthermore, when setting the device to form a low speed operation mode when no voltage is applied, the leakage current can be reduced in a standby state, thereby reducing standby power consumption. The method of controlling the voltage of the piezoelectric body 11 for controlling the operating characteristics of the substrate 12 will be described in detail later with reference to FIGS. 4A and 4B.

In FIG. 1, the piezoelectric body 11 is larger than the substrate 12, but the size of the substrate 12 and the piezoelectric body 11 may be adjusted as necessary. In addition, although the piezoelectric body 11 is attached to the lower part of the board | substrate 12 in FIG. 1, the attachment position of the board | substrate 12 and the piezoelectric body 11 can be adjusted as needed.

3A and 3B are layout views illustrating a cell array layout of an SRAM. FIG. 3A is a layout diagram of a cell array of an I type, that is, a bar type SRAM, and FIG. 3B is a layout diagram of a cell array of an O type SRAM. For convenience of description, the first direction assumes the longitudinal direction of the drawings, and the second direction assumes the transverse direction of the drawings.

Referring to FIG. 3A, an SRAM cell may include active regions spaced apart from each other and a plurality of transistors formed on the active regions. Each active region is spaced apart by an isolation region. Each square separated by a solid line represents a respective SRAM cell, and as illustrated, a plurality of SRAM cells may be arranged along a first direction and a second direction. Adjacent SRAM cells arranged in the first and second directions may be mirror symmetrically arranged.

Each SRAM cell may include a P-type well (PW) active region and a PMOS (NW, N-type well, dotted line) active region. The NMOS active regions extend in the first direction and may be formed in a line type connected to the NMOS active regions of the SRAM cells arranged in the first direction. The PMOS active regions may be formed in a bar type having a long axis (first direction) and a short axis (second direction), and may be connected to adjacent SRAM cells adjacent to each other in the first direction.

Each SRAM cell may include a pair of NMOS active regions and a pair of PMOS active regions. The pair of PMOS active regions may be disposed between the pair of NMOS active regions.

Each SRAM cell may include a pull down gate (PD), a pull up gate (PU), and a pass gate. The pull-down gate and the pull-up gate may be electrically connected to each other by a sharing gate across the NMOS active region and the PMOS active region. The pass gate may be connected to a pass gate of an adjacent SRAM cell in a second direction. In each SRAM cell, the pull-down gate and the pass gate disposed in the same active region may share a junction region.

The shared gate connecting the pull-down gate and the pull-up gate may be arranged symmetrically with respect to the center point of the SRAM cell. The pass gate may also be arranged symmetrically with respect to the center point of the SRAM cell.

As described above, in an I-type SRAM cell, a pull down gate, a pull up gate, and a pass gate are all disposed in the same direction. Therefore, all of these gates exhibit the same current change effect on the stress, and when the tensile stress is applied by attaching the piezoelectric body as shown in FIG.

Referring to FIG. 3B, the SRAM cell may include active regions spaced apart from each other and a plurality of transistors formed on the active regions. Each active region is defined by an isolation region and spaced apart. Each square separated by a solid line represents a respective SRAM cell, and as illustrated, a plurality of SRAM cells may be arranged along a first direction and a second direction. Adjacent SRAM cells arranged in the first and second directions may be mirror symmetrically arranged.

Each SRAM cell may include a P-type well (PW) active region and a PMOS (NW, N-type well, dotted line) active region. The NMOS active region and the PMOS active region are spaced apart by the device isolation region. Each of the NMOS active regions and the PMOS active regions may be connected to an NMOS active region or a PMOS active region adjacent to each other in the second direction to form an O type active region.

Each SRAM cell may include a pull down gate, a pull up gate, and a pass gate. The pull-down gate and the pull-up gate may be electrically connected to each other by a sharing gate across the NMOS active region and the PMOS active region. The pass gate may be formed in a line type extending in the first direction. In each SRAM cell, the pull-down gate and the pass gate disposed in the same active region may share a junction region.

In the O type SRAM cell, the pull-down gate and the pull-up gate are disposed in the same direction, and the pass gate is disposed in the direction perpendicular to the pull-down gate and the pull-up gate. However, since the pass gate is an N-channel, the direction perpendicular to the gate direction and horizontal? All show the same current change effect in the direction. Therefore, all of these gates exhibit the same current change effect on the stress, and when the tensile stress is applied by attaching the piezoelectric body as shown in FIG. 1, the operation speed according to the increase of the current can be increased.

4A and 4B are graphs illustrating changes in characteristics of each device according to gate and stress directions. 4A is a graph showing a change in current according to stress in a direction perpendicular to the gate direction, and FIG. 4B is a graph showing a change in current according to stress in a direction parallel to the gate direction.

As shown in FIG. 4A, when stress is applied in a direction perpendicular to the gate direction, the NMOS increases the current as the strain increases, but the PMOS decreases the current as the strain increases. Accordingly, although the pass gate is disposed in the direction perpendicular to the pull-down gate and the pull-up gate in FIG. 2B, the pass gate may exhibit the same current change effect.

As shown in FIG. 4B, when stress is applied in a direction parallel to the gate direction, the current increases as the strain increases in both NMOS and PMOS. Accordingly, the pull-down gate and the pull-up gate may be arranged in the same direction in FIGS. 2A and 2B to exhibit the same current change effect.

5A and 5B are block diagrams illustrating a semiconductor device and an operating method thereof according to an embodiment of the present invention. 5A is a block diagram illustrating a semiconductor device according to a first embodiment, and FIG. 5B is a block diagram illustrating a semiconductor device according to a second embodiment.

As illustrated in FIG. 5A, the semiconductor device may include an element 101, a piezoelectric body 102, a controller 103, and a comparator 104. The region classified by the dotted line may be composed of one chip. That is, the device 101, the controller 103, and the comparer 104 may be included in one chip. The substrate shown in FIG. 1 may include a device 101 or a chip classified by a dotted line.

The semiconductor device according to the first exemplary embodiment may satisfy both low power operation and high speed mode operation. This is because the control unit 103 generates or maintains a bias by an externally input command, and the required operating speed and element 101 are obtained. It can be controlled through the comparison unit 104 for comparing the operating speed. The controller 103 may include a bias generation circuit or an internal voltage generation circuit.

The device 101 is selected from the group consisting of SRAM, Flash, DRAM, Digital Logic, and a converter (eg, a DC-DC converter with power transistors arranged in the same direction). Either gate direction may include a device fixed to one side. At this time, the SRAM may include an I type or an O type SRAM.

The piezoelectric body 102 is attached to the device 101 and serves to apply a voltage from the controller 103 to generate a mechanical shift to apply stress to the device 101. The piezoelectric body 102 may include a material in which mechanical variation such as expansion or contraction is generated by applying a voltage. The piezoelectric body 102 may include a ferroelectric ceramic. For example, the ferroelectric ceramic may include any one selected from the group consisting of PZT (Pb (Ti, Zr) O ₃ , lead zirconate titanate), PbTiO ₃ (lead titanate), and BaTiO ₃ (barium titanate). In addition, the piezoelectric body 11 may include a piezoelectric single crystal (eg, quartz) or a zinc oxide film (ZnO). In addition, the piezoelectric body 102 is not limited thereto, and may include all piezoelectric materials having a large output dynamic energy with respect to the input electricity.

The high speed operation mode and the low power mode will be described in detail as follows.

First, in the high speed operation mode, a command CMD for the high speed operation is input from the outside. The commanded control unit 103 generates a bias and applies it to the piezoelectric body 102. The applied piezoelectric body 102 increases the current by applying a tensile stress to the device 101, and increases the operating speed of the device. Can be improved. At this time, in the comparison unit 104 measuring the operating speed of the device 101 when the voltage is not applied compares the operating speed of the device 101 and the operating speed of the device 101 is stressed from the piezoelectric body 102 At the same time, a signal is transmitted to the controller 103 by comparing the operation speed of the device 101 required by an externally received command.

If there is no change in the operating speed of the device 101 or does not reach the required operating speed, the controller 103 may generate a larger bias and apply it to the piezoelectric body 102.

When the operating speed of the device 101 is the same as the required operating speed, the controller 103 may maintain high speed operation by continuously applying the same bias to the piezoelectric body 102.

Next, in the low power mode, a command CMD for low power is input from the outside. The control unit 103 receiving the command may stop the voltage applied to the piezoelectric body 102 so that no further tensile stress is applied to the element 101 in the piezoelectric body 102. If no voltage is applied to the piezoelectric body 102, no stress is applied to the element 101, so that a small current flows, thus reducing leakage current.

As described above, by forming the element 101 to which the piezoelectric body 102 is attached, it is possible to operate in the high speed mode and the low current mode, respectively, using one element. Furthermore, when setting the device to form a low speed operation mode when no voltage is applied, the leakage current can be reduced in a standby state, thereby reducing standby power consumption.

Table 1 and Table 2 are for comparing the characteristic of a comparative example and a present Example. Table 1 shows the characteristics of the comparative example, and Table 2 shows the characteristics of the present example.

As shown in Table 1, in the comparative example, a device for low power operation or a device for high speed operation is selected, and it is impossible to select a mode in each device. That is, the device for low power operation can operate only in the low power mode, the device for high speed operation can operate only in the high speed mode. As a result, in the comparative example, each element as needed is required.

As shown in Table 2, the present embodiment may select a low power mode or a high speed mode as one device. That is, since both operations can be performed by a single device, there is no need to form a device for each mode, thereby greatly improving the process margin.

In addition, in the low power mode, both the standby power, power consumption, and operation speed of the comparative example and the present embodiment are kept low. However, in the comparative example, the standby power is high when the device is used for high speed operation. In contrast, in the present embodiment, the standby power can be kept low even when operating in the high speed mode. As a result, in the present embodiment, since low current flows in the standby power in both the low power mode and the high speed mode, the standby power consumption may be reduced by reducing the leakage current in the standby state.

As illustrated in FIG. 5B, the semiconductor device may include an element 201, a piezoelectric body 202, a controller 203, a comparator 204, and a sensing unit 205. The region classified by the dotted line may be composed of one chip. That is, the device 201, the controller 203, the comparator 204 and the sensing unit 205 may be included in one chip. The substrate shown in FIG. 1 may include a device 201 or a chip classified by a dotted line.

The semiconductor device according to the second exemplary embodiment may satisfy both low power operation and high speed mode operation, and may compensate for deterioration of characteristics due to heat generated during operation of the device 201. This is a control unit 203 for generating or maintaining a bias by an externally input command, a sensing unit for measuring the temperature of the comparator 204 for comparing the required operating speed with the operating speed of the device 201 and the device 201. The control may be performed through the unit 205. The controller 203 may include a bias generation circuit or an internal voltage generation circuit.

The device 201 is selected from the group consisting of SRAM, Flash, DRAM, Digital Logic, and a converter (eg, a DC-DC converter with power transistors arranged in the same direction). Either gate direction may include a device fixed to one side. At this time, the SRAM may include an I type or an O type SRAM.

The piezoelectric element 202 is attached to the element 201 and applies a voltage from the control unit 203 to generate a mechanical shift, thereby acting to stress the element 201. The piezoelectric material 202 may include a material in which mechanical variation such as expansion or contraction is generated by applying a voltage. The piezoelectric body 202 may include a ferroelectric ceramic. For example, the ferroelectric ceramic may include any one selected from the group consisting of PZT (Pb (Ti, Zr) O ₃ , lead zirconate titanate), PbTiO ₃ (lead titanate), and BaTiO ₃ (barium titanate). In addition, the piezoelectric body 11 may include a piezoelectric single crystal (eg, quartz) or a zinc oxide film (ZnO). In addition, the piezoelectric body 202 is not limited thereto, and may include all piezoelectric materials having a large output dynamic energy with respect to the input electricity.

The high speed operation mode and the low power mode will be described in detail as follows.

First, in the high speed operation mode, a command CMD for the high speed operation is input from the outside. The commanded control unit 203 generates a bias and applies it to the piezoelectric body 202. The applied piezoelectric material 202 increases the current by applying a tensile stress to the device 201, and increases the operating speed of the device. Can be improved. In this case, the comparison unit 204 that measures the operating speed of the device 201 compares the operating speed of the device 201 and the operating speed of the device 201 that is stressed from the piezoelectric body 202 when no voltage is applied. At the same time, a signal is transmitted to the controller 203 by comparing the operation speed of the device 201 required from the externally received command.

If there is no change in the operating speed of the device 201 or does not reach the required operating speed, the controller 203 may generate a larger bias and apply it to the piezoelectric body 202.

When the operating speed of the device 201 is the same as the required operating speed, the controller 203 may maintain high speed operation by continuously applying the same bias to the piezoelectric body 202.

Next, in the low power mode, a command CMD for low power is input from the outside. The control unit 203 receiving the command may stop the voltage applied to the piezoelectric body 202 so that no further tensile stress is applied to the element 201 in the piezoelectric body 202. If no voltage is applied to the piezoelectric element 202, no stress is applied to the element 201, so that a small current flows, and thus, leakage current may also be reduced.

As described above, by forming the device 201 to which the piezoelectric body 202 is attached, it is possible to operate in the high speed mode and the low current mode by using one device. Furthermore, when setting the device to form a low speed operation mode when no voltage is applied, the leakage current can be reduced in a standby state, thereby reducing standby power consumption.

An operation method for preventing deterioration of device characteristics is as follows.

First, the sensing unit 205 stores a temperature which does not affect the non-operation or deterioration of the characteristics of the element 201, and compares the temperature of the element 201 with the existing temperature when the element 201 operates. Signal 203). Inevitably heat is generated during operation of the device 201, but if the generated heat is excessive, a problem of deterioration of operating characteristics of the device, such as a decrease in operating speed, is inevitable.

Therefore, in the second embodiment, the temperature of the device 201 is steadily checked with a temperature that does not affect the deterioration of characteristics, and when the temperature of the device 201 exceeds the reference point, a signal is transmitted to the control unit 203 to transmit the piezoelectric material 202. Larger bias can be applied. When a larger bias is applied to the piezoelectric body 202, a larger tensile stress is applied to the attached device 201, thereby preventing a decrease in operating speed caused by heat.

As such, by adding the sensing unit 205 for measuring the temperature of the device 201, it is possible to prevent and compensate for deterioration of characteristics due to heat generated during operation of the device 201. In the present embodiment, the comparative example and the sensing unit are simultaneously included, but a semiconductor device including only the sensing unit may also be formed to prevent deterioration of device characteristics.

Although the technical spirit of this embodiment has been described in detail according to the above embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, a person of ordinary skill in the art of the present embodiment will understand that various embodiments are possible within the scope of the technical idea of the present embodiment.

11: piezoelectric
12: device

Claims (19)

A substrate on which an element including a plurality of transistors is formed; And
A piezoelectric body formed in contact with the substrate,
The piezoelectric body is formed in a direction parallel to the transistor,
In a high speed operation mode, a voltage is applied to the piezoelectric body to stress the substrate to increase the current flowing through the transistor,
Breaking the voltage applied to the piezoelectric body in the low power mode
Semiconductor device.
Claim 2 has been abandoned upon payment of a set-up fee. The method of claim 1,
The substrate includes a semiconductor chip having a packaging process is completed.
Claim 3 has been abandoned upon payment of a set-up fee. The method of claim 1,
The substrate includes any one selected from the group consisting of SRAM, Flash, DRAM, Digital Logic, and Converter.
Claim 4 has been abandoned upon payment of a setup registration fee. The method of claim 1,
The substrate includes a device in which the gate electrode of the transistor is fixedly arranged in one direction. Claim 5 was abandoned upon payment of a set-up registration fee. The method of claim 1,
And the piezoelectric material includes any one material selected from the group consisting of ferroelectric ceramics, piezoelectric single crystals, and zinc oxide films.
Claim 6 has been abandoned upon payment of a setup registration fee. The method of claim 1,
The piezoelectric body includes any one of ferroelectric ceramics selected from the group consisting of PZT (Pb (Ti, Zr) O ₃ , lead zirconate titanate), PbTiO ₃ (lead titanate), and BaTiO ₃ (barium titanate).
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1,
The substrate includes a control unit for controlling whether the voltage is applied to the piezoelectric body according to the mode, and a comparison unit for comparing a desired operating speed of the device with a current operating speed,
The comparing unit transmits a first signal indicating that the current operating speed is the same as the desired operating speed or a second signal indicating that the current operating speed is less than the desired operating speed to the controller.
The controller may be configured to maintain the voltage applied to or not applied to the piezoelectric body when receiving the first signal, and to increase the voltage applied to the piezoelectric body when receiving the second signal.
Semiconductor device.
Claim 8 has been abandoned upon payment of a set-up fee. The method of claim 7, wherein
The substrate further includes a sensing unit for measuring the temperature of the device,
The sensing unit transmits a third signal informing the controller if the temperature of the device exceeds a predetermined reference point,
The control unit may increase the voltage applied to the piezoelectric body when the third signal is received.
Semiconductor device. A substrate including an element including a plurality of NMOS transistors and a PMOS transistor; And
A piezoelectric body formed in contact with the substrate,
The piezoelectric body is formed at least in a direction parallel to the PMOS transistor,
In a high speed operation mode, a voltage is applied to the piezoelectric body to stress the substrate to increase the current flowing through the transistor,
Breaking the voltage applied to the piezoelectric body in the low power mode
Semiconductor device.
Claim 10 has been abandoned upon payment of a set-up registration fee. The method of claim 9,
The NMOS transistor includes a pull-down transistor and a pass transistor, and the PMOS transistor includes a pull-up transistor.
Claim 11 was abandoned upon payment of a set-up fee. The method of claim 10,
The substrate includes an I type active region.
Claim 12 was abandoned upon payment of a set-up fee. The method of claim 11,
And the pull-down transistor, the pull-up transistor, and the pass transistor are arranged in the same direction.
Claim 13 has been abandoned upon payment of a set-up fee. The method of claim 10,
The substrate includes an O type active region.
Claim 14 was abandoned upon payment of a set-up fee. The method of claim 13,
And the pull-down transistor and the pull-up transistor are disposed in the same direction, and the pass transistor is disposed in a direction perpendicular to the pull-down transistor and the pull-up transistor.
Forming a semiconductor device including a device, a piezoelectric body for applying stress to the device, a control unit for controlling whether a voltage is applied to the piezoelectric body, and a comparison unit for comparing a current operating speed of the device with a desired operating speed;
Inputting an external command to inform the controller of a high speed mode or a low power mode;
Applying a voltage to the piezoelectric body by the controller when the external command is in the high speed operation mode;
Applying stress to the device in the piezoelectric body in accordance with the applied voltage;
Performing the comparison by the comparing unit to transmit a first signal indicating that a current operating speed is equal to a desired operating speed, or a second signal indicating that the current operating speed is less than a desired operating speed;
Maintaining a voltage applied to the piezoelectric body in accordance with the first signal or increasing the voltage applied to the piezoelectric body in accordance with the second signal; And
When the external command is in the low power mode, disconnecting the voltage applied to the piezoelectric body from the control unit
Control method of a semiconductor device comprising a.
Claim 16 was abandoned upon payment of a set-up fee. The method of claim 15,
The semiconductor device further includes a sensing unit measuring a temperature of the device,
Transmitting, by the sensing unit, a third signal informing the controller if the temperature of the device exceeds a predetermined reference point; And
Increasing the voltage applied to the piezoelectric body in accordance with the third signal by the controller;
Method of controlling a semiconductor device.
Claim 17 was abandoned upon payment of a set-up fee. The method of claim 16,
And controlling the temperature of the device at the same time as comparing the operating speeds of the devices.
Claim 18 was abandoned when the set registration fee was paid. The method of claim 15,
The device includes a device selected from the group consisting of SRAM, Flash, DRAM, Digital Logic, and Converter.
Claim 19 was abandoned upon payment of a set-up fee. The method of claim 15,
And the piezoelectric material includes any one material selected from the group consisting of ferroelectric ceramics, piezoelectric single crystals, and zinc oxide films.

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