KR102055245B1 - Multiplication circuit and radio communication device - Google Patents

Abstract

The present invention provides a multiplication circuit capable of controlling the output level of a desired multiplication wave in a desired range. The multiplication circuit according to the present invention comprises a multiplier output unit including a transistor and receiving an input signal having a predetermined frequency and outputting a multiply wave of a predetermined multiplier of the input signal, and controlling a voltage between a gate source of the transistor. And a control unit, wherein the multiplication wave output unit controls harmonic distortion related to the output of the multiplication wave based on the voltage between the gate sources.

Description

Multiplication circuit and a wireless communication device using the same {MULTIPLICATION CIRCUIT AND RADIO COMMUNICATION DEVICE}

The present invention relates to a multiplication circuit and a wireless communication device using the same.

With the advance of wireless communication, the tendency to make a carrier signal high frequency is remarkable. On the other hand, in the design of semiconductor integrated circuits related to the output of such carriers, the difficulty is increasing with increasing frequency. For example, in the design of a circuit using a millimeter wave band in the 80 GHz band, the design parameter becomes a value close to the parasitic element, and the difficulty of the parasitic element cannot be ignored, thereby increasing the design difficulty.

Therefore, attention has been paid to a multiplication circuit capable of outputting a multiplication wave (harmonic wave) having a frequency of an integer multiple of the frequency of the input signal using a nonlinear element such as a transistor. By using such a multiplication circuit, the frequency of the signal output from the oscillator (the input signal) can be kept low, and the difficulty of circuit design regarding the output of high frequency can be kept low. Patent Document 1 discloses an example of a frequency multiplier using a multiplication circuit.

Japanese Patent Publication No. 2007-158803

On the other hand, in the radio communication apparatus capable of outputting high frequency, it is required to be able to switch the output level and frequency of the carrier wave according to the reception environment and the application to be used.

Therefore, in order to realize such a wireless communication device with a relatively low design difficulty, a multiplication circuit capable of controlling the output level of a multiplication wave of a desired multiplier (hereinafter simply referred to as a "preferred multiplication wave") in a desired range is provided. It is required.

Therefore, this invention is made | formed in view of the said problem, and an object of this invention is to provide the multiplication circuit which can output by controlling the output level of a desired multiplication wave to a desired range.

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, According to an aspect of the present invention, a multiplication wave output unit including a transistor, receiving an input signal having a predetermined frequency, and outputting a multiplication wave of a predetermined multiplication factor of the input signal, and the transistor And a control unit for controlling the voltage between gate sources of the multiplier output unit, wherein the harmonic distortion associated with the output of the multiplier wave is controlled based on the voltage between the gate sources.

With this arrangement, the harmonic distortion of the transistor can be changed by controlling the voltage between the gate sources of the transistors.

The controller may be configured to control the voltage between the gate sources within a predetermined range, and the multiplication wave output unit may be configured to control the harmonic distortion corresponding to the voltage between the gate sources under the control of the voltage between the gate sources. You may set to.

The amplitude value of the multiplication wave may be controlled to a desired range by the control of the harmonic distortion.

The filter may be provided at a rear end of the multiplication wave output section and pass at least a frequency component corresponding to the multiplication wave.

The filter may be configured to cut off a frequency component corresponding to the input signal.

The harmonic distortion may be controlled by providing an auxiliary transistor connected in parallel to the transistor and controlling a voltage between gate sources applied to the auxiliary transistor.

In addition, in order to solve the above problems, according to another aspect of the present invention, an oscillator and a transistor for outputting an input signal of a predetermined frequency, receiving the input signal, and multiplying the multiplication wave of a predetermined multiplier of the input signal A multiplication output unit for outputting, a control unit controlling a voltage between a gate source of the transistor, and a modulation unit for modulating a baseband signal of which the multiplication wave is desired as a carrier wave, wherein the multiplication wave output unit outputs the multiplication wave. A harmonic distortion with respect to is controlled to a value corresponding to the voltage between the gate source is provided.

The oscillator may be configured to be capable of controlling the frequency of the input signal.

It is comprised so that a desired frequency component can be cut off, and you may be equipped with the filter which cuts off the frequency component corresponding to the input signal whose frequency was controlled by the said oscillator.

As described above, according to the present invention, it is possible to provide a multiplication circuit and a wireless communication device capable of controlling the output level of a desired multiplication wave in a desired range.

1 is a block diagram showing a schematic configuration of a wireless communication device according to an embodiment of the present invention.
2 is a graph showing an example of the relationship between the harmonic distortion coefficient of a transistor and the voltage between the gate source.
3A is a block diagram showing a schematic configuration of a multiplication circuit according to an embodiment of the present invention.
3B is an exemplary diagram of a circuit diagram of the multiplication circuit shown in FIG. 3A
4A is a block diagram showing a schematic configuration of a radio communication apparatus according to a first embodiment of the present invention.
Fig. 4B is a graph showing the relationship between the harmonic distortion control voltage and the amplitude value of the output signal after modulation in the radio communication apparatus according to the first embodiment of the present invention.
5 is an exemplary diagram of a circuit diagram of a multiplication circuit according to a modification of the present invention.
6A is a table showing the detailed parameters of each transistor of the multiplication circuit according to the second embodiment of the present invention.
Fig. 6B is a graph showing the relationship between the harmonic distortion control voltage and the amplitude value of the output signal in the radio communication apparatus according to the second embodiment of the present invention.
7 is a block diagram showing a schematic configuration of a radio communication apparatus according to a third embodiment of the present invention.

EMBODIMENT OF THE INVENTION Preferred embodiment of this invention is described in detail, referring drawings attached below. In addition, in this specification and drawing, the overlapping description is abbreviate | omitted by attaching | subjecting the same code | symbol about the component which has substantially the same function and structure.

[Wireless communication device]

First, the configuration of a wireless communication apparatus according to the present embodiment will be described with reference to FIG.

1 is a block diagram showing a schematic configuration of a radio communication apparatus according to the present embodiment. As shown in FIG. 1, the radio communication apparatus includes a frequency multiplier 10, a modulator 20, and a transmitter 30.

The frequency multiplier 10 includes a multiplication circuit 11 and a harmonic distortion control unit 12. In addition, the multiplication circuit 11 includes a multiplication wave output section 111 and a filter 112.

The multiplication wave output unit 111 receives an input signal including a frequency component of a predetermined frequency. For example, an oscillator or the like is used to generate the input signal. As the oscillator, an oscillator capable of changing the oscillation frequency, such as a voltage controlled oscillator (VCO), may be used. In addition, the above-mentioned frequency component contained in the said input signal is called "reference wave fOSC" hereafter.

Although the details will be described later, the multiplication wave output section 111 includes a transistor. The harmonic distortion control voltage Vg is applied to the multiplication wave output unit 111 from the harmonic distortion control unit 12, and the harmonic distortion control voltage Vg is applied as a gate source voltage to the transistor of the multiplication wave output unit 111. . According to the voltage value of the harmonic distortion control voltage Vg, the harmonic distortion of the transistor included in the multiplication wave output section 111 changes. In addition, the detailed description of the said operation principle is demonstrated below. By the change of the harmonic distortion, the output level of the harmonic component (that is, the multiplication wave) in the input signal is changed. That is, by controlling the voltage value of the harmonic distortion control voltage Vg applied from the harmonic distortion control unit 12, the output level of the multiplication wave of the desired multiplication factor in the input signal can be adjusted to a desired value. In addition, below, it demonstrates as the output level of the multiplying wave n * fOSC of predetermined multiplier n (n≥2) by the multiplying wave output part 111 was adjusted to the desired value.

The multiplying wave output section 111 outputs to the filter 112 an input signal whose output level of the multiplying wave n * fOSC of the predetermined multiplier n is adjusted.

The harmonic distortion control unit 12 applies the harmonic distortion control voltage Vg to the multiplication wave output unit 111 to control the harmonic distortion at the multiplication wave output unit 111 to a value corresponding to the harmonic distortion control voltage Vg. .

The harmonic distortion control unit 12 may be configured to be able to change the harmonic distortion control voltage Vg applied to the multiplication wave output unit 111. For example, in the example shown in FIG. 1, the harmonic distortion control part 12 is comprised including several switch SW1-SWm. Further, different voltages Vg1 to Vg_m are configured to be applied to the wirings in which ON / OFF is switched by each of the switches SW1 to SWm. By such a configuration, by switching the switches SW1 to SWm, the voltage corresponding to the switch in the ON state among the voltages Vg1 to Vg_m is applied to the multiplication wave output unit 111 as the harmonic distortion control voltage Vg. Furthermore, the configuration of the harmonic distortion control unit 12 shown in FIG. 1 is an example, and if harmonic distortion control voltage Vg applied to the multiplication wave output unit 111 can be controlled to a desired value, the harmonic distortion control unit 12 The configuration of is not limited. In addition, the said harmonic distortion control part 12 has shown an example of the "control part." In addition, the frequency multiplier 10 in which the harmonic distortion control unit 12 is included in the multiplication circuit 11 may be simply referred to as a "multiplication circuit".

The filter 112 receives an input signal from the multiplication wave output unit 111 in which the output level of the multiplication wave n * fOSC of the predetermined multiplication number n is adjusted. The filter 112 is comprised so that the frequency component used as a carrier, for example, the multiplication wave n * fOSC of predetermined multiplier n of the frequency component contained in the said input signal may be passed. In addition, the filter 112 may be comprised so that only the frequency component used as a carrier wave may be removed. For example, the filter 112 may be caused to pass through a multiplication wave n * fOSC used as a carrier wave and to remove the reference wave fOSC which is a source of generation of the multiplication wave n * fOSC in order not to use it as a carrier wave. In addition, below, the filter 112 demonstrates as having passed the multiplying wave n * fOSC. The filter 112 outputs the filtered input signal, that is, the multiplication wave n * fOSC, to the modulator 20. In addition, below, the filtered input signal output from the said filter 112 is called "output signal."

The modulator 20 receives an output signal from the filter 112, that is, a multiplication wave n * fOSC of a predetermined frequency. The multiplication wave n * fOSC is a multiplication wave of a predetermined multiplication number n of the reference wave fOSC, and the output level is adjusted in the multiplication wave output unit 111. In addition, the modulator 20 receives the baseband signal fBB generated based on the data to be transmitted. The modulator 20 modulates the baseband signal fBB using the multiplication wave n * fOSC as a carrier wave. The modulator 20 outputs the modulated signal fTX to the transmitter 30. In response, the transmitter 30 transmits the signal fTX to a predetermined transmission destination.

[Multiplication circuit 11]

Next, the operation principle and the detailed configuration of the multiplication circuit 11 will be described.

(Operation principle)

First, with reference to FIG. 2, the principle that harmonic distortion of the transistor included in the multiplication circuit 11 is controlled by the harmonic distortion control voltage Vg is demonstrated. 2 is a graph showing an example of the relationship between the harmonic distortion coefficient of a transistor and the voltage between the gate source. In the example of FIG. 2, a MOS transistor having a channel length of L = 60 [nm] and a channel width of W = 40 [um] is used. 2, graphs g10, g11, g12, and g13 are shown. 2 represents the voltage Vgs [V] between gate sources applied to the transistor, which is common among the graphs g10 to g13. In the multiplication circuit 11 according to the present embodiment, the applied harmonic distortion control voltage Vg corresponds to the gate-source voltage Vgs [V] in FIG.

Graph g10 shows the change of the drain source current Ids [A] with respect to the gate source voltage Vgs [V].

In addition, the graph g11 shows the change of the harmonic distortion coefficient gm-1st [A / V] of the 1st harmonic (that is, the reference wave) with respect to the gate-source voltage Vgs [V]. The term "harmonic distortion coefficient" indicates an amplification factor of harmonic distortion. In addition, the graph g12 shows the change of the harmonic distortion coefficient gm-2nd [A / V2] of the second harmonic with respect to the voltage Vgs [V] between gate sources. Moreover, graph g13 shows the change of the harmonic distortion coefficient gm-3rd [A / V3] of 3rd harmonics with respect to the gate-source voltage Vgs [V].

As shown in FIG. 2, the graph g12 takes an extreme value near the gate-source voltage Vgs = 0.55 [V], and at this time, the harmonic distortion coefficient gm-2nd of the second harmonic becomes maximum. That is, the graph g12 changes the amplitude value of the second harmonic (that is, the multiplication wave of the multiplication factor 2) by changing the gate-source voltage Vgs [V] in the range of 0.0 [V] to 1.0 [V]. It can be shown. In addition, by setting Vgs = 0.55 [V], the second harmonic of the maximum amplitude value can be obtained.

In addition, the graph g13 takes extreme values in the vicinity of the gate-source voltage Vgs = 0.65 [V] and Vgs = 0.35 [V]. That is, the harmonic distortion coefficient gm-3rd of the 3rd harmonic becomes the maximum at the minus side in the vicinity of the gate source voltage Vgs = 0.65 [V], and is near the gate source voltage Vgs = 0.35 [V]. On the plus side. That is, the graph g13 can change the amplitude value of the third harmonic (that is, the triplex of the multiplication factor 3) by changing the gate source voltage Vgs [V] in the range of 0.0 [V] to 1.0 [V]. It is present.

Moreover, it is not necessary to consider the difference in phase, and when only focusing on the amplitude value, if the absolute values of the harmonic distortion coefficients are the same, harmonics of the same amplitude value can be obtained on the plus side and the minus side. Specifically, in the example shown in the graph g13, the absolute values of the harmonic distortion coefficients are almost the same in the vicinity of Vgs = 0.65 [V] and in the vicinity of Vgs = 0.35 [V]. That is, in the example shown in the graph g13 of FIG. 2, in the case of both Vgs = 0.65 [V] and Vgs = 0.35 [V], the 3rd harmonic of the same amplitude value can be obtained. Therefore, if it is not necessary to consider the influence of other harmonics, by setting the voltage between gate sources Vgs = 0.35 [V], the third harmonic of the same amplitude value as in the case of Vgs = 0.65 [V] can be obtained and consumed. The power can be kept low. Furthermore, in the above example, the second harmonic and the third harmonic have been described. However, the second harmonic and the third harmonic are only examples. For example, the fifth harmonic may be a target harmonic such as a fifth harmonic. In such a case, what is necessary is just to investigate the characteristic of the said harmonic beforehand, and to control the voltage Vgs between gate sources according to the characteristic.

As described above, each harmonic distortion coefficient of the transistor is changed in accordance with the voltage Vgs between the gate sources. Therefore, in the multiplication circuit 11 according to the present embodiment, the harmonic distortion of the transistor is changed by controlling the gate-to-gate voltage Vgs by using this characteristic of the transistor, and the output level of the desired harmonic output from the transistor is a desired value. To control. Hereinafter, the configuration of the multiplication circuit 11 according to the present embodiment will be described.

(Configuration)

Next, the detailed structure of the multiplication circuit 11 is demonstrated with reference to FIG. 3A and FIG. 3B.

3A is a block diagram showing a schematic configuration of a multiplication circuit 11 according to an embodiment of the present invention, and the multiplication circuit 11 in FIG. 3A corresponds to the multiplication circuit 11 in FIG. 3B is an example of the circuit diagram of the multiplication circuit 11 shown in FIG. 3A.

As shown in FIG. 3B, the multiplication circuit 11 includes a transistor M1. As the transistor M1, for example, a MOS transistor is used. In addition, below, the case where a MOS transistor is used as transistor M1 is demonstrated as an example, However, transistor M1 is not limited to a MOS transistor, It is also possible to replace it with another kind of transistor. The input signal input from the input terminal RFIN is input to the gate of the transistor M1 through the capacitor Cin. In addition, the capacitor Cin plays a role of blocking a DC component between the input terminal RFIN and the gate of the transistor M1. That is, the direct current component is cut off from the input signal input from the input terminal RFIN, and only the alternating current component is input to the gate of the transistor M1.

In addition, a harmonic distortion control voltage Vg is applied from the harmonic distortion control unit 12 to the gate side of the transistor M1 through an inductor Lb. The source side of the transistor M1 is connected to ground. In other words, the harmonic distortion control voltage Vg is applied to the transistor M1 as a gate-to-gate voltage. Further, the inductor Lb serves to block high frequency components between the gate of the transistor M1 and the harmonic distortion control unit 12.

As described above with reference to FIG. 2, when the harmonic distortion control voltage Vg is applied between the gate sources of the transistor M1, the harmonic distortion coefficient of the transistor M1 changes according to the voltage value of the harmonic distortion control voltage Vg. As a result, the amplitude value of each harmonic component included in the input signal input to the transistor M1 is adjusted according to the harmonic distortion coefficient and outputted to the drain side of the transistor M1. That is, an example of a specific configuration in which the transistor M1 (and a circuit related to the input / output of the transistor M1) corresponds to the multiplication wave output unit 111 in FIG. 3A is shown.

The circuit group U112 and the output terminal RFOUT are connected to the drain side of the transistor M1.

Circuit group U112 has shown the specific structure corresponding to the filter 112 shown in FIG. 3A. The circuit group U112 includes a capacitor CLS and an inductor LLS (hereinafter referred to as "LC series circuit CLSLLS") connected in series, and a capacitor CLP and an inductor LLP (hereinafter referred to as "LC parallel circuit CLPLLP") connected in parallel. It is connected in parallel and is comprised.

The LC series circuit CLSLLS serves to remove frequency components corresponding to the magnetic resonance frequency. For this reason, for example, by setting the self-resonance frequency of the LC series circuit CLSLLS to the frequency of the reference wave fOSC, it can be operated to remove the frequency component corresponding to the reference wave fOSC from the input signal. Moreover, in the following description, the LC series circuit CLSLLS is described as operating to remove frequency components corresponding to the reference wave fOSC.

In addition, the LC parallel circuit CLPLLP serves to pass a frequency component corresponding to the magnetic resonance frequency. Therefore, for example, by setting the self-resonant frequency of the LC parallel circuit CLPLLP near the frequency of the multiplication wave n * fOSC using the carrier wave, a frequency component corresponding to the multiplication wave n * fOSC in the input signal can be selectively passed. have. Furthermore, in the following description, the LC parallel circuit CLPLLP is described as operating to pass a frequency component corresponding to the multiplication wave n * fOSC.

Thus, in the transistor M1, the input signal whose output level of the multiplication wave n * fOSC of predetermined multiplier n is adjusted is filtered by the circuit group U112. At this time, as shown above, the frequency component corresponding to the reference wave fOSC is removed, and the frequency component corresponding to the multiplication wave n * fOSC is passed. In this way, the filtered input signal is output from the output terminal RFOUT. That is, the multiplication wave n * fOSC adjusted to the predetermined output level is output from the output terminal RFOUT. The multiplication wave n * fOSC output from the output terminal RFOUT is input to the modulator 20 as a carrier wave.

As described above, the frequency multiplier 10 according to the present embodiment controls the harmonic distortion control voltage Vg applied between the gate sources of the transistors M1 of the multiplication circuit 11, thereby outputting the multiplier n * fOSC of the desired multiplier n. You can adjust the level to the desired value. In addition, since the oscillation frequency of the oscillator (i.e., the frequency of the reference wave fOSC) can be kept low, a wireless communication device capable of controlling and outputting a high frequency output level such as 80 GHz in a desired range with a relatively low design difficulty. It can be realized.

Example 1

Next, as a more specific configuration of the above-described embodiment, as an example in which the output level of the multiplier n * fOSC output from the frequency multiplier 10 is controlled to be in a predetermined range by the control of the harmonic distortion control voltage Vg, Explain about.

First, with reference to FIG. 4A, the structure of the radio | wireless communication apparatus which concerns on Example 1 is demonstrated. Here, the description will be made by paying attention to the configuration of the frequency multiplier 10a whose operation differs from the above-described embodiment shown in FIG. 1, and the modulation unit 20 and the transmission unit ( 30), detailed description will be omitted.

In addition, the multiplication circuit 11a which concerns on a present Example has shown the same structure as the multiplication circuit 11 shown in FIG. 3B. That is, in this embodiment, the transistor M1 (and the circuit related to the input / output of the transistor M1) in FIG. 3B corresponds to the multiplication wave output section 111a in this embodiment. In addition, the circuit group U112 in FIG. 3B corresponds to the filter 112a in this embodiment. Further, in the first embodiment, the channel length L = 60 [nm] and the channel width W = 40 [um] are used for the transistor M1 of the multiplication wave output section 111a according to the present embodiment.

In addition, the frequency multiplier 10a according to the present embodiment receives an input signal in which the frequency of the reference wave fOSC is 40 GHz, and outputs a double multiplication wave 2 * fOSC (80 GHz) having a multiplier n = 2. For this reason, the filter 112a is adjusted to remove the frequency component near 40 GHz corresponding to the reference wave fOSC, and to pass the frequency component near 80 GHz corresponding to the double wave 2 * fOSC.

In such a configuration, the harmonic distortion control unit 12a according to the present embodiment is configured so that the harmonic distortion control voltage Vg can be changed to a pitch of 0.1 V from 0.4 [V] to 0.8 [V]. As a specific example, as shown in FIG. 4A, the harmonic distortion control unit 12a includes switches SW1 to SW5. Each switch is also configured such that different voltages Vg1 to Vg5 are applied to the wirings in which ON / OFF is switched by each of the switches SW1 to SW5. Further, in this embodiment, Vg1 = 0.4 [V], Vg2 = 0.5 [V], Vg3 = 0.6 [V], Vg4 = 0.7 [V], and Vg5 = 0.8 [V]. Accordingly, when the switch SW1 is in the ON state, Vg1 = 0.2 [V] is applied as the harmonic distortion control voltage Vg from the harmonic distortion control unit 12a to the transistor M1 of the multiplication wave output unit 111a. In addition, by switching the switch in the ON state to SW2, SW3, SW4, SW5, the voltage values of the harmonic distortion control voltage Vg are changed to Vg2 = 0.5 [V], Vg3 = 0.6 [V], Vg4 = 0.7 [V], Vg5 = It is possible to switch sequentially to 0.8 [V].

Reference is made here to FIG. 4B. 4B is a graph showing the relationship between the harmonic distortion control voltage Vg and the amplitude value of the output signal fTX after modulation in the case where the harmonic distortion control voltage Vg is changed to 0.1V pitch in the wireless communication device shown in FIG. 4A. . 4B shows the amplitude value [mVpp] of the signal fTX after modulation, that is, the amplitude of the signal after the output signal (doubled wave 2 * fOSC) from the frequency multiplier 10a is modulated by the modulator 20. FIG. The value is shown. In addition, the horizontal axis has shown the voltage value [V] of the harmonic distortion control voltage Vg. In addition, although FIG. 4A shows the structure at the time of changing a harmonic distortion control voltage Vg to 0.4 [V]-0.8 [V], the graph g21 shown in FIG. 4B shows the harmonic distortion control voltage Vg as 0.2 [V]. ] Is shown in the case where it changes to 0.8 [V].

The harmonic distortion control voltage Vg is applied between the gate sources of the transistors M1 in the multiplication wave output section 111a. Therefore, when the harmonic distortion control voltage Vg is changed, the harmonic distortion of the transistor M1 changes in conjunction with this, and as a result, the output level of each multiplication wave included in the input signal changes in accordance with the harmonic distortion. For example, in the example shown in FIG. 4A, when the harmonic distortion control voltage Vg is changed from 0.2 [V] to 0.8 [V], the amplitude value of the signal fTX after modulation is changed between 390 to 780 [mVpp]. It is becoming. This is due to the change of the voltage applied between the gate sources of the transistor M1 in the multiplication wave output section 111a by the control of the harmonic distortion control voltage Vg, thereby changing the harmonic distortion of the transistor M1.

As shown in Fig. 4A, particularly in the vicinity of the harmonic distortion control voltage Vg = 0.4 [V], the amplitude value of the signal fTX after modulation becomes maximum, after which the amplitude value decreases. At this time, the difference ΔGv between the amplitude value at the time of Vg = 0.4 [V] and the amplitude value at Vg = 0.8 [V] is ΔGv> 6 [dB].

As described above, in the configuration shown in FIG. 4A, the harmonic distortion control unit 12a is configured to be able to control the harmonic distortion control voltage Vg in the range of 0.4 [V] to 0.8 [V], thereby achieving a gain variable range of 6 dB or more. It is possible to realize.

[Modification]

Next, a radio communication apparatus according to a modification of the above-described embodiment will be described.

The radio communication apparatus according to the modification differs in the configuration of the radio communication apparatus shown in FIG. 1 from the multiplication circuit 11. Hereinafter, with reference to FIG. 5, the radio communication apparatus which concerns on a modification is focused on the structure of the multiplication circuit 11b different from the above-mentioned embodiment. 5 is an example of a circuit diagram of a multiplication circuit 11b according to a modification.

As shown in FIG. 5, the multiplication circuit 11b which concerns on the said modification differs from the multiplication circuit 11 shown by FIG. 3B by the auxiliary transistor M2 other than transistor M1. Therefore, a description will be given focusing on the configuration related to the auxiliary transistor M2, and the detailed description of the same configuration as that of the multiplication circuit 11 shown in FIG. 3B will be omitted.

The auxiliary transistor M2 is connected in parallel with the transistor M1. Specifically, the drain side of the transistor M1 and the drain side of the auxiliary transistor M2 are connected. In addition, similarly to the transistor M1, the input signal input from the input terminal RFIN is input to the gate of the auxiliary transistor M2 through the capacitor Cin. The source side of the auxiliary transistor M2 is connected to ground.

In the multiplication circuit 11b which concerns on the said modification, the voltage VgM1 and VgM2 comprised so that each gate side of the transistor M1 and the auxiliary transistor M2 are independently controllable via the inductor Lb is applied. Furthermore, as the voltage VgM1, the harmonic distortion control voltage Vg from the harmonic distortion control unit 12 is applied similarly to the multiplication circuit 11 shown in FIG. 3B.

Furthermore, as described above, the voltages VgM1 and VgM2 are configured to be independently controllable. Therefore, when a transistor having the same characteristic is used for the transistor M1 and the auxiliary transistor M2, and the same harmonic distortion control voltage Vg is applied, a multiply wave n * fOSC of a desired multiplier n is interposed between these transistors M1 and M2. It is possible to configure to strengthen each other. Alternatively, a transistor having different characteristics may be applied to the transistor M1 and the auxiliary transistor M2, or a voltage different from the harmonic distortion control voltage Vg may be applied to the auxiliary transistor M2. In this way, by independently controlling the transistor M1 and the auxiliary transistor M2, for example, it is possible to operate a negative multiplication wave while negating other multiplication waves while enhancing the desired multiplication wave.

In addition, about the other structure, it is the same as the multiplication circuit 11 shown in FIG. 3B.

Example 2

Next, as the second embodiment, a case where the multiplication circuit 11b shown in the modification is applied to the frequency multiplier 10a shown in the first embodiment instead of the multiplication circuit 11a will be described. In addition, the frequency multiplier 10a in this embodiment is called especially the frequency multiplier 10b, and the filter 112a in this embodiment is called especially the filter 112b.

First, with reference to FIG. 6A, the detailed structure of transistor M1 and auxiliary transistor M2 in a present Example is demonstrated. 6A is a table showing detailed parameters of the transistor M1 and the auxiliary transistor M2 in the multiplication circuit 11b according to the present embodiment. Further, in the radio communication apparatus according to the second embodiment, a multi-finger type transistor is used as the transistor M1 and the auxiliary transistor M2 used in the multiplication circuit 11b.

As shown in Fig. 6A, the transistor M1 is a transistor with the number of fingers k = 20, and the channel width Wu = 2 [um] and the channel length L = 60 [nm] per finger. In other words, the total channel width Wtotal of the transistor M1 is Wtotal = Wu * k = 40 [nm]. The gate-source voltage Vgs, that is, the voltage VgM1 is applied to the transistor M1 in the range of 0.2 [V] to 0.8 [V]. Moreover, the default value of the voltage VgM1 was 0.45 [V], and the drain current Id at this time was 2.105 [mA].

The auxiliary transistor M2 is a transistor having the number of fingers k = 5, and the channel width Wu = 2 [um] and the channel length L = 60 [nm] per finger. That is, the total channel width Wtotal of the auxiliary transistor M2 is Wtotal = Wu * k = 10 [nm]. The auxiliary transistor M2 is supplied with a voltage Vgs between gate sources, that is, 0 [V], that is, no voltage or 0.5 [V] as the voltage VgM2. Moreover, the drain current Id when the voltage VgM2 was 0.5 [V] was 0.784 [mA].

In addition, the frequency multiplier 10b according to the present embodiment receives an input signal in which the frequency of the reference wave fOSC is 40 GHz, as in the case of the first embodiment, and receives a multiplier 2 * fOSC having a multiplier n = 2 (80 GHz). ) Will be output. Therefore, the filter 112b is adjusted so that the frequency component in the vicinity of 40 GHz corresponding to the reference wave fOSC is removed, and the frequency component in the vicinity of 80 GHz corresponding to the double-multiplex wave 2 * fOSC is passed.

Reference is made to FIG. 6B. 6B is a graph showing the relationship between the harmonic distortion control voltage and the amplitude value of the output signal in the radio communication apparatus according to the second embodiment. 6B shows the voltage VgM1 applied to the transistor M1, that is, the harmonic distortion control voltage Vg. In the present embodiment, the harmonic distortion control voltage Vg is set to 0.1 [V] in the range of 0.2 [V] to 0.8 [V]. V] The pitch is changed. 6B shows the amplitude value [mVpp] of the signal fTX after modulation, that is, the signal after the output signal (doubled wave 2 * fOSC) from the frequency multiplier 10a is modulated by the modulator 20. FIG. The amplitude value is shown.

In Fig. 6B, the graph g31 shows the case where the voltage VgM2 = 0 [V] applied between the gate sources of the auxiliary transistor M2, that is, the case where no gate source voltage is applied to the auxiliary transistor M2. In addition, the graph g32 has shown the case where the voltage VgM2 = 0.5 [V] applied between the gate sources of the auxiliary transistor M2.

As can be seen by comparing the graphs g31 and g32 in Fig. 6B, the amplitude value of the signal fTX after modulation by changing the voltage VgM2 applied as the gate-to-gate voltage to the auxiliary transistor M2 from 0 [V] to 0.5 [V]. This increases overall. This is because by operating the auxiliary transistor M2, the harmonic distortion coefficient gm-2nd of the second harmonic in the auxiliary transistor M2 is increased and the amplitude value of the double-multiple wave 2 * fOSC is increased.

Moreover, the amount of current increase at this time is increased by driving the auxiliary transistor M2, that is, the drain current Id = 0.784 [mA] of the auxiliary transistor M2. In this way, since the auxiliary transistor M2 is used auxiliary for distortion generation, the transistor size is small and the increase in current consumption can be kept small.

Thus, by providing the auxiliary transistor M2 connected in parallel to the transistor M1, the gain variable range is more precisely controlled and the control width is wider than in the case of the transistor M1 alone (simplex, unit, elementary substance). You may. As a specific example, as in this embodiment, by discretely switching the voltage VgM2 applied between the gate sources of the auxiliary transistor M2, discrete gain variable control is possible as shown in graphs g31 and g32 of FIG. 6B. In addition, the voltage VgM2 may be analog controlled. With such a configuration, for example, a wider gain variable range can be realized than in the case of the transistor M1 alone, and the gain can be continuously changed in this range. In addition, since the power consumption can be kept small, the auxiliary transistor M2 can realize the gain control described above with a slight current increase.

Example 3

Next, as a third embodiment, a wireless communication device capable of selectively outputting a multiplication wave of a desired multiplication number from among a plurality of types of multiplication waves (for example, a multiplication wave and a triplex wave) will be described with reference to FIG. do. 7 is a block diagram showing a schematic configuration of a radio communication apparatus according to the third embodiment. In addition, the following description will be given focusing on the configuration of the frequency multiplier 10c whose operation differs from the above-described embodiment shown in FIG. 1, and the modulation unit 20 and the transmission unit ( The detailed description thereof is omitted.

The frequency multiplier 10c according to the present embodiment outputs a desired multiplier wave to the modulator 20 by outputting a carrier wave of a desired frequency. Furthermore, the frequency of the reference wave fOSC may be configured to be changeable. For example, as a method of outputting a carrier of 80 [GHz], a double wave 2 * fOSC may be used, or a triplex 3 * fOSC may be used. In the case of using a multiplication wave 2 * fOSC, the frequency of the reference wave fOSC may be 40 GHz. In the case of using the triplex 3 * fOSC, the frequency of the reference wave fOSC may be 26.667 GHz. In addition, in the following description, in order to simplify the explanation, the frequency of the reference wave fOSC in the input signal is set to 30 [GHz], and when the carrier wave of 60 [GHz] is outputted using a double-multiplier wave 2 * fOSC, the three A case of outputting a 90 [GHz] carrier wave using a double wave 3 * fOSC will be described as an example.

Moreover, the multiplication circuit 11c which concerns on a present Example has shown the same structure as the multiplication circuit 11 shown in FIG. 3B. That is, in this embodiment, the transistor M1 (and the circuit related to the input / output of the transistor M1) in FIG. 3B corresponds to the multiplication wave output section 111c in this embodiment. In addition, the circuit group U112 in FIG. 3B corresponds to the filter 112c in this embodiment. Further, the transistor M1 included in the multiplication circuit 11c according to the present embodiment has a harmonic distortion coefficient gm of the second harmonic when the gate-to-gate voltage Vgs (that is, the harmonic distortion control voltage Vg) is 0.55 [V]. It is assumed that -2nd represents an extreme value (maximum value). In the transistor M1, when the gate-to-gate voltage Vgs is 0.3 [V] and 0.65 [V], it is assumed that the harmonic distortion coefficient gm-3rd of the third harmonic shows an extreme value (maximum value and minimum value).

The harmonic distortion control unit 12c according to the present embodiment is configured to switch the harmonic distortion control voltage Vg between 0.3 [V], 0.55 [V], and 0.65 [V] in accordance with the characteristics of the transistor M1. As a specific example, as shown in FIG. 7, the harmonic distortion control unit 12c includes switches SW0, SW1, and SW2. Different voltages Vg0, Vg1 and Vg2 are applied to the wirings to which ON / OFF is switched by each of the switches SW0, SW1, SW2. Furthermore, in this embodiment, Vg0 = 0.3 [V], Vg1 = 0.55 [V], and Vg2 = 0.65 [V]. By switching the switches SW0 to SW2 by such a configuration, a voltage corresponding to the switch which is turned ON among the voltages Vg0 to Vg2 is applied to the multiplication wave output section 111c as the harmonic distortion control voltage Vg.

Specifically, when the switch SW1 is in the ON state, Vg1 = 0.55 [V] is applied as the harmonic distortion control voltage Vg from the harmonic distortion control unit 12a to the transistor M1 of the multiplication wave output unit 111c. In this case, in the transistor M1, in particular, the amplitude value of the double wave 2 * fOSC is emphasized.

When the switch SW0 is in the ON state, Vg0 = 0.3 [V] is applied from the harmonic distortion control unit 12a to the transistor M1 of the multiplication wave output unit 111c as the harmonic distortion control voltage Vg. In this case, especially in the transistor M1, the amplitude value of the triplex 3 * fOSC is emphasized. This also applies to the case where the switch SW2 is in the ON state. In this case, Vg0 = 0.65 [V] is applied to the transistor M1 as the harmonic distortion control voltage Vg. In this case, especially in the transistor M1, the amplitude value of the triplex 3 * fOSC is emphasized.

The filter 112c according to the present embodiment is configured to be capable of switching at least one of a frequency component to be passed in synchronization with the switching of the harmonic distortion control voltage Vg by the harmonic distortion control unit 12c and a frequency component to be removed. For example, when the switch SW1 of the harmonic distortion control unit 12c is in the ON state, the multiplication wave 2 * fOSC of 60 [GHz] is emphasized and output from the multiplication wave output section 111c. Therefore, when the switch SW1 is in the ON state, the filter 112c passes a frequency component of 60 GHz corresponding to the double-multiple wave 2 * fOSC, and other frequency components (for example, the reference wave fOSC). The characteristics of the filter may be adjusted so as to remove the triplex 3 * fOSC).

Similarly, when the switch SW0 or SW2 of the harmonic distortion control unit 12c is in the ON state, the multiplication wave 3 * fOSC of 90 [GHz] is emphasized and output from the multiplication wave output section 111c. Therefore, when the switch SW0 or SW2 is in the ON state, the filter 112c passes a frequency component of 90 GHz corresponding to the triplex 3 * fOSC, and other frequency components (for example, the reference). The characteristics of the filter may be adjusted so as to remove the wave fOSC or the double wave 2 * fOSC).

As a specific example of the adjustment of the filter characteristics, in the case of the example shown in the circuit diagram shown in Fig. 3A, the magnetic resonance frequencies of the LC series circuit CLSLLS and LC parallel circuit CLPLLP constituting the circuit group U112 may be adjusted. For example, when changing the frequency component to be removed, the capacitor CLS of the LC series circuit CLSLLS can be digitally varied so as to change the self-resonance frequency of the LC series circuit CLSLLS. In addition, when changing the frequency component to pass, the capacitor CLP of the LC parallel circuit CLPLLP may be digitally changed, and the self-resonance frequency of the LC parallel circuit CLPLLP may be changed.

As described above, the frequency of the reference wave fOSC may be changed. In this case, the filter 112c may change a filter characteristic so that the frequency component corresponding to the reference wave fOSC after a change may be made into the removal object in synchronization with the change of the frequency of the reference wave fOSC.

With such a configuration, the harmonic distortion control unit 12c according to the present embodiment can selectively output a multiplication wave of a desired multiplication factor among a plurality of types of multiplication waves (for example, a multiplication wave and a triplex wave). . In addition, since the frequency of the reference wave fOSC can be configured to be changeable, a radio communication apparatus capable of outputting carrier waves of various frequencies can be realized with a relatively low design difficulty.

As mentioned above, although preferred embodiment of this invention was described in detail, referring an accompanying drawing, this invention is not limited to this example. It is apparent that any person having ordinary knowledge in the technical field to which the present invention belongs can predict various modifications or modifications within the scope of the technical idea described in the claims. It is understood to belong to the scope.

10, 10a, 10b, 10c frequency multiplier
11, 11a, 1lb, 11c multiplication circuit
12, 12a, 12c harmonic distortion control
20 modulation section
30 transmitter
111, 111a multiplication wave output
112, 112a, 112b, 112c filter
M1 transistor
M2 auxiliary transistor
RFIN input terminal
RFOUT output terminal
U112 circuit group

Claims (9)

In the multiplication circuit,
A multiplier output unit configured to receive an input signal of a predetermined frequency, output a multiply wave of a predetermined multiplier of the input signal, and control harmonic distortion on the output of the multiply wave based on a voltage between gate sources; ,
A control unit including a plurality of switches to which different voltages are respectively applied, and configured to control the gate source voltage by supplying a voltage corresponding to a switch turned on among the plurality of switches to the gate source voltage; ,
The multiplication wave output unit includes a transistor and an auxiliary transistor connected in parallel to the transistor,
And said harmonic distortion is controlled by said control part controlling the voltage between said gate source applied to said transistor and said auxiliary transistor. The method of claim 1,
The controller is configured to control the voltage between the gate sources within a predetermined range,
And the multiplication wave output unit sets the harmonic distortion to a value corresponding to the gate-to-gate voltage under control of the gate-to-gate voltage. The method according to claim 1 or 2,
And the amplitude value of the multiplication wave is controlled to a desired range by controlling the harmonic distortion. The method of claim 2,
And a filter disposed at a rear end of the multiplication wave output unit and configured to pass at least a frequency component corresponding to the multiplication wave. The method of claim 4, wherein
And the filter is configured to cut a frequency component corresponding to the input signal. delete In a wireless communication device,
An oscillator for outputting an input signal of a predetermined frequency;
A multiplier output unit configured to receive the input signal, output a multiplier of a predetermined multiplier of the input signal, and control harmonic distortion on the output of the multiplier based on a voltage between gate sources;
A control unit including a plurality of switches to which different voltages are respectively applied, and configured to control the gate source voltage by supplying a voltage corresponding to a switch turned on among the plurality of switches to the gate source voltage;
A modulator for modulating a desired baseband signal as the carrier wave;
The multiplication wave output unit includes a transistor and an auxiliary transistor connected in parallel to the transistor,
The harmonic distortion is controlled by the control unit by controlling the voltage between the gate source applied to the transistor and the auxiliary transistor. The method of claim 7, wherein
And the oscillator is configured to control the frequency of the input signal. The method of claim 8,
And a filter configured to block a predetermined frequency component and to cut a frequency component corresponding to the input signal whose frequency is controlled by the oscillator.

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