KR102051698B1 - 단일 페이지 테이블 엔트리 내의 속성 필드들의 다중 세트들 - Google Patents

단일 페이지 테이블 엔트리 내의 속성 필드들의 다중 세트들 Download PDF

Info

Publication number
KR102051698B1
KR102051698B1 KR1020157005315A KR20157005315A KR102051698B1 KR 102051698 B1 KR102051698 B1 KR 102051698B1 KR 1020157005315 A KR1020157005315 A KR 1020157005315A KR 20157005315 A KR20157005315 A KR 20157005315A KR 102051698 B1 KR102051698 B1 KR 102051698B1
Authority
KR
South Korea
Prior art keywords
processing unit
memory
access
chunk
page table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020157005315A
Other languages
English (en)
Korean (ko)
Other versions
KR20150038513A (ko
Inventor
콜린 크리스토퍼 샤프
토마스 앤드류 사토리우스
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20150038513A publication Critical patent/KR20150038513A/ko
Application granted granted Critical
Publication of KR102051698B1 publication Critical patent/KR102051698B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/656—Address space sharing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
KR1020157005315A 2012-08-02 2013-07-18 단일 페이지 테이블 엔트리 내의 속성 필드들의 다중 세트들 Active KR102051698B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/565,434 US8938602B2 (en) 2012-08-02 2012-08-02 Multiple sets of attribute fields within a single page table entry
US13/565,434 2012-08-02
PCT/US2013/051069 WO2014022110A1 (en) 2012-08-02 2013-07-18 Multiple sets of attribute fields within a single page table entry

Publications (2)

Publication Number Publication Date
KR20150038513A KR20150038513A (ko) 2015-04-08
KR102051698B1 true KR102051698B1 (ko) 2019-12-03

Family

ID=48916200

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157005315A Active KR102051698B1 (ko) 2012-08-02 2013-07-18 단일 페이지 테이블 엔트리 내의 속성 필드들의 다중 세트들

Country Status (8)

Country Link
US (1) US8938602B2 (https=)
EP (1) EP2880540B1 (https=)
JP (3) JP2015527661A (https=)
KR (1) KR102051698B1 (https=)
BR (1) BR112015001988B1 (https=)
ES (1) ES2763545T3 (https=)
HU (1) HUE047108T2 (https=)
WO (1) WO2014022110A1 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9141559B2 (en) * 2012-01-04 2015-09-22 Intel Corporation Increasing virtual-memory efficiencies
US9378572B2 (en) 2012-08-17 2016-06-28 Intel Corporation Shared virtual memory
US9373182B2 (en) 2012-08-17 2016-06-21 Intel Corporation Memory sharing via a unified memory architecture
US9436616B2 (en) 2013-05-06 2016-09-06 Qualcomm Incorporated Multi-core page table sets of attribute fields
US20140331019A1 (en) * 2013-05-06 2014-11-06 Microsoft Corporation Instruction set specific execution isolation
US9530000B2 (en) 2013-06-14 2016-12-27 Microsoft Technology Licensing, Llc Secure privilege level execution and access protection
US9507726B2 (en) 2014-04-25 2016-11-29 Apple Inc. GPU shared virtual memory working set management
US9563571B2 (en) 2014-04-25 2017-02-07 Apple Inc. Intelligent GPU memory pre-fetching and GPU translation lookaside buffer management
US9921897B2 (en) 2016-01-06 2018-03-20 International Business Machines Corporation Testing a non-core MMU
GB2547242B (en) 2016-02-11 2018-05-23 Advanced Risc Mach Ltd Graphics processing
US10019377B2 (en) * 2016-05-23 2018-07-10 Advanced Micro Devices, Inc. Managing cache coherence using information in a page table
US9864700B1 (en) * 2016-08-17 2018-01-09 Advanced Micro Devices, Inc. Method and apparatus for power reduction in a multi-threaded mode
KR101942663B1 (ko) * 2017-09-28 2019-01-25 한국과학기술원 가상 메모리 주소 변환 효율화를 위한 연속성 활용 주소 변환 방법 및 시스템
US10747679B1 (en) * 2017-12-11 2020-08-18 Amazon Technologies, Inc. Indexing a memory region
CN110198331B (zh) * 2018-03-28 2022-11-25 腾讯科技（上海）有限公司 一种同步数据的方法及系统
US10969980B2 (en) * 2019-03-28 2021-04-06 Intel Corporation Enforcing unique page table permissions with shared page tables
CN112115521B (zh) * 2019-06-19 2023-02-07 华为技术有限公司 数据访问方法及装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070168644A1 (en) 2006-01-17 2007-07-19 Hummel Mark D Using an IOMMU to Create Memory Archetypes

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3454854B2 (ja) * 1992-01-16 2003-10-06 株式会社東芝 メモリ管理装置及び方法
US6446034B1 (en) 1998-12-16 2002-09-03 Bull Hn Information Systems Inc. Processor emulation virtual memory address translation
US6286092B1 (en) 1999-05-12 2001-09-04 Ati International Srl Paged based memory address translation table update method and apparatus
US7444636B2 (en) 2002-07-15 2008-10-28 Hewlett-Packard Development Company, L.P. Method and system of determining attributes of a functional unit in a multiple processor computer system
US7111145B1 (en) 2003-03-25 2006-09-19 Vmware, Inc. TLB miss fault handler and method for accessing multiple page tables
US7539842B2 (en) 2006-08-15 2009-05-26 International Business Machines Corporation Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables
US7865675B2 (en) 2007-12-06 2011-01-04 Arm Limited Controlling cleaning of data values within a hardware accelerator
US8015361B2 (en) 2007-12-14 2011-09-06 International Business Machines Corporation Memory-centric page table walker
US8099541B2 (en) * 2008-01-22 2012-01-17 Globalfoundries Inc. Minivisor entry point in virtual machine monitor address space
US8397049B2 (en) * 2009-07-13 2013-03-12 Apple Inc. TLB prefetching
US20110016290A1 (en) 2009-07-14 2011-01-20 Arie Chobotaro Method and Apparatus for Supporting Address Translation in a Multiprocessor Virtual Machine Environment
US8386745B2 (en) * 2009-07-24 2013-02-26 Advanced Micro Devices, Inc. I/O memory management unit including multilevel address translation for I/O and computation offload
US20110161620A1 (en) 2009-12-29 2011-06-30 Advanced Micro Devices, Inc. Systems and methods implementing shared page tables for sharing memory resources managed by a main operating system with accelerator devices
US8669990B2 (en) * 2009-12-31 2014-03-11 Intel Corporation Sharing resources between a CPU and GPU
US20120233439A1 (en) 2011-03-11 2012-09-13 Boris Ginzburg Implementing TLB Synchronization for Systems with Shared Virtual Memory Between Processing Devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070168644A1 (en) 2006-01-17 2007-07-19 Hummel Mark D Using an IOMMU to Create Memory Archetypes

Also Published As

Publication number Publication date
EP2880540B1 (en) 2019-09-25
CN104508641A (zh) 2015-04-08
JP2019109906A (ja) 2019-07-04
JP6728419B2 (ja) 2020-07-22
BR112015001988B1 (pt) 2022-03-15
JP2018041485A (ja) 2018-03-15
JP2015527661A (ja) 2015-09-17
HUE047108T2 (hu) 2020-04-28
WO2014022110A1 (en) 2014-02-06
US8938602B2 (en) 2015-01-20
KR20150038513A (ko) 2015-04-08
EP2880540A1 (en) 2015-06-10
ES2763545T3 (es) 2020-05-29
BR112015001988A2 (pt) 2017-07-04
US20140040593A1 (en) 2014-02-06

Similar Documents

Publication Publication Date Title
KR102051698B1 (ko) 단일 페이지 테이블 엔트리 내의 속성 필드들의 다중 세트들
US9436616B2 (en) Multi-core page table sets of attribute fields
JP6796304B2 (ja) 最終レベルキャッシュシステム及び対応する方法
CN107636625B (zh) 用于共享系统高速缓存的虚拟化控制的方法和装置
US20170177497A1 (en) Compressed caching of a logical-to-physical address table for nand-type flash memory
CN115481054B (zh) 数据处理方法、装置及系统、系统级soc芯片及计算机设备
JP2016522942A (ja) 高性能でかつ低コストのフラッシュ変換層のためのシステムおよび方法
CN105830059A (zh) 文件访问方法、装置及存储设备
US20160188251A1 (en) Techniques for Creating a Notion of Privileged Data Access in a Unified Virtual Memory System
US9367478B2 (en) Controlling direct memory access page mappings
US9916255B2 (en) Data storage based on memory persistency
US12380034B2 (en) Extended attributes for shared page tables
JP6676052B2 (ja) 不均一メモリアーキテクチャにおける改善されたレイテンシを可能にするためのシステムおよび方法
US8347064B1 (en) Memory access techniques in an aperture mapped memory space
US20160103766A1 (en) Lookup of a data structure containing a mapping between a virtual address space and a physical address space
CN104508641B (zh) 单页表条目内的多组属性字段

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20150227

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20180702

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20190719

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20191030

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20191127

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20191127

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20220921

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20230921

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee