KR102051304B1 - One-transistor dram cell device based on polycrystalline silicon and fabrication method thereof - Google Patents

Abstract

The present invention intentionally forms a semiconductor layer (eg, a polysilicon layer) having relatively low crystallinity at the lower end of the body (active region) to physically trap holes accumulated in the cell body, thereby dramatically improving retention time. The present invention provides a polysilicon based 1T DRAM cell device which can be manufactured at low cost, and can be processed in functional blocks and a batch process.

Description

Polysilicon based 1T DRAM cell device and method of manufacturing the same {ONE-TRANSISTOR DRAM CELL DEVICE BASED ON POLYCRYSTALLINE SILICON AND FABRICATION METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more particularly, to a 1T DRAM cell device having a single transistor based on polysilicon without a capacitor and a method of manufacturing the same.

DRAM, a dynamic random access memory, is a representative memory device in the semiconductor memory field, along with NAND flash memory, and is a fiercely competitive field among semiconductor leaders including Korea.

Conventional DRAMs have one transistor and one capacitor, i.e., a 1T1C structure. Due to the complex process resulting from the presence of capacitors, they cannot be integrated simultaneously with the CPU but must be manufactured and supplied in a stand-alone type, while the capacity growth is slower than flash memory devices based on the same ultra-fine semiconductor process. Difficulty in dimensional stacking has been pointed out as a technical limitation of 1T1C DRAM.

Accordingly, capacitor-free 1T DRAMs have been proposed, but have a shorter retention time than conventional 1T1C DRAMs. In addition, as in Korean Patent Laid-Open Publication No. 10-2017-0055031, when the cell body is insulated with an investment oxide of an expensive silicon-on-insulator (SOI) substrate, the unit cost of the device increases, and a tunneling field effect transistor ( The use of TFETs also reduces the possibility of batch processing and functional blocks consisting of typical MOSFET devices.

The present invention has been proposed to solve the above-described problems of the conventional 1T DRAM cell device, by intentionally forming a polysilicon region at the lower end of the DRAM cell to physically trap holes accumulated in the cell body, thereby significantly reducing retention time. An object of the present invention is to provide a polysilicon-based 1T DRAM cell device capable of improving and increasing the possibility of functional blocks and batch processing at low cost by having a general MOSFET structure in a bulk substrate or the like, and a method of manufacturing the same.

In order to achieve the above object, the 1T DRAM cell device according to the present invention comprises a blocking insulating film; A first semiconductor layer formed on the blocking insulating film; A second semiconductor layer formed on the first semiconductor layer; A source / drain region formed on the second semiconducting layer with a channel region interposed therebetween, the source / drain region having a conductivity type opposite to the channel region; And a gate formed on the channel region with a gate insulating layer interposed therebetween.

Another feature of the 1T DRAM cell device according to the present invention is that the first semiconductor layer has a lower crystallinity than the same semiconductor material layer or the second semiconductor layer as the second semiconductor layer.

The semiconductor material layer is another feature of the 1T DRAM cell device according to the present invention that the layer of silicon material.

The blocking insulating film is a silicon oxide film formed on a silicon substrate, the channel region is provided to form a p-type channel at a driving voltage of the gate, and the first semiconductor layer captures holes for trapping holes at grain boundaries. The layer is another feature of the 1T DRAM cell device according to the present invention.

The source / drain regions are formed such that each lower portion thereof meets the first semiconductor layer, and has an ion implantation layer having a higher concentration than other portions of the first semiconductor layer near an interface between the blocking insulating layer and the first semiconductor layer. It is another feature of the 1T DRAM cell device according to the present invention.

A method of manufacturing a 1T DRAM cell device according to the present invention includes a first step of forming a silicon oxide film on a silicon substrate by chemical vapor deposition or thermal oxidation; A second step of forming an active region of a silicon-based material on the silicon oxide layer through chemical vapor deposition; Forming a gate insulating film on the active region, and forming a gate on the gate insulating film; And a fourth step of ion implanting the gate as a mask to form a source / drain region having a conductivity type opposite to that of the active region.

Here, in the second step, the first semiconductor layer is formed of polysilicon having low crystallinity by a low temperature process, and then a high temperature process having a higher temperature than the low temperature process is continuously performed to have a higher crystallinity than the first semiconductor layer. A second semiconductor layer may be formed of crystalline silicon, and the source / drain region of the fourth step may be formed with the channel region under the gate interposed in the second semiconductor layer.

An ion implantation process may be further performed to form a peak point of ion implantation near the interface between the silicon oxide film and the polysilicon between the second and third steps.

The ion implantation process between the second step and the third step may be taken instead of or in parallel with the method of changing the process temperature in the second step.

The present invention intentionally forms a semiconductor layer (eg, a polysilicon layer) having relatively low crystallinity at the lower end of the body (active region) to physically trap holes accumulated in the cell body, thereby dramatically improving retention time. It can be produced at low cost and can be processed in functional blocks and batch processes.

1 is a cross-sectional view illustrating a structure of a 1T DRAM cell device according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

1T DRAM cell device according to an embodiment of the present invention, as shown in Figure 1, the blocking insulating film 20; A first semiconductor layer 30 formed on the blocking insulating layer; A second semiconductor layer 40 formed on the first semiconductor layer; A source 42 / drain region 44 spaced apart from each other with a channel region 41 interposed therebetween in the second semiconducting layer, the source 42 / drain region 44 having a conductivity type opposite to the channel region; And a gate 60 formed on the channel region 41 with the gate insulating layer 50 interposed therebetween.

Here, the first semiconductor layer 30 and the second semiconductor layer 40 constitute an active region (body) in which cell elements are made, and like an ordinary cell element, an insulating insulating film (not shown) on each side, etc. It is surrounded and electrically isolated from neighboring cells.

The blocking insulating layer 20 is to insulate holes and the like introduced by insulating the cell body from the outside. If the insulator is used, the blocking insulating layer 20 may be formed of a glass or flexible material layer instead of the substrate. If formed on 10) may be a deposited or buried oxide layer, specifically, a silicon oxide film. The silicon substrate 10 may be a bulk substrate as well as a silicon-on-insulator (SOI) substrate.

The channel region 41 is provided such that a p-type channel is formed at a driving voltage (eg, V _GS <0) of the gate 60, and the first semiconductor layer 30 has holes in a grain boundary. It may be a hole trapping layer to capture. By doing so, it is possible to physically capture a large number of holes in the lower part of the cell body, thereby improving retention time.

The first semiconductor layer 30 may be formed as a heterojunction with a different semiconductor material layer from the second semiconductor layer 40, but the same semiconductor material layer may have lower crystallinity than the second semiconductor layer in any case. Shall be. By doing so, the mobility of carriers (electrons or holes) in the channel region 41 of the second semiconductor layer 40 can be increased to enable low-power driving, as well as more grain boundaries of the first semiconductor layer 30. It has the advantage of capturing holes.

As a specific example, the first semiconductor layer 30 may be formed of polysilicon, and the second semiconductor layer 40 may be formed of crystalline silicon.

In another embodiment, although not shown, in FIG. 1, the source 42 / drain region 44 may be formed such that each lower portion thereof meets the first semiconductor layer 30.

In addition, an ion implantation layer having a higher concentration than that of other portions of the first semiconductor layer 30 may be further formed near the interface between the blocking insulating layer 20 and the first semiconductor layer 30.

Next, a method of manufacturing a 1T DRAM cell device according to the present invention for manufacturing the structure of FIG. 1 will be described.

First, the silicon oxide film 20 is formed on the silicon substrate 10 by chemical vapor deposition (CVD) or thermal oxidation (first step).

Subsequently, active regions 30 and 40 are formed of silicon-based material on the silicon oxide layer 20 through chemical vapor deposition (second step).

At this time, in the second step, after forming the first semiconductor layer 30 of polycrystalline silicon having a low crystallinity by a low temperature process, a high temperature process having a higher temperature than the low temperature process is continuously performed to determine the first semiconductor layer. By forming the second semiconductor layer 40 with high crystalline silicon, the first semiconductor layer is formed of low crystalline polysilicon to form a hole trapping layer underneath, while continuously having a relatively high crystallinity thereon. The second semiconductor layer may be formed of crystalline silicon to increase the mobility of carriers (electrons or holes) during cell operation.

Next, a gate insulating film 50 is formed on the active region, and a gate 60 is formed on the gate insulating film (third step).

Subsequently, ion implantation is performed using the gate 60 as a mask to form a source 42 / drain region 44 having a conductivity type opposite to that of the active regions 30 and 40 (fourth step). In this case, the source 42 / drain region 44 is formed in the second semiconductor layer 40 with the channel region 41 under the gate 60 interposed therebetween.

In another embodiment, an ion implantation process may be further performed between the second and third steps such that a peak point of ion implantation is formed near an interface between the silicon oxide film 20 and the first semiconductor layer 30, which is polysilicon. By proceeding, the crystallinity of the first semiconductor layer 30 may be further reduced.

Of course, the ion implantation process between the second step and the third step may be taken instead of the method of changing the process temperature in the second step or used in parallel.

Finally, an operation method of the 1T DRAM cell device according to the embodiment of FIG. 1 will be briefly described.

<Write operation>

The body voltage V _B = 0 applied to the silicon substrate 10, the source voltage V _S = 0 applied to the source region 42, the voltage between gate and source V _GS <0, and the voltage between drain and source V _DS > 0. Each is applied to the band-to-band tunneling valence band electrons of the p-type channel region 41 to the drain region 44.

At this time, free holes are formed in the p-type channel and written in a 0 or 1 state, depending on the extent to which they are trapped in the grain boundary and lower hole trapping layer of polysilicon, the first semiconductor layer 30. You lose. Additional pulses of V _GS > 0 may be applied for effective hole migration to the lower hole trapping layer.

<Read operation>

A voltage of V _B = 0, V _S = 0, V _GS > V _th (threshold voltage of MOSFET) and V _DS > 0 is applied to determine the 0 and 1 states of the memory device by the height of the drain current.

At this time, due to high impact ionization to V _DS it is excessive it is preferable to apply the additional electronics, as appropriate voltage V _DS of the small size, so it difficult to make accurate memory state is determined by the hole pairs are generated.

<Clear operation>

The erase operation is forcibly removing trapped holes from the trap by applying a voltage of V _B = 0, V _S = 0, V _GS <0, and V _DS <0. Since holes that are not trapped are naturally destroyed by recombination, V _S <0, V _G <0, and V _D <0 are applied to prevent the outflow of holes due to agitation of the source region 42 and the drain region 44. This can be done at each junction.

At this time, in order to prevent the holes from being held in the lower portion of the gate 60, it is preferable to set the conditions such that V _S and V _D can have a negative value larger than the surface potential of the channel caused by V _G. Do.

10: silicon substrate
20: deposited or buried oxide film (silicon oxide film)
30: first semiconductor layer
40: second semiconductor layer
41: channel area
42: source area
44: drain region
50: gate insulating film
60: gate

Claims (7)

Blocking insulating film;
A first semiconductor layer formed on the blocking insulating layer;
A second semiconductor layer formed on the first semiconductor layer;
A source / drain region formed on the second semiconducting layer with a channel region interposed therebetween so as to have a conductivity type opposite to that of the channel region; And
A gate formed on the channel region with a gate insulating film interposed therebetween,
And the first semiconductor layer is a hole trapping layer that traps holes at grain boundaries.
The method of claim 1,
And the first semiconductor layer has a lower crystallinity than the same semiconductor material layer or the second semiconductor layer as the second semiconductor layer.
The method of claim 2,
And the first semiconductor layer is polysilicon and the second semiconductor layer is crystalline silicon.
The method according to any one of claims 1 to 3,
The blocking insulating film is a silicon oxide film formed on a silicon substrate,
The channel region is a 1T DRAM cell device, characterized in that the p-type channel is formed by the driving voltage of the gate.
The method of claim 4, wherein
The source / drain regions are formed such that each lower portion thereof meets the first semiconductor layer,
And an ion implantation layer having a higher concentration than other portions of the first semiconductor layer near an interface between the blocking insulating film and the first semiconductor layer.
Forming a silicon oxide film on the silicon substrate by chemical vapor deposition or thermal oxidation;
Forming an active region of a silicon-based material on the silicon oxide layer through chemical vapor deposition;
Forming a gate insulating film on the active region, and forming a gate on the gate insulating film; And
A fourth step of forming a source / drain region of the conductivity type of the opposite type to the active region by ion implantation using the gate as a mask,
In the second step, the first semiconductor layer is formed of polysilicon having low crystallinity by a low temperature process, and then a high temperature process having a higher temperature than the low temperature process is continuously performed to form crystalline silicon having a higher crystallinity than the first semiconductor layer. To form a second semiconductor layer,
And the source / drain regions of the fourth step are formed in the second semiconductor layer with the channel region under the gate interposed therebetween.
The method of claim 6,
And further performing an ion implantation process such that a peak point of ion implantation is formed near the interface between the silicon oxide film and the polysilicon between the second and third steps.

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