KR102050551B1 - Power semiconductor having trench of step structure and method of manufacturing thereof - Google Patents

Abstract

The present invention relates to a power semiconductor. A manufacturing method of a power semiconductor having a step structure trench comprises the steps of: depositing a hard mask on an upper surface of a first conductive epi-layer in an initial thickness; forming a trench pattern by etching the hard mask; forming a first trench which is extended from the upper surface of the first conductive epi-layer in a vertical direction by using the trench pattern and is inclined at a first trench side wall angle; allowing the trench pattern to be primarily extended in a horizontal direction to have a first pattern side wall angle; forming a second trench which is extended from a bottom of the first trench in the vertical direction by using the primarily extended trench pattern and is inclined at a second trench side wall angle; and forming a second conductive binding region on a side wall of the first trench and the side wall of the second trench.

Description

Power semiconductor having trenches having a stepped structure and a method for manufacturing the same

The present invention relates to a power semiconductor.

In the case of silicon carbide power semiconductor, the ion implantation process is relatively difficult compared to silicon power semiconductor. Silicon carbide has a lower thermal diffusion coefficient and a stronger silicon-carbon bond than silicon, making it difficult to apply a silicon-based ion implantation process and a trench process. In the case of silicon, a relatively simple process of forming an ion implantation pattern on the surface of a silicon wafer with photoresist or polysilicon, and diffusing and activating ions through heat treatment after ion implantation is applied. In the case of silicon carbide, since ions must be implanted at high energy and high temperature, an ion implantation pattern formed of a material such as photoresist cannot be used, and a hard mask pattern such as silicon oxide film is used. When using a hard mask pattern, impurities may remain on the wafer surface or the surface of the wafer may be rough in the process of removing the already used pattern and forming a new pattern. On the other hand, the rigid physical properties of silicon carbide acts as a major cause of limiting the depth of the trench.

The present invention seeks to provide a silicon carbide Schottky diode in which the sidewalls of the trench are stepped.

Embodiments according to one aspect of the present invention provides a method for manufacturing a power semiconductor having a stepped trench. In the method of manufacturing a power semiconductor having a trench having a stepped structure, depositing a hard mask with an initial thickness on an upper surface of a first conductivity type epi layer, etching the hard mask to form a trench pattern, and using the trench pattern. Forming a first trench extending in a vertical direction from the top surface of the first conductive epitaxial layer and inclined at a first trench sidewall angle, wherein the trench pattern is first expanded in a horizontal direction to have a first pattern sidewall angle Forming a second trench extending vertically from the bottom of the first trench and inclined at a second trench sidewall angle using a first extended trench pattern and forming a second conductivity type junction region in the first trench And forming a sidewall of the second trench and a sidewall of the second trench.

In example embodiments, the trench pattern may extend in the horizontal direction by wet etching, and the first trench and the second trench may extend in the vertical direction by dry etching.

In one embodiment, a method of manufacturing a power semiconductor having a trench having a stepped structure may further include a second extension in a horizontal direction so that the first extended trench pattern has a second pattern sidewall angle after forming the second trench. And forming a third trench extending vertically from the bottom of the second trench and inclined at a third trench sidewall angle using a second extended trench pattern, wherein the second conductivity type junction is formed. Forming a region on the sidewall of the first trench and the sidewall of the second trench may include forming the second conductivity type junction region on the sidewall of the third trench.

In example embodiments, a lower width of the first trench may be greater than an upper width of the second trench, and a lower width of the second trench may be greater than an upper width of the third trench.

An embodiment according to one aspect of the present invention provides a power semiconductor having a trench of a stepped structure. A power semiconductor having a trench having a stepped structure includes a first conductive substrate formed of silicon carbide containing a first conductive impurity, a first conductive epitaxial layer epitaxially grown on the first conductive substrate, and the first conductive epitaxial layer. 1, a stepped trench extending vertically from an upper surface of the conductive epitaxial layer, a second conductive junction region formed in the first conductive epitaxial layer along the bottom and sidewalls of the trench, and filling the inside of the trench. And a schottky metal layer formed on an upper surface of the first conductive epitaxial layer, an anode formed on an upper surface of the schottky metal layer, and a cathode electrode formed on a lower surface of the first conductive type substrate.

In an embodiment, the trench includes a first trench inclined at a first trench sidewall angle, a second trench extending in a vertical direction from a bottom of the first trench and inclined at a second trench sidewall angle, wherein the first trench is inclined at a second trench sidewall angle. The second trench sidewall angle is greater than the first trench sidewall angle, and a lower width of the first trench is greater than an upper width of the second trench so that a step may be formed in the connection region between the first trench and the second trench. .

In an embodiment, the width of the second conductive junction region formed along the sidewalls of the first trench and the sidewall of the second trench increases vertically downward, while the width of the second conductive junction region in the connection region decreases. can do.

In example embodiments, the method may further include a third trench extending in a vertical direction from the bottom of the second trench and inclined at a third trench sidewall angle, wherein the third trench sidewall angle is greater than the second trench sidewall angle. The lower width of the second trench is greater than the upper width of the third trench, so that a step may be formed in the connection region between the second trench and the third trench.

According to the exemplary embodiment of the present invention, the trench may be formed in a self-aligning manner by using one mask so that the ion implantation region may be formed on the sidewall of the trench without using the tilt ion implantation. In particular, it is possible to control the ion implantation depth by the trench.

In the following, the invention is described with reference to the embodiments shown in the accompanying drawings. For clarity, the same components have been assigned the same reference numerals throughout the accompanying drawings. Configurations shown in the accompanying drawings are merely exemplary embodiments to illustrate the present invention, but are not intended to limit the scope of the present invention. In particular, the accompanying drawings, in order to help understand the invention, some of the components are exaggerated. Since the drawings are meant for understanding the invention, it should be understood that the width or thickness of the components represented in the drawings may vary in actual implementation. On the other hand, the same components are described with reference to the same reference numerals throughout the detailed description of the invention.
1 is a cross-sectional view illustrating a power semiconductor having a stepped trench.
2 is a diagram exemplarily illustrating a difference between hard mask etching and silicon carbide etching.
3 and 4 are cross-sectional views illustrating a step of forming a stepped trench.
5 is a cross-sectional view illustrating an ion region formed by vertical ion implantation and an ion region formed by tilt ion implantation.

The present invention may be variously modified and have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail with reference to the accompanying drawings. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

If an element such as a layer, region or substrate is described as being on or "onto" another element, the element may be directly above or directly above another element and There may be intermediate or intervening elements. On the other hand, if one element is mentioned as being "directly on" or extending "directly onto" another element, no other intermediate elements are present. In addition, when one element is described as being "connected" or "coupled" to another element, the element may be directly connected to or directly coupled to another element, or an intermediate intervening element may be present. have. On the other hand, when one element is described as being "directly connected" or "directly coupled" to another element, no other intermediate element exists.

"Below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" Relative terms such as "vertical" may be used herein to describe a relationship of one element, layer or region to another element, layer or region, as shown in the figures. It is to be understood that these terms are intended to encompass other directions of the device in addition to the orientation depicted in the figures.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the sake of understanding, a power semiconductor device having a general structure will be described by way of example.

1 is a cross-sectional view illustrating a power semiconductor having a stepped trench.

Referring to FIG. 1, the silicon carbide power semiconductor may be a trench junction barrier schottky diode. The trench junction barrier Schottky diode is divided into an active region and an edge termination region at least surrounding the active region. The active region includes a Schottky junction and a PN junction. The edge termination region may have various structures such as a guard ring, a bevel, and a junction termination extension.

The trench junction barrier Schottky diode includes a first conductive substrate 100, a first conductive epitaxial layer 105, a second conductive junction region 120, a second conductive buffer region 130, and an insulating layer ( 140, the Schottky metal layer 150, the anode electrode 160, the ohmic bonding layer 170, and the cathode electrode 180. Here, the first conductivity type is doped with n-type impurities, and the second conductivity type refers to a region or layer doped with p-type impurities, but vice versa.

The first conductivity type substrate 100 is formed by doping the first conductivity type impurities to a 4H-SiC or 6H-SiC substrate. The concentration of the first conductivity type impurity of the first conductivity type substrate 100 may be about 5 × 10 ¹⁸ cm ⁻³ , and the thickness of the first conductivity type substrate 100 may be about 9.8 μm.

The first conductivity type epi layer 105 is formed by epitaxially growing silicon carbide doped with a first conductivity type impurity on an upper portion of the first conductivity type substrate 100. Here, the concentration of the first conductivity type impurities of the first conductivity type epi layer 105 may be about 9 × 10 ¹⁵ , and the thickness of the first conductivity type epi layer 105 may be about 350 μm.

In the active region, the stepped trench 110 extends substantially vertically from the top surface of the first conductivity type epi layer 105 toward the interior of the first conductivity type epi layer 105. The sidewalls of the stepped trench 110 may be formed in a stepped structure, and the width of the trench may decrease as it is deeper from the top surface of the first conductivity type epitaxial layer 105. Meanwhile, at least a portion of the sidewalls of the stepped trench 110 may be formed to be substantially inclined so that the width of the trench may decrease as it is deeper from the top surface of the first conductivity type epi layer 105.

The plurality of second conductivity type junction regions 120 are formed on sidewalls and bottoms of the stepped trenches 110. The plurality of second conductivity type junction regions 120 may be formed by ion implanting a second conductivity type impurity, for example, Al, into the sidewalls and the bottom of the stepped structure trench 110. By ion implantation, the plurality of second conductive junction regions 120 are moved into the first conductive epitaxial layer 105 in a vertical direction from the sidewalls of the stepped trench 110 and the bottom of the stepped trench 110. It is formed to extend. Here, the concentration of the second conductivity type impurity in the second conductivity type junction region 120 is about 1 × 10 ¹⁸ cm ⁻³ , and the depth of the second conductivity type junction region 120 is the stepped trench 110. About 0.7 μm from the sidewalls and the bottom of the substrate. The structure of the stepped trench 110 and the second conductivity type junction region 120 will be described in detail with reference to FIG. 5 below.

The second conductive buffer region 130 is formed over the active region and the edge termination region of the upper surface of the first conductive epitaxial layer 105 and surrounds the active region. The second conductivity type buffer region 130 may be formed by ion implanting a second conductivity type impurity into the first conductivity type epi layer 105. The width of the second conductivity type buffer region 130 is larger than that of the second conductivity type junction region 120. One side of the second conductivity type buffer region 130 contacts the Schottky metal layer 150 and extends toward the edge termination region in the horizontal direction. Here, the concentration of the second conductivity type impurities in the second conductivity type buffer region 130 is about 1 × 10 ¹⁸ to about 1 × 10 ²⁰ cm ⁻³ , and the depth of the second conductivity type buffer region 130 is About 05 to 0.7 μm.

The insulating layer 140 is formed on a portion of the buffer layer 125 and on the first conductive epitaxial layer 105 in the edge termination region. The insulating layer 140 is formed to surround the plurality of second conductivity type junction regions 120 to define an active region. The insulating layer 140 is formed to overlap at least a portion of the second conductivity type buffer region 130. The insulating layer 140 extends in the horizontal direction toward the first conductive base region 130 at a position where a part of the left side of the second conductive buffer region 130 is exposed, so that the insulating layer 140 of the second conductive buffer region 130 is formed. Cover the rest. The insulating layer 140 may be formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like. Here, the thickness of the insulating layer 140 may be about 1.0 to about 2.0 ㎛.

The schottky metal layer 150 is formed on the first conductive epitaxial layer 105 to be schottky bonded to a portion of the first conductive epitaxial layer 105 and filled in the stepped trench 110. The schottky metal layer 150 may extend in a horizontal direction to cover a portion of the insulating layer 140.

The anode electrode 160 is formed on the schottky metal layer 150, and the cathode electrode 180 is formed on the lower portion of the first conductivity type substrate 100. The anode electrode 160 and the cathode electrode 180 are formed of a metal or a metal alloy. The silicide layer 170 for ohmic contact is formed between the first conductivity type substrate 100 and the cathode electrode 180.

Hereinafter, the operation of the trench junction barrier Schottky diode having a plurality of second conductivity type junction regions 120 will be described.

The trench junction barrier Schottky diode having the second conductivity type junction region 120 formed inside the stepped trench 110 may improve breakdown voltage and leakage current characteristics when compared with a conventional Schottky diode. The plurality of second conductive bonding regions 120 are PN bonded to the first conductive epitaxial layer 105, and the Schottky metal layer 150 is in Schottky contact with the first conductive epitaxial layer 105. The second conductivity type junction region 120 formed in the sidewalls of the stepped trench 110 increases the area of the PN junction. In particular, when compared with conventional trench junction barrier Schottky diodes, the bottom of the staircase stepped trench 110 is formed at a deeper location. Thus, the depletion layer formed inside the first conductivity type epi layer 105 is also formed in the deeper region. The deeply formed depletion layer allows for effective field dispersion.

When the reverse voltage is applied, the plurality of second conductive junction regions 120 form a depletion layer due to the PN junction with the first conductive epitaxial layer 105. The depletion layer formed along the second conductivity type junction region 120 on the sidewalls of the stepped trench 110 extends in the horizontal direction, and the depletion layer formed along the bottom extends in the vertical direction. Since the depletion layer formed along the periphery of the plurality of second conductivity type junction regions 120 blocks a path through which leakage current can flow, the depletion layer has a lower leakage current value than that of a general Schottky diode. In particular, the depletion layer formed along the periphery of the plurality of second conductivity type junction regions 120 may relatively reduce the electric field concentrated in the region where the Schottky metal layer 150 and the first conductivity type epi layer 105 contact. Can be. As a result, a threshold voltage relatively higher than that of a typical Schottky diode can be realized.

2 is a diagram exemplarily illustrating a difference between hard mask etching and silicon carbide etching.

The hard mask 200 is formed on the upper surface of the first conductivity type epi layer 105 to be used as the trench pattern 210. The trench pattern is formed by etching the hard mask to expose the top surface of the silicon carbide epitaxial layer on which the trench is to be formed. The upper width W _PT of the trench pattern may be greater than the lower width W _PB of the trench pattern.

The hard mask 200 has an initial thickness th _HM and is etched during both the hard mask etching and the silicon carbide etching to reduce the thickness. In order to etch by the target depth E _Depth of the trench 110, n-1 hard mask etching and n silicon carbide etching are performed, where the hard mask etching is wet etching and the silicon carbide etching is dry etching. The initial thickness th _HM = T _Min + T _Etch of the hard mask 200 may be. Here, the minimum thickness T _Min of the hard mask 200 is about 1.5 μm, and is a thickness of the hard mask required for use as a blocking mask during ion implantation. T _Etch is the total etching thickness of the hard mask etched during n-1 hard mask etching and n silicon carbide etching, and may be T _Etch = E _Depth / E _Sel + E _HM . Here, the target depth E _Depth is E _SiC ⅹ n, E _Sel is a silicon carbide-hard mask etch selectivity, and E _HM is E _{SiO 2} ⅹ (n-1). E _SiC is an etching depth of the first conductivity type epi layer 105 by one silicon carbide etching, and E _SiO2 is an etching thickness of the hard mask 200 by one hard mask etching.

The trench patterns 210 are etched with the sidewalls inclined by hard mask etching. Hard mask etching is isotropic wet etching, and silicon carbide etching is anisotropic dry etching. In the case of wet etching, a difference occurs in the flow of the etchant in the upper and lower portions of the trench pattern 210. This is the reason that the lower etching rate is different. As a result, the width W _PT of the upper portion of the trench pattern 210 is greater than the width W _PB of the lower portion thereof, such that the sidewall of the trench pattern 210 is etched obliquely. The trench pattern 210 top-bottom width difference is greater every subsequent hard mask etch, and the slope of the sidewalls due to the trench pattern 210 top-bottom width difference affects the slope of the trench 110 sidewalls during silicon carbide etching. Crazy That is, as the upper-bottom width difference of the trench pattern 210 increases, the etching gas is not smoothly discharged from the lower portion of the trench 110, so that the etching rate difference between the upper and lower portions of the trench 110 increases. As a result, the top-bottom width difference of the trench 110 may be large each time silicon carbide etching is repeated.

The hard mask is not removed during n-1 hard mask etching and n silicon carbide etching. That is, the stepped trench 110 is formed in a self-aligning manner by using one hard mask. Meanwhile, the hard mask 200 is also used for ion implantation into the sidewalls and the bottom of the stepped trench 110.

3 and 4 are cross-sectional views illustrating a step of forming a stepped trench. It is to be understood that numerical values, such as ratios, to be described below, may vary depending on process parameters such as etching gas, etchant, time, temperature and the like. Meanwhile, an example in which three silicon carbide etchings are performed to achieve the target depth of the trench 110 determined by the ion implantation depth is described. However, the number of times of performing the silicon carbide etching is performed according to the etching depth and the target depth by one silicon carbide etching. May be increased or decreased.

3 and 4 together, in step (a), a hard mask 200 is formed on the top surface of the first conductivity type epi layer 105. The hard mask 200 may be formed by, for example, depositing SiO ₂ to an initial thickness th ₁ using a PECVD process. In the PECVD process, SiO ₂ may be deposited at a deposition rate of 1.0-1.3 μm / min at about 400 ° C. using a mixed gas of SiH ₄ and O ₂ .

In step (b), a PR pattern 305 is formed on the top surface of the hard mask 200. The PR pattern 305 may be formed by applying the photoresist 300 and removing the photoresist at a position where the trench pattern 210 is to be formed.

In step (c), trench patterns 210 are formed in hard mask 200. The trench pattern 210 may be formed by dry etching the hard mask 200 at an etching rate of about 0.5 μm / min or less using an etching gas including CF ₄ , CHF ₃ , Ar, and O ₂ . Here, the etching selectivity of SiO ₂ and PR is 4: 1 or less. The etch selectivity may be substantially perpendicular to sidewalls of the trench pattern 210.

In step (d), the photoresist 200 is removed. The upper width of the trench pattern 210 is w ₁₁ and the lower width is w ₂₁ . Here, the upper width w ₁₁ may be about 14% to about 17% greater than the lower width w ₂₁ , and the upper width w ₁₁ may be about 24% to about 27% of the initial thickness th ₁ .

In step (e), a first trench 111 is formed in the first conductivity type epi layer 105. The first trench 111 may be formed by dry etching the first conductive epitaxial layer 105 at an etching rate of about 1.0 μm / min or less using an etching gas including SF ₆ , Ar, and O ₂ . Here, the etching selectivity of SiC and SiO ₂ is 5: 1 or less. The sidewalls of the first trench 111 may be formed to be inclined at the angle of the first trench sidewalls. Here, the side wall angle is an angle between the vertical straight line and the side wall. The first trench 111 is formed by first etching the first conductive epitaxial layer 105 formed of silicon carbide by the first depth d ₁ in the vertical direction. The upper width of the first trench 111 is w ₂₂ and the lower width is w ₃₂ , which may be continuously etched and gradually widened in subsequent etching. Here, the upper width w ₂₂ may be about 11% to about 14% greater than the lower width w ₃₂ , and the first depth d ₁ may be about 0.5 μm to about 1.0 μm. Meanwhile, when the first epitaxial layer is etched, the hard mask 200 is also etched, so that the thickness th ₂ of the hard mask 200 may be reduced to about 96% to 98% of the initial thickness th ₁ and the trench pattern 210. ) Has a top width of w ₁₂ and a bottom width of w ₂₂ . Here, the upper width w ₁₂ may be about 15% to about 18% greater than the lower width w ₂₂ .

In step (f), the trench pattern 210 is first expanded in the horizontal direction. The trench pattern 210 may be expanded by wet etching the hard mask 200 at an etching rate of about 60 nm / min or less using an etchant mixture of NH ₄ F and HF. By the presence or absence of the trench pattern 210 and the width of the pattern, the etching liquid flows smoothly in the upper portion of the trench pattern 210 and the etching rate is relatively high, whereas the etching liquid is stagnant in the lower portion of the trench pattern 210 and the etching rate is relatively low. . In particular, the etched material trench pattern 210 may not be discharged smoothly. As a result, the sidewalls of the trench patterns 210 are formed to be inclined at the first pattern sidewall angle. The upper width of the first extended trench pattern 210 is w ₁₃ , the lower width is w ₂₃ , and the thickness of the hard mask 200 is th ₃ . The upper width w ₁₃ may be about 35% to about 38% of the initial thickness th ₁ . Meanwhile, the thickness th ₃ of the hard mask 200 may be reduced to about 77% to 80% of the initial thickness th ₁ .

In step (g), a second trench 112 is formed in the first conductivity type epi layer 105. The second trench 112 is formed by, for example, secondary dry etching the bottom of the first trench 111 in the vertical direction in the same manner as in step (e). The sidewalls of the second trench 112 may be formed to be inclined at the second trench sidewall angle. Here, the second trench sidewall angle may be greater than the first trench sidewall angle. By the second epitaxial layer etching, the first trenches 111 also extend in the horizontal direction. The upper width of the first trench 111 is w ₂₄ , the upper width of the second trench 112 is w ₃₄ and the lower width is w ₄₄ , which may be continuously etched and gradually widened in subsequent etching. The lower width of the first trench 111 is substantially larger than the upper width w ₃₄ of the second trench 112, thereby forming a first step (111s in FIG. 5). Here, the upper width w ₃₄ of the second trench 112 may be about 26% to about 29% greater than the lower width w ₄₄ , and the second depth d ₂ may be about 1.0 μm to about 2.0 μm. Meanwhile, when the second epitaxial layer is etched, the hard mask 200 is also etched, so that the thickness th ₄ of the hard mask 200 may be reduced to about 74% to 77% of the initial thickness th ₁ , and the trench pattern 210 may be reduced. The upper width of) is w ₁₄ and the lower width is w ₂₄ . Here, the upper width w ₁₄ may be about 31% to about 34% greater than the lower width w ₂₄ .

In step (h), the trench pattern 210 is second extended in the horizontal direction. For example, the trench pattern 210 may be expanded in the horizontal direction by wet etching the hard mask 200 in the same manner as in step (f). The sidewalls of the trench pattern 210 may be formed to be inclined at the second pattern sidewall angle. Here, the second pattern sidewall angle may be greater than the first pattern sidewall angle. The upper width of the second extended trench pattern 210 is w ₁₅ , the lower width is w ₂₅ , and the thickness of the hard mask 200 is th ₅ . The upper width w ₁₅ may be about 46% to about 49% of the initial thickness th ₁ . Meanwhile, the thickness th ₅ of the hard mask 200 may be reduced to about 57% to 60% of the initial thickness th ₁ .

In step (i), a third trench 113 is formed in the first conductivity type epi layer 105. The third trench 113 is formed by tertiary dry etching the bottom of the second trench 112 in the vertical direction, for example, in the same manner as in step (e). The sidewalls of the third trench 113 may be formed to be inclined at the angle of the third trench sidewalls. Here, the third trench sidewall angle may be greater than the second trench sidewall angle. By the third epitaxial layer etching, the first trenches 111 and the second trenches 112 also extend in the horizontal direction. The upper width of the first trench 111 is w ₂₆ , the upper width of the second trench 112 is w ₃₆ , the upper width of the third trench 113 is w ₄₆ and the lower width is w ₅₄ . The lower width of the second trench 112 is substantially greater than the upper width w ₄₆ of the third trench 113, thereby forming a second step (112s in FIG. 5). Here, the upper width w ₄₆ of the third trench 113 may be about 240% to about 270% greater than the lower width w ₅₆ , and the third depth d ₃ may be about 1.5 μm to about 3.0 μm. Meanwhile, when the third epitaxial layer is etched, the hard mask 200 is also etched so that the thickness th ₆ of the hard mask 200 may be reduced to about 53% to 57% of the initial thickness th ₁ .

In step (j), a second conductivity type junction region 120 is formed. The second conductivity type junction region 120 may be formed by ion implanting a second conductivity type impurity into the trench 110 using the hard mask 200 remaining after the third epitaxial layer etching as an ion implantation pattern. . The angle of the sidewalls of the trench 110 may vary depending on the depth, and the first and second steps may be formed, so that the second conductive junction region 120 may be formed on the sidewalls of the trench even without the inclined ion implantation. The second conductivity type junction region 120 is activated through heat treatment.

Thereafter, the insulating layer 140, the Schottky metal layer 150, the anode electrode 160, and the cathode electrode 180 are sequentially formed to complete the trench junction barrier Schottky diode.

5 is a cross-sectional view illustrating an ion region formed by vertical ion implantation and an ion region formed by tilt ion implantation.

Referring to FIG. 5, (a) is a second conductivity type junction region 120 formed by vertical ion implantation into the stepped trench 110, and (b) a second formed by oblique ion implantation into the stepped trench 110. The conductive junction region, and (c) each represent a second conductive junction region formed by gradient ion implantation into a general trench.

In (a) and (b), the stepped trench 110 may include the first trench 111, the second trench 112, and the third trench 113 formed in a self-aligning manner using one hard mask. Include. The first trench 111 is connected to the second trench 112, and the second trench 112 is connected to the third trench 113. The lower width of the first trench 111 is substantially larger than the upper width of the second trench 112, so that the first stairs 111s connect the first sidewall 111w and the second sidewall 112w. Meanwhile, the lower width of the second trench 112 is substantially larger than the upper width of the third trench 113, so that the second stairs 112s connect the second sidewall 112w and the third sidewall 113w. do.

The first bonding region 121 formed along the first sidewall 111w is formed of the second bonding region 123 formed along the second sidewall 112w at the first connection region 122 near the first stairs 111s. Connected. In the same way, the second bonding region 123 is connected with the third bonding region 125 at the second connecting region 124 near the second stairs 112s, and the third bonding region 125 is connected to the third bonding region 125. The fourth junction region 126 is connected near the bottom 113b of the trench 113. Here, the second conductivity type junction region 120 includes a first junction region 121, a second junction region 122, a third junction region 123, and a fourth junction region 126.

The first to third sidewalls 111w, 112w, and 113w may be inclined with respect to a straight line (hereinafter, referred to as a vertical line) substantially parallel to the depth direction of the trench 110. As a result, the first junction region 121 to the third junction region 123 may be formed along the first to third sidewalls 111w, 112w, and 113w by vertical ion implantation. Meanwhile, angles between the first to third sidewalls 111w, 112w, and 113w and the vertical line may be different from each other. The first angle between the vertical line and the first sidewall 111w may be smaller than the second angle between the vertical line and the third sidewall 113w. Therefore, the horizontal width of the junction region formed by the vertical ion implantation may increase with the depth of the trench 110. That is, as the first bonding region 121, the second bonding region 122, and the third bonding region 123 become deeper, the width in the horizontal direction increases. The lower portion of the first bonding region 121 and the upper portion of the second bonding region 123 are connected only in the first connection region 122 due to the first steps 111s. Similarly, the lower portion of the second junction region 123 and the upper portion of the third junction region 125 are connected only in the second connection region 122. Meanwhile, as the fourth junction region 126 deepens into the first conductive epitaxial layer 105, the width in the horizontal direction decreases.

In (b), the first junction region 121, the second junction region 122, and the third junction region 123 are formed along the sidewall also by vertical ion implantation, but the first junction region ( 121, horizontal widths of the second bonding region 122 and the third bonding region 123 may be increased. For example, as the horizontal width of the first stairs 111s and / or the second stairs 112s increases, the horizontal width of the first connecting regions 122 and / or the second connecting regions 124 decreases. Can go away or go away. This may affect the formation of the depletion layer and may result in the concentration of the electric field. When inclined ion implantation is performed in the stepped trench 110, the horizontal widths of the first junction region 121 ′ to the fourth junction region 126 ′ are vertically ion implanted to form the first junction regions 121 to th second. By increasing the horizontal width of the four junction regions 126, the occurrence of negative effects due to the decrease in the horizontal width of the first connection region 122 and / or the second connection region 124 may be suppressed or eliminated.

In (c), when the gradient ion implantation is applied, the second conductivity type junction region 120 ″ may also be formed on the sidewall of the general trench. Silicon carbide is known to have a maximum depth of 1 μm due to its rigid properties. Compared to the stepped trench 110, a relatively large amount of ions are implanted into the bottom 111b ″, but since the second junction region 126 ″ is formed at a relatively shallow position, the first junction region ( 126 '') and the depth at which the depletion layer is formed in the downward direction is also relatively shallow. Meanwhile, the first junction region 121 ″ formed along the sidewall 111w ″ has a relatively short vertical length, and thus forms a depletion layer thinly near the upper surface of the first conductive epitaxial layer 105.

The above description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

Claims (8)

Depositing a hard mask with an initial thickness on an upper surface of the first conductivity type epi layer;
Etching the hard mask to form a trench pattern;
Forming a first trench extending in a vertical direction from the top surface of the first conductivity type epi layer using the trench pattern and inclined at a first trench sidewall angle;
Firstly extending in the horizontal direction such that the trench pattern has a first pattern sidewall angle;
Forming a second trench extending in a vertical direction from the bottom of the first trench and inclined at a second trench sidewall angle using a first extended trench pattern; And
Forming a second conductivity type junction region in the sidewalls of the first trenches and in the sidewalls of the second trenches. The method according to claim 1,
The trench pattern is extended in the horizontal direction by wet etching,
The first trench and the second trench is a power semiconductor manufacturing method having a trench of a stepped structure extending in the vertical direction by dry etching. The method of claim 1, wherein after forming the second trench,
Secondly extending in a horizontal direction such that the first extended trench pattern has a second pattern sidewall angle; And
Forming a third trench extending in a vertical direction from the bottom of the second trench and inclined at a third trench sidewall angle using a second extended trench pattern,
Forming the second conductivity type junction region on the sidewall of the first trench and the sidewall of the second trench,
And forming a second conductive junction region on the sidewall of the third trench. The power semiconductor fabrication of claim 3, wherein the lower width of the first trench is greater than the upper width of the second trench, and the lower width of the second trench is greater than the upper width of the third trench. Way. A first conductivity type substrate formed of silicon carbide containing a first conductivity type impurity;
A first conductive epitaxial layer epitaxially grown on the first conductive substrate;
A trench having a stepped structure extending in a vertical direction from an upper surface of the first conductivity type epi layer toward the inside;
A second conductive junction region formed in the first conductive epitaxial layer along the bottom and sidewalls of the trench;
A Schottky metal layer filling the trench and formed on an upper surface of the first conductivity type epi layer;
An anode formed on an upper surface of the schottky metal layer; And
Including a cathode electrode formed on the lower surface of the first conductivity type substrate,
The trench,
A first trench inclined at a first trench sidewall angle, and
A second trench extending in a vertical direction from the bottom of the first trench and inclined at a second trench sidewall angle,
The second trench sidewall angle is greater than the first trench sidewall angle,
A lower width of the first trench is greater than an upper width of the second trench, and a step is formed in a connection region between the first trench and the second trench,
A width of the second conductivity type junction region formed along the sidewalls of the first trench and the sidewall of the second trench increases vertically downward,
And a stepped trench in which the width of the second conductivity type junction region in the connection region decreases. delete delete The method according to claim 5,
Further comprising a third trench extending in a vertical direction from the bottom of the second trench and inclined at a third trench sidewall angle,
The third trench sidewall angle is greater than the second trench sidewall angle,
The lower semiconductor width of the second trench is greater than the upper width of the third trench has a stepped trench having a stepped trench formed in the connection region of the second trench and the third trench.

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