KR102047962B1 - Mehod and apparatus for secondary synchronization in internet of things - Google Patents

Abstract

A secondary synchronization method and apparatus are disclosed in the Internet of Things. The receiving device may apply the channel estimation to the time-domain samples of the secondary synchronization signal to extract the frequency-domain samples. The receiving apparatus estimates the physical cell ID (PCI) and the 80 ms frame timing (FT) by decorrelating between the frequency domain standardized signal of the secondary synchronization signal and the frequency domain sample. Can be.

Description

METHOD AND APPARATUS FOR SECONDARY SYNCHRONIZATION IN INTERNET OF THINGS}

The present invention relates to a secondary synchronization method and apparatus in the Internet of Things.

Based on an orthogonal frequency division multiplexing (OFDM) transmission scheme, there is a wireless communication system that provides an IoT service over a large area at low power and cost. The wireless communication system supports various modes such as standalone operation mode, in-band operation mode, and guard band operation mode for versatility.

The standalone operation mode is a mode for operating a signal for providing an IoT service in a frequency band used by a global system for mobile communication (GSM). The in-band operation mode is a mode for operating a signal for providing an IoT service to at least one of available resource blocks (RBs) in a frequency band used in a conventional Long Term Evolution (LTE) system. The guardband operation mode is a mode in which a signal for providing an IoT service is operated on at least one of available (unavailable) RBs in a frequency band used in an existing LT system.

Such a wireless communication system may perform secondary synchronization on the last subframe of an even-numbered frame to obtain a physical cell ID (PCI) and an 80 ms frame timing (FT) regardless of the three operation modes described above. Transmit a signal (Secondary Synchronization Signal).

In more detail, one frame includes 10 subframes, and a narrowband secondary synchronization signal (NSSS) is transmitted in the last subframe of the even-numbered frame. In addition, a narrowband physical broadcast channel (NPBCH) is transmitted in the first subframe of every frame. NPBCH repeatedly transmits the same broadcasting information in units of 80 ms. The NSSS contains one of 504 PCI information, and this information does not change when a serving cell is determined. In order to acquire information on the start frame of the NPBCH repeated every 80 ms (that is, to obtain an 80 ms FT), the NSSS includes different 80 ms FT information in units of frames to which four NSSSs are allocated. In other words, the FT0 sequence for the 80ms FT is contained in the NSSS in the first frame of four frames, and the FT1 sequence is transmitted in the NSSS in the second frame. In the third frame, the sequence of FT2 is contained in NSSS and transmitted. Finally, in the fourth frame, the sequence of FT3 is contained in NSSS and transmitted. As such, by transmitting different FT sequences, start frame information of an 80 ms FT can be obtained.

In order to carry the above-described PCI and 80ms FT information, the NSSS signal in the frequency domain is composed of two different sequences for PCI and the FT sequence for 80ms FT in the form of mathematical multiplication. In order to receive the NSSS configured as described above and to obtain desired information, a very complicated decorrelation process is required. Therefore, the battery consumption of the receiving device increases. And complex decorrelation processes may be inadequate for wireless communication systems aimed at providing IoT services over large areas.

An object of the present invention is to provide a secondary synchronization method and apparatus capable of effectively obtaining a PCI and 80ms FT in the Internet of Things.

According to an embodiment of the present invention, a method for acquiring synchronization based on a secondary synchronization signal received from a transmission device by a receiving device in the IoT is provided. The method includes extracting a frequency domain sample by applying channel estimation to a time domain sample of the secondary synchronization signal, and performing decorrelating between the frequency domain standard signal of the secondary synchronization signal and the frequency domain sample. The method may include estimating a physical cell ID (PCI) and a frame timing (FT).

The estimating may include performing correlation between a Fourier Series (FS) sequence included in the frequency domain standard signal and the frequency domain sample to calculate a first value, and ZC (Zadoff) included in the frequency domain standard signal. Chu) calculating a second value by performing inverse correlation between the sequence and the first value, and performing a cross correlation between the scrambling sequence included in the frequency domain standard signal and the second value to calculate a third value. And estimating the PCI and the FT using the first value, the second value, and the third value.

The estimating may further include calculating a fourth value by performing CS (Cyclic Shift) combining on the third value.

The estimating of the PCI and the FT may include estimating the PCI and the FT using the first to fourth values.

The first value may be calculated using only sign conversion instead of a multiplication operation, and the third value may be calculated only through sign conversion instead of a multiplication operation.

After the calculating of the first value, the calculating of the second value, the calculating of the third value, and the calculating of the fourth value are repeated by a predetermined cumulative number of times, the PCI And estimating the FT may be performed.

The estimating may include estimating a first value by performing cross-correlation between a first FS sequence and a frequency domain sample of a Fourier Series (FS) sequence included in the frequency domain standard signal, and a second of the FS sequences. Estimating a second value by performing cross-correlation between a sequence and the frequency domain sample, estimating a third value by performing cross-correlation between a third sequence and the frequency domain sample of the FS sequence, and during the FS sequence Estimating a fourth value by performing cross correlation between a fourth sequence and the frequency domain sample, and estimating the PCI and the FT by comparing the first to fourth values.

The extracting may include removing a cyclic prefix from the time domain sample, down sampling the sample from which the CP has been removed, and performing a fast fourier transform (FFT) on the down sampled sample. It may include.

The FT may be an 80 ms FT.

According to another embodiment of the present invention, a method for acquiring synchronization based on a secondary synchronization signal received from a base station by a terminal in the IoT is provided. The method includes extracting a frequency domain sample from a time domain sample of the secondary synchronization signal, and performing physical correlation between the sequence included in the frequency domain standard signal of the secondary synchronization signal and the frequency domain sample. Estimating (PCI, Physical Cell ID) and 80ms frame timing (FT).

The estimating may include performing correlation between a Fourier Series (FS) sequence included in the frequency domain standard signal and the frequency domain sample to calculate a first value, and ZC (Zadoff) included in the frequency domain standard signal. Chu) calculating a second value by performing inverse correlation between the sequence and the first value, and performing a cross correlation between the scrambling sequence included in the frequency domain standard signal and the second value to calculate a third value. And calculating a fourth value by performing CS (Cyclic Shift) combining with the third value, and estimating the PCI and the FT using the first to fourth values. .

After the calculating of the first value, the calculating of the second value, the calculating of the third value, and the calculating of the fourth value are repeated by a predetermined cumulative number of times, the PCI And estimating the FT may be performed.

The first value may be calculated through addition calculation instead of a multiplication operation, and the third value may be calculated through addition calculation instead of a multiplication operation.

According to another embodiment of the present invention, a receiving apparatus is provided. The reception device may include an analog-to-digital converter configured to sample the secondary synchronization signal received from the transmitter into a digital signal to generate a first sampling signal, a filter to filter the first sampling signal, and the filtered first signal. A channel estimation is performed on the sampling signal to extract a frequency domain sample, and a decorating between the frequency domain standard signal of the secondary synchronization signal and the frequency domain sample causes a physical cell ID (PCI) and an 80 ms frame. It may include a synchronous estimator to estimate the timing (FT, Frame Timing).

The synchronous estimator calculates a first value by performing inverse correlation between the Fourier Series (FS) sequence included in the frequency domain standard signal and the frequency domain sample, and calculates a ZC (Zadoff Chu) included in the frequency domain standard signal. A second value is calculated by performing a cross correlation between a sequence and the first value, and a third value is calculated by performing a cross correlation between the scrambling sequence included in the frequency domain standard signal and the second value to calculate a third value. The fourth value may be calculated by performing CS (Cyclic Shift) combining, and the PCI and the FT may be estimated using the first to fourth values.

The synchronous estimator may estimate the PCI and the FT after repeatedly calculating the first to fourth values by a predetermined cumulative number of times.

The first value may be calculated through addition calculation instead of a multiplication operation, and the third value may be calculated through addition calculation instead of a multiplication operation.

The synchronous estimator includes: a first estimator configured to estimate a first value by performing cross-correlation between a first FS sequence and a frequency domain sample of an FS sequence included in the frequency domain standard signal, and among the FS sequences A second estimator for estimating a second value by performing inverse correlation between a second sequence and the frequency domain sample, and a second estimator performing inverse correlation between a third sequence of the FS sequence and the frequency domain sample to estimate a third value A third estimator, a fourth estimator configured to estimate a fourth value by performing inverse correlation between a fourth sequence of the FS sequence and the frequency domain sample, and comparing the first to the fourth values to compare the PCI and the It may include a selector for estimating the FT.

The synchronous estimator removes the cyclic prefix (CP) from the first sampling signal, downsamples the sample from which the CP is removed, and performs the down-sampled sample by performing a fast fourier transform (FFT) to extract the frequency domain sample. can do.

According to an embodiment of the present invention, PCI and 80ms FT can be obtained with fewer operations by reducing complex operations. Through this, the embodiment of the present invention can effectively implement the receiving device of the IoT at low power.

1 is a flowchart illustrating a method of generating an NSSS signal in a standalone operation mode according to an embodiment of the present invention.
2 is a flowchart illustrating a method of generating an NSSS signal in an in-band operation mode according to an embodiment of the present invention.
3 is a block diagram illustrating a receiving apparatus according to an exemplary embodiment of the present invention.
4 is a block diagram illustrating a synchronous estimator according to an embodiment of the present invention.
5 is a block diagram illustrating a first processing unit according to an exemplary embodiment of the present invention.
6 is a view showing a process of FFT according to an embodiment of the present invention.
7 is a block diagram illustrating a second processing unit according to an embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, the receiving device is a terminal, a mobile terminal (MT), a mobile station (MS), an advanced mobile station (AMS), a high reliability mobile station (HR) -MS), subscriber station (SS), portable subscriber station (PSS), access terminal (AT), user equipment (UE), etc. It may include all or part of the functionality of the MT, AMS, HR-MS, SS, PSS, AT, UE, and the like.

In addition, the transmitting apparatus includes a base station (BS), an advanced base station (ABS), a high reliability base station (HR-BS), a node B (node B), and an advanced node B (evolved). node B, eNodeB), access point (AP), radio access station (RAS), base transceiver station (base transceiver station, BTS), MMR (mobile multihop relay) -BS, base station It may also refer to a relay station (RS), a high reliability relay station (HR-RS) that performs a role of a base station, and may also refer to a BS, ABS, Node B, eNodeB, AP, RAS, BTS, MMR-, and the like. It may also include all or part of the functions of the BS, RS, HR-RS and the like.

First, generation of a narrowband secondary synchronization signal (NSSS) frequency domain signal according to an embodiment of the present invention will be described.

)는 Cyclically-extended Length-132 ZC (Zadoff Chu) 시퀀스(

)와 Cyclically-extended Length-132 binary Hadamard 시퀀스(

), 그리고 FS (Fourier Series) 시퀀스(

)의 결합으로 구성될 수 있다. 즉, NSSS 주파수영역 신호는 하기의 수학식 1과 같이 규정될 수 있다. NSSS frequency domain signal (

) Is a Cyclically-extended Length-132 ZC (Zadoff Chu) sequence (

) And the Cyclically-extended Length-132 binary Hadamard sequence (

), And the FS (Fourier Series) sequence (

Can be composed of a combination of That is, the NSSS frequency domain signal may be defined as in Equation 1 below.

이다. 또한, ZC 시퀀스(

)는 하기의 수학식 2와 같이 규정될 수 있다. Here, the cyclic shift index p is applied to the NSSS signal located in the last subframe of the (8k + 2p) th frame.

to be. In addition, the ZC sequence (

) May be defined as in Equation 2 below.

)는 하기의 수학식 3과 같이 규정될 수 있다. And a scrambling sequence (

) May be defined as in Equation 3 below.

이다. 이에 따라,

는 아래의 표 1과 같이 된다. In Equation 3,

to be. Accordingly,

Is shown in Table 1 below.

)는 하기의 수학식 4와 같이 규정될 수 있다. And the FS sequence (

) May be defined as in Equation 4 below.

이다. 이에 따라,

는 아래의 표 2와 같이 된다. In Equation 4,

to be. Accordingly,

Becomes as shown in Table 2 below.

Meanwhile, a mapping function for mapping a physical cell ID (PCI) to indices u and p may be defined as shown in Equation 5 below.

이 된다. Assuming that the receiving device (i.e., terminal) has acquired a particular u and q, the corresponding PCI

Becomes

)는 상기 수학식 1과 같이 규정된다. An NSSS signal generation method in the standalone operation mode will be described with reference to FIG. 1. Here, NSSS frequency domain signal (

) Is defined as in Equation 1 above.

1 is a flowchart illustrating a method of generating an NSSS signal in a standalone operation mode according to an embodiment of the present invention.

First, according to the PCI and the 80ms FT employed by a specific transmission device (i.e., base station), the transmission device generates an NSSS frequency domain signal defined in Equation 1 above.

로 분할한다. 송신 장치는 분할한 m별 12개 엘리먼트에 대해서 서브캐리어 위치 {k,n}와 심볼 m에 생성된 시퀀스 엘리먼트를 할당한 후 제로 페딩(Zero padding)을 수행하여 총 128개 샘플을 생성한다. 즉, 송신 장치는 m 마다 12개의 부반송파 위치(

)에 m번째 시퀀스 엘리먼트를 할당하고 116개 제로 페딩(Zero padding)을 수행한다. 좀더 상세히 설명하면, 물리적 부반송파 위치는 k=-64,-63,-62,…,-1,0,1,…,62,63이고, 논리적 부반송파 위치는 n=0,1,…,10이며, 상기 시퀀스 엘리먼트가 할당되는 부반송파 위치는 {-6,0}, {-5,1}, {-4,2},…,{-1,5},{0,6},…,{5,11}이며, 나머지 물리적 부반송파 위치 k(=-64,-63,…,-7,6,7,…,63)에는 제로가 페딩(padding)된다. 이러한 과정은 심볼 m마다 반복적으로 수행된다. Next, the transmitting apparatus performs a subcarrier mapping process. The transmitting apparatus divides 132 pieces into 11 pieces, each of 12 pieces in order of small element index to large index. That is, the transmitting device sends 132 elements

Split into The transmitting apparatus allocates the sequence elements generated at the subcarrier position {k, n} and the symbol m to the 12 elements for each m, and then performs zero padding to generate a total of 128 samples. In other words, the transmitting apparatus has 12 subcarrier positions per m (

) Assigns the m th sequence element to 116 zero padding. In more detail, the physical subcarrier positions are k = -64, -63, -62,... , -1,0,1,… And 62,63, and the logical subcarrier positions are n = 0, 1,... , 10, and the subcarrier positions to which the sequence element is assigned are {-6,0}, {-5,1}, {-4,2},... , {-1,5}, {0,6},... , {5,11} and zero padding to the remaining physical subcarrier positions k (= -64, -63, ..., -7,6,7, ..., 63). This process is repeatedly performed for every symbol m.

The transmitting device performs subcarrier indexing. That is, the transmitting apparatus performs cyclic shifting by 64. Here, the subcarrier indexing process includes the positions of the upper subcarrier group (the number of subcarriers corresponding to the BW of the upper half of the LTE system BW) and the lower subcarrier group (the number of subcarriers corresponding to the lower half of the BW of the LTE system BW). It can be done in exchange.

이면 CP 길이는 10이고 나머지는 모두 CP 길이가 9일 수 있다. The transmitter performs a 128-point Inverse Fast Fourier Transform (IFFT) and then inserts a Cyclic Prefix (CP). When inserting CP

In this case, the CP length is 10 and the rest of the CP lengths may all be 9.

For the NSSS signal generated as shown in FIG. 1, when the receiver (terminal) samples the ADC (Analog to Digital Converter) at 1.92 MHz, the number of samples of the NSSS time-domain signal is 1508 (= 138 + 137 * 10). Can be.

)는 상기 수학식 1과 같이 규정된다. The NSSS signal generation method in the in-band operation mode will be described with reference to FIG. 2. Here, NSSS frequency domain signal (

) Is defined as in Equation 1 above.

2 is a flowchart illustrating a method of generating an NSSS signal in an in-band operation mode according to an embodiment of the present invention.

First, in accordance with PCI and 80 ms FT employed by a specific transmission device (i.e., base station), the transmission device generates an NSSS frequency domain signal defined in Equation 1 above.

)에 m번째 시퀀스 엘리먼트를 할당하고 116개 제로 페딩(zero padding)을 수행한다. 그리고, 송신 장치는 레거시 LTE 시스템에 영향을 주지 않기 위해 레거시(Legacy) CRS(Cell-specific Reference Signal)가 할당되는 서브캐리어 위치에서는 펑처링(Puncturing)을 수행한다. Next, the transmitting apparatus performs a subcarrier mapping process. The transmitting apparatus allocates generated sequence elements to corresponding subcarrier positions {k, n} of a specific physical resource block (Physical RB) and symbol m in legacy LTE in-band, and then zero-paddings. padding) to generate a total of 128 samples. In other words, the transmitting apparatus includes 12 subcarrier positions (m each).

) Is assigned an m th sequence element and 116 zero padding is performed. The transmitter performs puncturing at a subcarrier location to which a legacy CRS (Cell-specific Reference Signal) is allocated so as not to affect the legacy LTE system.

The transmitting device performs subcarrier indexing according to bandwidth (BW) of the legacy LTE system. Here, the subcarrier indexing process includes the positions of the upper subcarrier group (the number of subcarriers corresponding to the BW of the upper half of the LTE system BW) and the lower subcarrier group (the number of subcarriers corresponding to the lower half of the BW of the LTE system BW). It can be done in exchange.

The transmitter performs a 128-point Inverse Fast Fourier Transform (IFFT) and then inserts a Cyclic Prefix (CP).

For the NSSS signal generated as shown in FIG. 2, when the receiver (terminal) samples the ADC (Analog to Digital Converter) at 1.92 MHz, the number of samples of the NSSS time domain signal is 1508 (= 138+ 137 * 10).

Meanwhile, the NSSS generation method in the guardband operation mode is the same as the inband operation mode except that the physical RB position is in the guardband and CRS puncturing is not required.

Hereinafter, a method and apparatus for obtaining PCI and 80ms FT based on the NSSS signal described above will be described.

3 is a block diagram illustrating a receiving apparatus 1000 according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the reception apparatus 1000 according to an exemplary embodiment of the present invention includes an RF processing unit 100, an analog-to-digital converter (ADC) 200, a filter unit 300, A synchronization estimator 400 and a physical layer controller 500 are included.

The RF processing unit 100 performs RF signal processing on the NSSS signal received from the transmitter. RF signal processing may include the ability to amplify the signal while removing noise, automatic frequency control (AFC), and bandpass filtering of the RB bands carrying the NSSS signal.

ADC 200 samples the analog signal into a digital signal at a predetermined sampling rate. Since the bandwidth occupied by the NB-IoT transmission signal is mostly 180 kHz, the sampling rate may be 1.92 MHz by Nyquist sampling theorem.

The filter unit 300 performs baseband filtering on the signal sampled at 1.92 MHz from the ADC 200. Since the bandwidth occupied by the NB-IoT transmission signal is 180 kHz, the filter unit 300 may be implemented as a low pass filter (LPF) having a 180 kHz bandwidth. That is, the filter unit 300 may have a 180 kHZ bandwidth since the filter unit 300 may filter only the physical RB in which the NSSS signal is loaded regardless of the system bandwidth (BW) of the transmitting apparatus (for example, the base station).

The synchronous estimator 400 receives a 1.92 MHz sampling signal filtered by the physical RB containing the NSSS signal from the filter unit 300, and estimates the PCI and 80 ms FT using the same. That is, the synchronization estimator 400 estimates the PCI and the 80 ms FT using the characteristics of the NSSS frequency domain standard signal transmitted every even frame.

The physical layer controller 500 controls the RF processing unit 100, the ADC 200, the filter unit 300, and the synchronization estimator 400. That is, the physical layer controller 500 controls the overall operation of the physical layer L1. In the following description, the physical layer controller 500 may be used interchangeably with the term 'L1 control'.

4 is a block diagram illustrating a sync estimator 400 according to an embodiment of the present invention.

As shown in FIG. 4, the synchronization estimator 400 according to an exemplary embodiment of the present invention includes a first processor 410 and a second processor 420. The synchronization estimator 400 is executed when the enable signal (i_start = ON) is received from the physical layer controller 500. The first processor 410 may be mixed with the term 'NSSS Step1', and the second processor 420 may be mixed with the term 'NSSS Step2'.

The first processor 410 performs channel estimation every 10 ms at a fixed sample timing offset (STO) from the time when the enable signal (i_start = ON) is received from the physical layer controller 500. The first processor 410 receives the samples corresponding to the total number of samples of the NSSS time domain standard signal every 10 ms from the fixed STO from the time when the enable signal is received from the physical layer controller 500, and recovers the channel. By performing a channel recovering process, samples corresponding to the NPSS frequency domain standard signal are extracted. In this case, the fixed STO means a starting point of a narrowband primary synchronization signal (NPSS) subframe that is defined when the receiving apparatus 1000 is implemented. Here, the NSSS detection window size of the first processor 410 may be 20 ms.

The second processor 420 performs correlation and accumulation (i_NumAcc) between the samples extracted by the first processor 410 and the NSSS frequency domain standard signal to obtain PCI and 80ms FT. The second processor 420 transfers the acquired PCI (o_PCI) and 80 ms FT (o_FT) to the physical layer controller 500 and is disabled (o_Done = ON).

Table 3 shows the input signal for the functional interface of the sync estimator 400.

Table 4 shows the output signal for the functional interface of the sync estimator 400.

5 is a block diagram illustrating a first processing unit 410 according to an embodiment of the present invention. The first processor 410 performs channel compensation by converting time-domain samples passed through an NFC (Narrowband Primary Synchronization Signal) estimated and passed through AFC (Automatic Frequency Control) to the frequency domain.

As illustrated in FIG. 5, the first processor 410 according to an exemplary embodiment of the present invention may include a buffer 411, a cyclic prefix remover 412, a down-sampler 413, And Fast Fourier Transform (FFT) 414. The first processor 410 is executed when i_Start_s1 = ON is received from the synchronization estimator 400.

The buffer 411 buffers 1508 samples corresponding to the NPSS time domain standard signal every 10 ms in the fixed STO from the time when i_Start_s1 = ON from the sync estimator 400. The buffer 411 buffers 1508 samples corresponding to the NSSS time domain standard signal every 10 ms in the fixed STO from the time when i_Start_s1 = ON from the sync estimator 400. Here, in FIG. 5, a signal buffered in the buffer 411, that is, a signal for 1508 samples corresponding to the NSSS time domain standard signal, is represented by buf_rx_nsss_s1.

CP remover 412 removes a cyclic prefix (CP). CP remover 412 removes the first 9 samples for every 137 samples for the first 137 * 4 samples for the 1508 samples stored in buffer 411, and the first 10 for the next 138 samples. 3 samples are removed, and for the next 137 * 6 samples, the first 9 samples are removed every 137 samples.

The down sampler 413 downsamples the sample from which the CP has been removed in the CP remover 412. That is, the down sampler 413 down-samples 8 times, and repeats the process of equally catching one sample every 8 samples for the CP-removed 1408 samples.

FFT 414 performs a Fast Fourier Transform (FFT) on the down sampled sample. 6 is a diagram illustrating a process of FFT 414 according to an embodiment of the present invention. Referring to FIG. 6, the FFT 414 performs a 16-point FFT transform every 16 samples on 176 samples that are 8 times downsampled, and then subcarrier indexing and guardband removing. And the extraction process is repeatedly performed to output 12 * 11 = 132 samples (buf_rx240_nsss [.]) Which are samples corresponding to the NPSS frequency domain standard signal. On the other hand, as shown in Figure 6, the subcarrier indexing process is a reverse process of the subcarrier indexing in the transmission apparatus, the guardband removal process is a process of removing the upper two subcarriers and the lower two subcarriers.

The FFT 414 transfers the 132x2 samples (buf_rx240_nsss [.]) Extracted during the 20ms time window to the second processor (SSS Step2) 420 in a 20ms period. The FFT 414 transmits a control signal o_Done_s1 = ON to the second processor (NSSS Step2) 420 at the end of every cycle.

Table 5 shows an input signal for a functional interface of the first processor 410.

Table 6 shows an output signal for the functional interface of the first processor 410.

7 is a block diagram illustrating a second processing unit 420 according to an embodiment of the present invention. The second processor 420 repeatedly performs four hypothesis processes on samples corresponding to the NPSS frequency domain standard signal input from the first processor 410 two times in units of 132 samples. do.

As shown in FIG. 7, the second processor 420 according to the embodiment of the present invention may include a first estimator 421, a second estimator 422, a third estimator 423, and a fourth estimator ( 424, Cyclic Shift (CS) Combiner (425), Memory (426), Buffer (427), and Selector (428). The first estimator 421 may be mixed with the term 'PCI_FT_H0', the second estimator 422 may be mixed with the term 'PCI_FT_H1', and the third estimator 423 may be mixed with the term 'PCI_FT_H2'. The fourth estimator 424 may be mixed with the term 'PCI_FT_H3'. The second processor 420 is executed when o_Done_s1 = ON is received from the first processor 410.

)에 대한 역상관(Decorrelating), 상기 수학식 2에 나타낸 ZC 시퀀스에 대한 역상관(Decorrelating), 그리고 상기 수학식 3에 나타낸 스크램블 시퀀스(Scramble sequence)에 대한 역스크램블(Descrambling)을 수행한다. The first estimator 421 stores a zeroth sequence of the FS sequence shown in Equation 4 above.

Decorrelating for), decorrelating for the ZC sequence shown in Equation 2, and descramble for the scramble sequence shown in Equation 3 are performed.

)에 대한 역상관(Decorrelating), 상기 수학식 2에 나타낸 ZC 시퀀스에 대한 역상관(Decorrelating), 그리고 상기 수학식 3에 나타낸 스크램블 시퀀스(Scramble sequence)에 대한 역스크램블(Descrambling)을 수행한다. The second estimator 422 performs a first sequence of the FS sequences shown in Equation (4).

Decorrelating for), decorrelating for the ZC sequence shown in Equation 2, and descramble for the scramble sequence shown in Equation 3 are performed.

)에 대한 역상관(Decorrelating), 상기 수학식 2에 나타낸 ZC 시퀀스에 대한 역상관(Decorrelating), 그리고 상기 수학식 3에 나타낸 스크램블 시퀀스(Scramble sequence)에 대한 역스크램블(Descarambling)을 수행한다.The third estimator 423 performs a third sequence of the FS sequences shown in Equation (4).

Decorrelating for), decorrelating for the ZC sequence shown in Equation 2, and descramble for the scramble sequence shown in Equation 3 are performed.

)에 대한 역상관(Decorrelating), 상기 수학식 2에 나타낸 ZC 시퀀스에 대한 역상관(Decorrelating), 그리고 상기 수학식 3에 나타낸 스크램블 시퀀스(Scramble sequence)에 대한 역스크램블(Descrambling)을 수행한다. The fourth estimating unit 424 performs a fourth sequence of the FS sequence shown in Equation 4 above.

Decorrelating for), decorrelating for the ZC sequence shown in Equation 2, and descramble for the scramble sequence shown in Equation 3 are performed.

The CS combiner 425 performs a cyclic shift (CS) combining on the inverse scrambled values output from each of the first to fourth estimators 421 to 424.

The memory 426 stores the output values output from the CS combiner 415 (that is, the values obtained by combining CS for each of the first to fourth estimators 421 to 424) from the synchronization estimator 400 (i_NumAcc). Accumulate as much as) and save each.

The selector 428 compares the stored values for each of the first to fourth estimators 421 to 424 received from the memory 425 to finally determine the PCI and the 80 ms FT. When the selector 427 finally determines the PCI and 80ms FT, it forwards o_Done_s2 = ON to the synchronous estimator 400.

On the other hand, the second processor 420 is inversely correlated to the FS sequence of Equation 4 for each of the first to fourth estimators 421 to 424 before the cumulative number i_NumAcc received from the synchronization estimator 400. Inverse correlation of the ZC sequence of Equation 2, inverse scramble of the scramble sequence of Equation 3, and CS combining of the CS combiner 425 are performed. When the cumulative number i_NumAcc arrives, the second processor 420 finally detects the PCI and the 80ms FT through the selector 428.

As shown in FIG. 7, the first estimator 421 according to an embodiment of the present invention includes a de-correlator 4211, a de-correlator 4212, and a descrambler De- scrambler) 4213. As shown in FIG. 7, since the second to fourth estimators 422, 423, and 424 have the same components as the first estimator 421, the first estimator 421 is used for convenience of description. Explain.

)에 대해 하기의 수학식 6과 같이 FS 시퀀스 역상관(Decorrelating)을 수행한다. The decorrelator 4211 may include a sample corresponding to an NSSS frequency domain standard signal input from the first processor 410.

FS sequence decorrelating is performed as shown in Equation 6 below.

는 상기 수학식 4와 상기 표 2와 같다. 상기 표 2에 나낸 바와 같이, 샘플 값들이

이 거나

이므로, 곱하기 연산 대신에 부호 변환(Sign Conversion)만을 이용하면, 상기 수학식 6은 덧셈(addition) 만으로 계산될 수 있다. 한편, 역상관기(4211)은 FS 시퀀스 중 0번째 시퀀스(

)에 대한 역상관을 수행하므로, 상기 수학식 6에서

는

로 대체된다. In Equation 6,

Is shown in Equation 4 and Table 2. As shown in Table 2 above, the sample values

This or

Therefore, if only Sign Conversion is used instead of the multiplication operation, Equation 6 may be calculated by addition only. On the other hand, the decorrelator 4211 has a zeroth sequence of the FS sequence (

Since the decorrelation of) is performed,

Is

Is replaced by.

에 대한 역상관(Decorrelating)을 수행한다. 이러한 역상관은 하기의 수학식 7과 같이 수행된다. The decorrelator 4212 is a ZC sequence of Equation 2

Perform decorrelating on. This decorrelation is performed as in Equation 7 below.

와 상기 수학식 6의

,

을 이용하여, 역상관을 수행한다. As shown in Equation 7, the decorrelator 4212 is a ZC sequence of Equation 2.

And of Equation 6

,

Using, we perform decorrelation.

에 대한 역상관(Decorrelating)을 수행한다. 이러한 역상관은 하기의 수학식 8과 같이 수행된다. The descrambler 4213 is a scrambling sequence of Equation 3 above.

Perform decorrelating on. This decorrelation is performed as in Equation 8 below.

와 상기 수학식 7의

및

을 이용하여, 역상관을 수행한다. 상기 표 1에 나타낸 바와 같이 스크램블링 시퀀스(Scrambling sequence)의 엘리먼트가 바이너리(binary)이므로, 곱하기 연산 대신에 부호 변환(Sign Conversion)만을 이용하면, 상기 수학식 8은 덧셈(addition) 만으로 계산될 수 있다. As shown in Equation 8, the descrambler 4214 is a ZC sequence of Equation 3

And of Equation 7

And

Using, we perform decorrelation. As shown in Table 1, since the elements of the scrambling sequence are binary, if only Sign Conversion is used instead of the multiplication operation, Equation 8 may be calculated by addition only. .

The CS combiner 425 performs CS combining as shown in Equation 9 below.

는 감쇄 계수(decay factor)를 나타내고, A는 동기 추정기(400)의 윈도우 사이즈(window size)로서 20ms에 해당한다. 그리고

이다. In Equation 9,

Denotes a decay factor, and A represents a window size of the synchronization estimator 400, which corresponds to 20 ms. And

to be.

The selector 428 obtains specific u, q, and p when having the highest correlation value among the decision variables derived in Equation 9 above. Here, PCI can be calculated from ( u- 3) + q * 126 from u and q. And, 80ms FT can be obtained from the information on whether belongs to the first 132 samples or later 132 samples through p.

Table 7 shows an input signal for a functional interface of the second processor 420.

Table 8 shows an output signal for the functional interface of the second processor 420.

According to an embodiment of the present invention, since a complex calculation process is not required in the decorrelating process for one of two different sequences transmitted from a transmitter for PCI acquisition, a low power receiver may be implemented. In addition, according to an embodiment of the present invention, since a complex operation is not required in the decorrelation process of the FT sequence transmitted from the transmitting apparatus to obtain 80 ms, a low power receiver may be implemented. And through this, an optimized receiving apparatus can be implemented.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (19)

A method for acquiring synchronization based on a secondary synchronization signal received from a transmitting device by a receiving device in the IoT,
Extracting frequency-domain samples by applying channel estimation to time-domain samples of the secondary synchronization signal, and
Estimating physical cell ID (PCI) and frame timing (FT) by decorrelating between the frequency domain standardized signal of the secondary synchronization signal and the frequency domain sample; ,
The frequency domain standard signal includes a Fourier Series (FS) sequence including information on the FT, a Zadoff Chu (ZC) sequence including information about the PCI, and a scrambling sequence including information about the PCI. How to include. The method of claim 1,
The estimating step,
Calculating a first value by performing inverse correlation between the Fourier Series sequence and the frequency domain sample;
Calculating a second value by performing cross correlation between the ZCoff sequence and the first value;
Calculating a third value by performing cross-correlation between the scrambling sequence and the second value, and
Estimating the PCI and the FT using the first value, the second value, and the third value. The method of claim 2,
The estimating may further include calculating a fourth value by performing a Cyclic Shift (CS) combining on the third value. The method of claim 3,
Estimating the PCI and the FT includes estimating the PCI and the FT using the first to fourth values. The method of claim 2,
The first value is calculated through Sign Conversion instead of a multiplication operation,
And the third value is calculated by only sign conversion instead of a multiplication operation. The method of claim 3,
After the calculating of the first value, the calculating of the second value, the calculating of the third value, and the calculating of the fourth value are repeated by a predetermined cumulative number of times, the PCI And estimating the FT is performed. The method of claim 1,
The estimating step,
Estimating a first value by performing cross-correlation between a first FS sequence and the frequency domain samples in the Fourier Series sequence;
Estimating a second value by performing cross correlation between a second sequence of the FS sequences and the frequency domain samples;
Estimating a third value by performing inverse correlation between a third sequence of the FS sequence and the frequency domain sample;
Estimating a fourth value by performing inverse correlation between a fourth sequence of the FS sequence and the frequency domain sample, and
Estimating the PCI and the FT by comparing the first to fourth values. The method of claim 1,
The extracting step,
Removing a cyclic prefix from the time-domain sample;
Downsampling the sample from which the CP has been removed, and
And performing a fast fourier transform (FFT) on the down sampled sample.
The method of claim 1,
The FT is an 80 ms FT. A method for acquiring synchronization on the basis of a secondary synchronization signal received from a base station in an IoT,
Extracting a frequency domain sample from the time domain sample of the secondary synchronization signal, and
Estimating physical cell ID (PCI) and 80 ms frame timing (FT) through inverse correlation between a sequence included in the frequency domain standard signal of the secondary synchronization signal and the frequency domain sample. Include,
The frequency domain standard signal includes a Fourier Series (FS) sequence including information on the FT, a Zadoff Chu (ZC) sequence including information about the PCI, and a scrambling sequence including information about the PCI. How to include. The method of claim 10,
The estimating step,
Calculating a first value by performing inverse correlation between the Fourier Series sequence and the frequency domain sample;
Calculating a second value by performing cross correlation between the ZCoff sequence and the first value;
Calculating a third value by performing cross-correlation between the scrambling sequence and the second value,
Calculating a fourth value by performing CS (Cyclic Shift) combining the third value; and
Estimating the PCI and the FT using the first to fourth values. The method of claim 11,
After the calculating of the first value, the calculating of the second value, the calculating of the third value, and the calculating of the fourth value are repeated by a predetermined cumulative number of times, the PCI And estimating the FT is performed. The method of claim 11,
The first value is calculated through addition calculation instead of multiplication operation,
And the third value is calculated through addition calculation instead of multiplication operation. An analog-to-digital converter configured to sample the secondary synchronization signal received from the transmitting apparatus into a digital signal to generate a first sampling signal;
A filter unit for filtering the first sampling signal, and
Extracting a frequency domain sample by channel estimation on the filtered first sampling signal, and performing physical correlation through decorrelating between the frequency domain standard signal of the secondary synchronization signal and the frequency domain sample. A sync estimator for estimating Cell ID) and 80 ms frame timing (FT),
The frequency domain standard signal includes a Fourier Series (FS) sequence including information on the FT, a Zadoff Chu (ZC) sequence including information about the PCI, and a scrambling sequence including information about the PCI. Receiving device comprising a. The method of claim 14,
The synchronous estimator,
Calculating a first value by performing cross-correlation between the Fourier Series (FS) sequence and the frequency domain sample, calculating a second value by performing cross-correlation between the ZC (Zadoff Chu) sequence and the first value,
Performing a cross-correlation between the scrambling sequence and the second value to calculate a third value and performing a CS (Cyclic Shift) combining to calculate the fourth value,
And receiving the PCI and the FT using the first to fourth values. The method of claim 15,
And the synchronization estimator is configured to estimate the PCI and the FT after repeatedly calculating the first to fourth values by a predetermined cumulative number of times. The method of claim 15,
And the first value is calculated through addition calculation instead of multiplication operation, and the third value is calculated through addition calculation instead of multiplication operation. The method of claim 14,
The synchronous estimator,
A first estimator configured to estimate a first value by performing inverse correlation between a first FS sequence and the frequency domain samples in the Fourier Series sequence;
A second estimator configured to estimate the second value by performing inverse correlation between a second sequence of the FS sequence and the frequency domain sample;
A third estimator configured to estimate a third value by performing inverse correlation between a third sequence of the FS sequences and the frequency domain samples;
A fourth estimator configured to estimate a fourth value by performing inverse correlation between a fourth sequence of the FS sequence and the frequency domain sample, and
And a selector for comparing the first to fourth values to estimate the PCI and the FT. The method of claim 14,
The synchronous estimator,
And removing the cyclic prefix (CP) from the first sampling signal, down sampling the sample from which the CP has been removed, and performing the fast sampled transform (FFT) to extract the frequency domain sample.

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