KR102047250B1 - semiconductor memory apparatus - Google Patents

semiconductor memory apparatus Download PDF

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KR102047250B1
KR102047250B1 KR1020120155558A KR20120155558A KR102047250B1 KR 102047250 B1 KR102047250 B1 KR 102047250B1 KR 1020120155558 A KR1020120155558 A KR 1020120155558A KR 20120155558 A KR20120155558 A KR 20120155558A KR 102047250 B1 KR102047250 B1 KR 102047250B1
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South Korea
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word line
main word
block
address
bank
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KR1020120155558A
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Korean (ko)
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KR20140085224A (en
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지성수
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에스케이하이닉스 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

In an embodiment, a semiconductor memory device may include a common block address generator configured to generate a common block address in response to a bank row address; And a plurality of main word line selectors for selectively activating a plurality of main word lines assigned to the cell block in response to the common block address.

Figure R1020120155558

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device for driving a word line.

The semiconductor memory device includes a plurality of cell blocks (also called Mat or unit cell arrays) in a memory bank, and each cell block includes a plurality of memory cells. In order to access a memory cell, a corresponding word line must be activated. For example, one cell block has a plurality of sub word lines, and a plurality of sub words lines for driving the plurality of sub word lines are required. The main word line of (Main word line) is provided.

When one memory bank is selected by a bank address, the semiconductor memory device decodes a row address input from the outside and drives a word line using the decoded row address. Responsive to the decoded row address, selectively activate a plurality of main word lines corresponding to the corresponding cell blocks among the plurality of cell blocks included in the memory bank, and reconfigure the plurality of sub word lines corresponding to the activated main word lines. Optionally activate it. As a result, a memory cell provided in one activated sub word line may be accessed in the memory bank.

1 is a view showing a layout area of a semiconductor memory device of the prior art.

Referring to FIG. 1, a conventional semiconductor memory device includes a plurality of banks. In general, one bank includes an X-DEC region 10, a Y-DEC region 11, an X-HOLE region 12, It can be divided into SWD region 13, BLSA region 14, SUB_HOLE region 15, and cell array region 16.

In general, a sub word line driver for selectively activating a plurality of sub word lines allocated to one cell array region 16 is located in the SWD region 13, and a main word line corresponding to the corresponding sub word line driver is provided. The main word line selector for activation is located in the X-DEC region 10.

The number of cell blocks is increasing due to the increase in capacity and integration of semiconductor memory devices. As the number of cell blocks increases, the area occupied by the cell blocks increases, but a circuit for driving the cell blocks located in the X-DEC region 10. The area occupied also increases.

2A is a diagram illustrating a semiconductor memory device for one conventional cell block.

Referring to FIG. 2A, a semiconductor memory device for driving a word line of one cell block according to the related art includes a block address generator 20, a main word line selector 21, and a sub word line selector 22. The sub word line driver 23 and the cell block 24 are included.

In operation, the block address generator 20 may generate the first and second block addresses BAX_M and BAX_S in response to the bank row address LAX_T. The main word line selector 21 selectively activates the plurality of main word lines MWLB in response to the first block address BAX_M. The sub word line selector 22 generates the sub word line select signal FX in response to the second block address BAX_S. The sub word line driver 23 selectively activates the plurality of sub word lines in response to the activated main word line and the sub word line selection signal FX to thereby activate the activated sub word lines in the cell block 24. To access the cell. For reference, the first and second block addresses BAX_M and BAX_S are for selectively driving a plurality of sub word lines, respectively, and may be a plurality of signals. The bank row address LAX_T is generated by a logical combination of an externally input row address and a bank address. The bank row address LAX_T is a signal that is activated only when a bank corresponding to the bank address is activated.

FIG. 2B illustrates a semiconductor memory device for a plurality of cell blocks included in a conventional memory bank.

Referring to FIG. 2B, in general, one memory bank 60 includes a plurality of cell blocks, and each cell block includes a corresponding sub word line driver, a corresponding main word line selector, and a corresponding block address generator. Equipped. For example, the first cell block 61 of the plurality of cell blocks may include a first subword line driver 51, a first main word line selector 41, and a first block address generator 31. Each).

The first block address generator 31 corresponding to the first cell block 61 disposed in the cell array region (FIGS. 1 and 16) is disposed in the X-DEC region (FIGS. 1 and 10). According to LAX, a first block address BAX_1 is generated. The first main word line selector 41 is disposed in the X-DEC region (FIGS. 1 and 10), and selectively activates the plurality of first main word lines MWLB1 according to the first block address BAX_1. The first sub word line driver 51 disposed in the SWD regions (FIGS. 1 and 13) is activated and operates in response to one main word line activated among the plurality of first main word lines MWLB1. An operation of selectively activating the first sub word line SWL1 is performed. For reference, a signal not shown in FIG. 2B may be additionally input to the first sub word line driver 51 to be used for an operation of selectively activating the sub word line.

Each operation of the second block address generator 32, the second main word line selector 42, and the second subword line driver 52 corresponding to the second cell block 62 may be described in detail. Since the description is the same as that of the block 61, the description thereof is omitted.

As described above, the conventional semiconductor memory device for driving a word line includes a sub word line driver, a main word line selector, and a block address generator corresponding to each cell block. Therefore, as the number of cell blocks increases, the area occupied by a plurality of block address generators disposed in the X-DEC region increases proportionally as the number of cell blocks increases, resulting in a common input to a plurality of block address generators. There is a problem in that the loading of the bank row address signal (FIG. 2B, LAX) is increased.

An embodiment of the present invention provides a semiconductor memory device capable of reducing the layout area occupied by the block address generator and reducing the load of the row address signal.

In an embodiment, a semiconductor memory device may include a common block address generator configured to generate a common block address in response to a bank row address; And a plurality of main word line selectors for selectively activating a plurality of main word lines assigned to the cell block in response to the common block address.

In addition, according to another embodiment of the present invention, a semiconductor memory device may include a memory bank including a plurality of cell blocks; A common block address generator for generating a common block address in response to the bank row address; And a plurality of main word line selectors for selectively activating a plurality of main word lines assigned to the cell block in response to the common block address.

The present technology based on the above-mentioned solution means can reduce the layout area of the X-DEC region of the semiconductor memory device and reduce the load of the row address.

1 is a view showing a layout area of a conventional semiconductor memory
FIG. 2A illustrates a semiconductor memory device for one conventional block of cells. FIG.
2B illustrates a semiconductor memory device for a plurality of cell blocks included in a conventional bank.
3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
4 is a detailed circuit diagram of the block control signal generator 100 of FIG. 3.
FIG. 5 is a detailed circuit diagram of the common block address generator 200 of FIG. 3.
6A, 6B, 6C, and 6D are detailed circuit diagrams of the first main word line selector 301 of FIG. 3.

Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

For reference, in the drawings and detailed description, terms, symbols, and symbols used to refer to elements, blocks, and the like may be indicated by detailed units as necessary, so that the same terms, symbols, and symbols are the same in the entire circuit. Note that it may not refer to. In general, logic signals and binary data values of a circuit are classified into high level or low level according to voltage level, and additionally, high impedance (Hi-Z) state, etc. can be added if necessary. Define and describe what you can have. In addition, a high level configuration for indicating an activation state of a signal and a circuit may be configured at a low level according to an embodiment.

A semiconductor memory device according to an embodiment of the present invention described below includes 32 (2 5 ) cell blocks in one bank, each cell block includes 512 (2 9 ) sub word lines, and each cell It is assumed that 64 (2 6 ) main word lines corresponding to the block are provided (when the coding ratio of a plurality of sub word lines per one main word line is 1: 8). Therefore, 14 bank row addresses (LAX0,1,2,3,4,5,6,7,8,9, A, B, C, D) to selectively activate one subword line in one bank. As a result, 2 14 (2 5 * 2 9 ) sub word lines can be selectively activated.

3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Here, as described above, although 32 cell blocks are provided in one bank, only 16 cell blocks will be described for convenience.

In addition, the bank row addresses LAX0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, and D are generated by a logical combination of an externally input row address and a bank address. This signal is activated when the bank corresponding to the bank address is activated. That is, the bank row addresses LAX0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, and D are for selecting one main word line included in one bank. Indicates which bank the row address corresponds to, and if the bank is not activated, the bank row address LAX0,1,2,3,4,5,6,7,8,9, A, B , C, D) is disabled. In addition, the bank row address may be decoded and used, for example, the bank row address LAX0 may be decoded and used as a 2-bit signal of LAX0 <0: 1>, and two LAX1 and 2 signals may be combined with each other. Can be decoded into a 4-bit signal of the decoded LAX12 <0: 3>.

For example, as shown in FIG. 2B, LAXD <0: 1> is a signal dividing 32 cell blocks into two groups. When LAXD <0> is activated, the first cell block group (of FIG. 3, 500) may be activated, and when LAXD <1> is activated, one of the second cell block group (not shown in FIG. 3) among 32 cell blocks may be activated. The sub word line can be activated. LAX9ABC <0:15> is a signal for selecting one of 16 cell blocks included in each of the first and second cell block groups. LAX012 <0: 7> (not shown in FIG. 3, but see FIG. 2A) shows 64 main words corresponding to one cell block when the main word line and the sub word line use a 1: 8 coding scheme. A signal for dividing a line into 512 sub word lines, that is, a signal for selecting one main word line from one of eight sub word lines. In addition, the remaining LAX34 <0: 3>, LAX56 <0: 3>, and LAX78 <0: 3> are signals for selecting one of the 64 main word lines corresponding to one cell block. Line selection address ”.

Referring to FIG. 3, a semiconductor memory device according to an embodiment of the present invention may include a block control signal generator 100, a common block address generator 200, and first to sixteenth main word line selectors 301 to 316. The main word line selection group 300 including the sub word line selection group 400 including the first to 16 sub word line drivers 401 to 416, and the first to 16 cell blocks 501 to 516. One bank 500 is included.

The block control signal generator 100 may be disposed in the X-DEC region, and in response to the bank row addresses LAXD <0> and LAX9ABC <0:15>, the first to 16th block enable signals MDECEN <0: 15> and the first to sixteenth word line non-driven control signals WLOFFB <0:15>. Here, the first to sixteenth block enable signals MDECEN <0:15> correspond to the first to sixteenth word line non-driven control signals WLOFFB <0:15>, respectively, and when the block enable signal is activated, The corresponding non-drive control signal is deactivated, and when the block enable signal is deactivated, the corresponding non-drive control signal is activated. For example, when the first block enable signal MDECEN <0> is activated, the corresponding first word line non-drive control signal WLOFFB <0> is deactivated and the first block enable signal ( When MDECEN <0> is deactivated, the corresponding first word line non-drive control signal WLOFFB <0> is activated.

As such, the block control signal generation unit (FIGS. 3 and 100) may be designed as the following circuit diagram.

4 is a detailed circuit diagram of the block control signal generator 100 of FIG. 3.

Referring to FIG. 4, the block control signal generation unit (FIGS. 3 and 100) may include first to fifteen NAND gates NAND1 to NAND15 and one to fifteen NAND gates that receive a bank row address LAXD <0> as one input. And first through fifteen inverters INV1 through INV15 that receive the outputs of the NAND1 through NAND15 and output the first through fifteen block enable signals MDECEN <0:15>, respectively. LAX9ABC <0:15> is input to each of the other inputs of the first to fifteen NAND gates NAND1 to NAND15, respectively, and the outputs of the first to fifteen NAND gates NAND1 to NAND15 are not driven. The signal is output as the signal WLOFFB <0:15>.

3, the common block address generation unit 200 may be disposed in the X-DEC region, which includes a row address LAXD <0> having bank information, and a main word line selection address LAX34 <0: 3. >, The first to 16 main word lines of the common block addresses BAX34 <0: 3>, BAX56 <0: 3>, and BAX78 <0: 3> in response to LAX56 <0: 3> and LAX78 <0: 3>. It supplies to the selection parts 301-316 in common. Here, each of the main word line selection units 301 to 316 is activated / deactivated and controlled through the corresponding word line non-drive signal WLOFFB or the block enable signal MDECEN.

Here, most preferably, the common block address generation unit 200 reaches the first to sixteenth main word line selection units where the common block addresses BAX34 <0: 3>, BAX56 <0: 3>, and BAX78 <0: 3> arrive. It is placed in a position that minimizes the farthest distance among the distances. As a result, the time required for the common block addresses BAX34 <0: 3>, BAX56 <0: 3>, and BAX56 <0: 3> to reach the main word line selector is minimized, thereby increasing the operation speed.

As such, the common block control signal generation unit (FIGS. 3 and 200) may be designed as the following circuit diagram.

FIG. 5 is a detailed circuit diagram of the common block control signal generator 200 of FIG. 3.

Referring to FIG. 5, first, LAXBAX34 of the common block address generation unit 200 for outputting the common block address BAX34 <0: 3> may include first to fourth NAND gates (NAND1, NAND2, NAND3, and NAND4), and first to fourth to NAND gates. 4 Inverters (INV1, INV2, INV3, INV4) are provided. The first NAND gate NAND1 receiving the bank row address LAXD <0> and the main word line selection address LAX34 <0> connects an output to an input of the first inverter INV1, and the first inverter INV1 is Connect the output to the common block address BAX34 <0>. The second NAND gate NAND2 receiving the bank row address LAXD <0> and the main word line selection address LAX34 <1> connects an output to an input of the second inverter INV2, and the second inverter INV2 Connect the output to the common block address BAX34 <1>. The third NAND gate NAND3 receiving the bank row address LAXD <0> and the main word line selection address LAX34 <2> connects an output to an input of the third inverter INV3, and the third inverter INV3 Connect the output to the common block address BAX34 <2>. The fourth NAND gate NAND4, which receives the bank row address LAXD <0> and the main word line selection address LAX34 <3>, connects an output to an input of the fourth inverter INV4, and the fourth inverter INV4 Connect the output to the common block address BAX34 <3>. As a result, the common block address generator 200 outputs the main word line selection address LAX34 <0: 3> to the common block address BAX34 <0: 3> when the bank row address LAXD <0> is activated at a high level. On the other hand, when the bank row address LAXD <0> is deactivated to the low level, all of the common block addresses BAX34 <0: 3> are deactivated to the low level and output. Next, LAXBAX56 and LAXBAX78 of the common block address generation unit 200 for outputting the common block addresses BAX56 <0: 3> and BAX78 <0: 3> are referred to as common block address BAX34 <0: 3> is the same as the case, so detailed description thereof will be omitted.

3, the main word line selection group 300 including the first to 16 main word line selection units 301 to 316 may be disposed in the X-DEC region, where the common block address BAX34 < 0 to 3, BAX56 <0: 3>, BAX78 <0: 3>, the first to second main word lines including a plurality of main word lines in response to the word line non-driving signal WLOFFB and the block enable signal MDECEN. 16 Activates one main word line from the main word line groups MWLB1 <0:63> to MWLB16 <0:63>. The first to 16 main word line selectors 301 to 316 each have a corresponding subword line driver. For example, the first main word line selector 301 may be connected to the first sub word line driver 401. It works in response. That is, when the first word line non-drive control signal WLOFFB <0> is inactivated and the first block enable signal MDECEN <0> is activated, the common block addresses BAX34 <0: 3> and BAX56 < Selectively activates one main wordline of the first main wordline group MWLB1 <0:63> including a plurality of main wordlines according to 0: 3> and BAX78 <0: 3>. 1 The sub word line driver is activated to selectively activate the sub word line.

The first main word line selector (Figs. 3 and 301) may be designed as the following circuit diagram.

6A, 6B, 6C, and 6D are detailed circuit diagrams of the first main word line selector 301 of FIG. 3.

Referring to FIG. 6A, the first main word line selection unit 301 includes first to fourth BAX78 drivers BAX78DRV0, BAX78DRV1, BAX78DRV2, and BAX78DRV3 that receive respective signals of the common block address BAX78 <0: 3>. . The first to fourth BAX78 drivers BAX78DRV0, BAX78DRV1, BAX78DRV2, and BAX78DRV3 each drive 16 main word lines, and are generally responsible for the first main word line group MWLB <0:63>. The first BAX78 driver BAX78DRV0 responds to WLOFFB <0>, MDECEN <0>, BAX34 <0: 3>, BAX56 <0: 3>, and BAX78 <0>, and the first main wordline group MWLB <0:63>) may activate one main word line among MWLB <0:15>. The rest of the second to fourth BAX78 drivers BAX78DRV1, BAX78DRV2, and BAX78DRV3 also replace only BAX78 <1>, BAX78 <2>, and BAX78 <3>, and have the same circuit configuration.

Referring to FIG. 6B, the first BAX78 driver BAX78DRV0 may further include the first to fourth BAX56 drivers BAX56DRV0, BAX56DRV1, BAX56DRV2, BAX56DRV3, and BAX78 <0 which receive respective signals of the common block address BAX56 <0: 3>. > Is connected to the gate, the drain is connected to the NBAXB56 node (NBAXB56), the first NMOS transistor (N78), the drain is connected to the source of the first NMOS transistor (N78) and the gate is the first block enable signal (MDECEN < 0>) and a second NMOS transistor NM having a source connected to the ground voltage VSS. The first to fourth BAX56 drivers BAX56DRV0, BAX56DRV1, BAX56DRV2, and BAX56DRV3 are respectively responsible for driving four main word lines. The first BAX56 driver BAX56DRV0 is configured to respond to the voltage levels of the WLOFFB <0>, BAX34 <0: 3>, BAX56 <0>, and NBAXB56 nodes NBAXB56, and the first main word line group MWLB <0:63 One of the main word lines of MWLB <0: 3> of>) may be activated. The remaining second to fourth BAX56 drivers BAX56DRV1, BAX56DRV2, and BAX56DRV3 also replace only BAX56 <1>, BAX56 <2>, and BAX56 <3>, and have the same circuit configuration. Here, when the first block enable signal MDECEN <0> is inactivated to a low level, the first to fourth BAX78 drivers BAX78DRV0, BAX78DRV1, BAX78DRV2, and BAX78DRV3 do not operate.

Referring to FIG. 6C, the first BAX56 driver BAX56DRV0 may again receive the first to fourth BAX34 drivers BAX34DRV0, BAX34DRV1, BAX34DRV2, BAX34DRV3, and BAX56 <0 that receive respective signals of the common block address BAX34 <0: 3>. NMOS transistor (N56_0) with> connected to the gate, the source connected to the NBAXB56 node (NBAXB56), and the drain connected to the NBAXB34 node (NBAXB34). The first to fourth BAX34 drivers BAX34DRV0, BAX34DRV1, BAX34DRV2, and BAX34DRV3 are respectively responsible for driving one main word line. The first BAX34 driver BAX34DRV0 is the MWLB <of the first main word line group MWLB <0:63> in response to the voltage levels of the WLOFFB <0>, BAX34 <0: 3>, and NBAXB34 nodes NBAXB34. 0> can be activated. The rest of the second to fourth BAX34 drivers BAX34DRV1, BAX34DRV2, and BAX34DRV3 also replace only BAX34 <1>, BAX34 <2>, and BAX34 <3>, and have the same circuit configuration.

Referring to FIG. 6D, the first BAX34 driver BAX34DRV0 connects a boosted voltage VPP to a source, a node A (A) to a drain, and a WLOFFB <0> to a gate, and a first PMOS transistor P1. A second PMOS transistor P2 having a boost voltage VPP connected to the source, a node A (A) connected to the drain, a node B (B) connected to the gate, and a node A (A) connected to the drain A first NMOS transistor N1 having a NBAX34 node (NBAX34) connected thereto and a BAX34 <0> connected to a gate thereof, a first inverter INV1 that receives a node A (A) and outputs it to a node B (B); and And a second inverter INV2 that receives the node B (B) and outputs it to MWLB1 <0>. If the NBAX34 node NBAX34 becomes the ground voltage, MWLB1 <0> may be activated according to BAX34 <0> and WLOFFB <0>. That is, if BAX34 <0> is activated at high level and WLOFFB <0> is disabled at high level, MWLB1 <0> is activated at low level, while BAX34 <0> is disabled at low level and WLOFFB <0> is disabled. When this low level is activated, MWLB1 <0> is deactivated to a high level. The rest of the second to fourth BAX34 drivers BAX34DRV1, BAX34DRV2, and BAX34DRV3 also replace only BAX34 <1>, BAX34 <2>, and BAX34 <3>, and have the same circuit configuration.

3, the sub word line selection group 400 including the first to sixteenth sub word line drivers 401 to 416 is located in the SWD regions (FIGS. 1 and 13) adjacent to the corresponding cell blocks, respectively. The first to 16 main word line selectors 301 to 316 and the first to 16 cell blocks 501 to 516 correspond to each other. For example, the first cell block 501 corresponds to the first sub word line driver 401 and the first main word line selector 301.

The first to sixteenth sub word line drivers 401 to 416 respectively activate one sub word line in response to a main word line selectively activated from a corresponding main word line selector. For example, when the main word line of one of the 64 main word lines MWLB1 <0:63> output by the first main word line selector 301 is activated, the first main word line selector 3010. ). The first sub word line driver 201 corresponding to) activates one sub word line of the first sub word line group SWL1 <0: 511> including a plurality of sub word lines. For reference, although not shown in FIG. 3, referring to FIG. 2A, the sub word line driver receiving BAX0,1,2 generated by the bank row addresses LAX0,1,2 is a 1: 8 coding scheme. One of the eight sub word lines corresponding to the main word line of N may be selectively activated.

3, the first to sixteenth cell blocks 501 to 516 are each provided with a plurality of memory cells. The memory cells connected to the activated sub word line may be activated according to an operation of the sub word line driver corresponding to each cell block to read / write data of the activated memory cells.

As described above, in the semiconductor memory device of FIG. 3, the plurality of main word lines are selected from the common block addresses BAX34, BAX56, and BAX78 in response to the main wordline selection addresses LAX34, 56, and 78. By providing a common block address generation unit 200 which is commonly supplied to the units 301-310, the layout area occupied by a plurality of conventional block address generation units (FIGS. 2B and 200) can be eliminated, and the common block address Since the main word line selection addresses LAX34, LAX56, and LAX78, which are input to the generation unit 200, are connected only to the common block address generation unit 200, loads of the main word line selection addresses LAX34, LAX56, and LAX78 have to be loaded. Can be reduced.

According to another exemplary embodiment, a common block address generation unit for supplying common block addresses BAX34 and BAX56 to a plurality of main word line selection units in common in response to, for example, LAX34 and LAX56, which are a part of a main word line selection address. In this case, the layout block area occupied by a plurality of individual block selection address generation units (FIGS. 2B and 200) can be reduced, and LAX34 and LAX56 which are a part of the main word line selection address inputted to the common block address generation unit are common. Since only the block address generator 200 is connected, the load of the main word line selection addresses LAX34 and LAX56 can be reduced.

As described above, specific description has been given in accordance with an embodiment of the present invention. For reference, although not directly related to the technical spirit of the present invention, in order to explain the present invention in more detail, an embodiment including an additional configuration may be exemplified, and an active high ( Active High) or Active Low configuration may vary depending on the embodiment. In addition, according to another exemplary embodiment, a person skilled in the art may easily change according to the number of cell blocks, the coding method of the main word line and the sub word line, and the decoding method of the row address.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

100: block control signal generation unit
200: common block address generation unit
301-316: 1st-16th main word line selector
401 to 416: first to sixteenth sub word line drivers
501 to 516: first to sixteenth cell block

Claims (7)

A memory bank having a plurality of cell blocks;
A block control signal generator for outputting a plurality of block enable signals respectively corresponding to the plurality of cell blocks in response to bank row addresses;
A common block address generation unit for generating a common block address common to the plurality of cell blocks in response to the bank row address and the main word line selection address; And
A plurality of main word line selectors, each of which is activated according to a corresponding one of the plurality of block enable signals, for selectively activating a plurality of main word lines assigned to the corresponding cell block in response to the common block address;
A semiconductor memory device having a.
The method of claim 1,
A plurality of sub word line drivers for selectively activating a plurality of sub word lines assigned to the cell block in response to the activated main word lines of the corresponding main word line selection unit.
A semiconductor memory device further comprising.
The method of claim 1,
And the block control signal generator and the common block address generator are disposed in an X-DEC area.
The method of claim 1,
The common block address generation unit
And the common block address is disposed at a position capable of minimizing the longest distance among the distances running to the plurality of main word line selectors.
The method of claim 1,
And the bank row address is generated by a logical combination of an externally input row address and a bank address. delete delete
KR1020120155558A 2012-12-27 2012-12-27 semiconductor memory apparatus KR102047250B1 (en)

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KR102047250B1 true KR102047250B1 (en) 2019-11-21

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