KR102038384B1

KR102038384B1 - Nano sturucture semiconductor light emitting device

Info

Publication number: KR102038384B1
Application number: KR1020140074785A
Authority: KR
Inventors: 유건욱; 이규철; 최영빈; 허재혁
Original assignee: 삼성전자주식회사; 서울대학교산학협력단
Priority date: 2014-06-19
Filing date: 2014-06-19
Publication date: 2019-10-31
Also published as: KR20150145756A

Abstract

The present invention relates to a nanostructure semiconductor light emitting device, comprising: a base layer comprising a first conductivity type semiconductor; A plurality of nanocores each disposed on the base layer, the first conductive semiconductor being divided into a first region and a second region in a vertical direction from the base layer, and a second region of the plurality of nanocores A plurality of nano light emitting structures having an active layer and a second conductivity type semiconductor layer sequentially disposed on a surface of the semiconductor layer; A conductive protective layer disposed on a surface of the second conductive semiconductor layer of the plurality of nano light emitting structures; And a current blocking layer obtained by oxidizing at least an end of the active layer, thereby reducing leakage current on the surface of the light emitting structure, thereby improving the light emitting efficiency of the nano light emitting structure.

Description

Nano structure semiconductor light emitting device {NANO STURUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE}

The present invention relates to a nanostructure semiconductor light emitting device.

The light emitting diode is a device in which a material contained in the device emits light by using electrical energy. The light emitting diode converts energy generated by recombination of electrons and holes of the bonded semiconductor into light. Such light emitting diodes are widely used as lighting, display devices, and light sources, and their development is being accelerated.

In particular, the development of general lighting using light emitting diodes has recently been fueled by the commercialization of mobile phone keypads, turn signal lamps, and camera flashes using gallium nitride (GaN) based light emitting diodes, which have been actively developed and used. Like LED backlight units of large TVs, automotive headlights, and general lighting, LED light emitting diodes are increasingly being used for large-scale, high-output, and high-efficiency products, which improves the light extraction efficiency of light-emitting diodes used in such applications. There is a need for a way to do this.

There is a need in the art for a nanostructure semiconductor light emitting device capable of improving the luminous efficiency of a nano light emitting structure.

One embodiment of the invention the base layer consisting of a first conductivity type semiconductor; A plurality of nanocores each disposed on the base layer and formed of a first conductivity type semiconductor and divided into a first region and a second region in a vertical direction from the base layer, and a second region of the plurality of nanocores A plurality of nano light emitting structures having an active layer and a second conductivity type semiconductor layer sequentially disposed on a surface of the semiconductor layer; A conductive protective layer disposed on a surface of the second conductive semiconductor layer of the plurality of nano light emitting structures; And a current blocking layer obtained by oxidizing at least an end of the active layer.

The current blocking layer may include an end portion of the second conductive semiconductor layer and a region in which the first region of the nanocore is oxidized.

The current blocking layer may extend from the first region of the nanocore to the surface of the base layer.

The current blocking layer may be formed to a thickness of about 5nm to about 200nm.

The conductive protective layer may be made of a metal material.

The conductive protective layer may have a light transmittance.

The nano light emitting structure may have a side surface having a first crystal surface that is substantially perpendicular to a crystal surface of the base layer, and an upper end portion that is a second crystal surface different from the first crystal surface.

The first region of the nanocore may have a smaller width than the second region of the nanocore.

Another embodiment of the invention is a base layer made of a first conductivity type semiconductor; An active layer and a second conductive semiconductor layer disposed on the base layer and spaced apart from a plurality of nanocores formed of a first conductivity type semiconductor, and spaced apart from an upper surface of the base layer, and sequentially disposed on surfaces of the plurality of nanocores; A plurality of nano light emitting structures having; A conductive protective layer disposed on a surface of the second conductive semiconductor layer; And an insulating support member disposed between the nano light emitting structures to cover a portion of the conductive protective layer, wherein the insulating support member is formed on the surface of the nano core so as to be positioned at an end surface of the active layer and an adjacent surface thereof. It provides a nanostructure semiconductor light emitting device characterized in that it extends to the non-region.

The region where the nanocore is located in the base layer may have a higher level surface than other regions.

The nanostructure semiconductor light emitting device according to the embodiment of the present invention has the effect of reducing the leakage current on the surface of the nano light emitting structure, thereby improving the light emitting efficiency of the nano light emitting structure.

In addition, the solution and effect of said subject are not limited to what was mentioned above. Various features of the present invention and the advantages and effects thereof may be understood in more detail with reference to the following specific embodiments.

1 is a cross-sectional view of a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
FIG. 2 is an enlarged view of portion A of FIG. 1.
3A to 3F are cross-sectional views of main processes illustrating a manufacturing process of a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
4A to 4E are cross-sectional views of main processes illustrating an example of a current blocking layer forming process that may be applied to the nanostructure semiconductor light emitting device obtained in FIG. 3F.
5A to 5C are cross-sectional views of main processes illustrating an example of an electrode forming process that may be applied to the nanostructure semiconductor light emitting device obtained in FIG. 4E.
FIG. 6 is an enlarged view of a portion B of FIG. 3F.
7 is a cross-sectional view of a nanostructure semiconductor light emitting device according to another embodiment of the present invention.
FIG. 8 is a modification of the nanostructure semiconductor light emitting device of FIG. 7.
9 is a cross-sectional view of a nanostructure semiconductor light emitting device according to still another embodiment of the present invention.
FIG. 10 is a modification of the nanostructure semiconductor light emitting device of FIG. 1.
FIG. 11 is another modified example of the nanostructure semiconductor light emitting device of FIG. 1.
12 is a graph showing the leakage current reduction effect of the nanostructure semiconductor light emitting device of the present invention.
13 and 14 illustrate various examples of a semiconductor light emitting device package employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
15 and 16 show an example of a backlight unit employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
17 shows an example of a lighting apparatus employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.
18 shows an example of a head lamp employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Shape and size of the elements in the drawings may be exaggerated for more clear description.

1 is a cross-sectional view of a nanostructure semiconductor light emitting device according to an embodiment of the present invention, and FIG. 2 is an enlarged view of portion A of FIG. 1.

As shown in FIG. 1 and FIG. 2, the nanostructure semiconductor light emitting device 1 according to the present embodiment includes a base layer 12 made of a first conductivity type semiconductor and a plurality of nanolight emitting structures formed on an upper surface thereof. 15).

The plurality of nano light emitting structures 15 may include an active layer 15b and a second conductive semiconductor layer 15c sequentially formed on the surface of the nanocore 15a 'made of the first conductive semiconductor and the nanocore 15a'. ).

The base layer 12 is formed on the substrate 11 to provide a growth surface of the nano light emitting structure 15 and to electrically connect one side polarities of the plurality of nano light emitting structures 15. Can be. Meanwhile, the region where the nanocores 15a are located in the base layer 12 may have a higher level surface than other regions.

The substrate 11 may be an insulating, conductive or semiconductor substrate. For example, the substrate 11 may be sapphire, SiC, Si, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , GaN. The base layer 12 may be a nitride semiconductor that satisfies Al _x In _y Ga ₁ _-x- _y N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1) It may be doped with n-type impurities such as Si to have a form.

A plurality of nanocores 15a made of a first conductivity type semiconductor are formed on the base layer 12, and an active layer 15b and a second conductivity type semiconductor layer 15c are sequentially formed on the surface of the nanocore 15a. By forming the nano-light emitting structure 15 of the so-called shell structure can be formed.

The first conductive semiconductor of the nanocore 15a may be an n-type nitride semiconductor, for example, n-type Al _x In _y Ga ₁ _-x- _y N (0 ≦ x <1, 0 ≦ y <1). , 0 ≦ x + y <1). The first conductivity type semiconductor constituting the nanocore 15a may be made of the same material as the first conductivity type semiconductor of the base layer 12. For example, the base layer 12 and the nanocores 15a may be formed of n-type GaN.

The active layer 15b may have a multi-quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked, for example, a nitride semiconductor, and a GaN / InGaN or GaN / AlGaN structure. Alternatively, a single quantum well (SQW) structure may be used. The second conductive semiconductor layer 15c may be a crystal that satisfies p-type Al _x In _y Ga ₁ _-xy N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1). The second conductivity type semiconductor layer 15c may further include a current blocking layer (not shown) adjacent to the active layer 15b. The current blocking layer (not shown) are stacked with each other a plurality of _{Al x In y Ga 1 -x- y} N (0≤x <1, 0≤y <1, 0≤x + y <1) of different compositions It may have a structure or one or more layers consisting of Al _y Ga _(1-y) N (0≤y <1), the band gap is larger than the active layer 15b, the second conductivity type (p-type) semiconductor layer 15c To prevent electrons from falling over.

As shown in FIG. 2, the nano light emitting structure 15 according to the exemplary embodiment of the present invention has a shape where an end portion is removed, and a dotted line part of FIG. 2 indicates the removed region. This end includes at least an end of the active layer 15b, and may include adjacent first and second conductivity type semiconductor layers 15a and 15c. The removed region may be removed to have a distance of at least t1 from the surface of the end, and the surface of the end is formed to have a distance of D from the top surface of the base layer 12.

One region of the end and side surfaces of the nano light emitting structure 15 of this configuration may be filled with the same material. Specifically, the area of the nano light emitting structure 15 and the base layer 12 may be filled with an insulating material. The top surfaces can be insulated from each other.

The nano light emitting structure 15 of this configuration has an effect that can reduce the leakage current. This will be described in detail.

FIG. 6 illustrates a state before the end of the nano light emitting structure is removed. Reference numeral 13a denotes a first material layer 13a used as a mask for growing the nanocores 15a '. The area P where the end portion of the nano light emitting structure 15 and the first material layer 13a come into contact with each other causes stress on the bonding surface due to bonding between dissimilar materials, and the stress of the nano light emitting structure 15 The crystallinity is lowered to form an amorphous surface on the surface of the nano light emitting structure 15. The first and second conductivity-type semiconductor layers formed on the amorphous surface do not form a normal P-N junction, and thus leakage current may occur. Since the leakage current causes a problem of lowering the luminous efficiency of the entire nano light emitting structure 15, if the current is replaced by an insulator or the amorphous surface is removed, the leakage current is fundamentally reduced. The luminous efficiency of the light emitting nanostructures 15 may be improved.

In this embodiment, the end portion of the nano light emitting structure 15 in which the leakage current is generated is removed, thereby essentially blocking a path through which the leakage current flows through the end of the nano light emitting structure 15. Therefore, there is an effect that the probability of the leakage current is greatly reduced.

The conductive protective layer 16 is formed on the surface of the nano light emitting structure 15. The conductive protective layer 16 is formed separately from the surface of each of the plurality of nano light emitting structures 15. The conductive protective layer 16 is to prevent the nano light emitting structure 15 from being damaged during the plasma treatment in the manufacturing process, and is formed of a material having a light transmittance so as to pass light emitted from the active layer 15b. It may be formed of a material such as Ni / Au to have conductivity. The conductive protective layer 16 is formed so that the nano light emitting structure 15 has a thin thickness while being sufficient not to be damaged in the plasma process, thereby preventing the light emitted from the active layer 15b from being absorbed or reflected. It is preferable. In this embodiment, the conductive protective layer 16 may be formed to a thickness of about 1 μm or less.

The contact electrode 19 is formed on the conductive protective layer 16 so that each conductive protective layer 16 is electrically connected. The nanostructure semiconductor light emitting device 1 may include first and second electrodes 21a and 21b connected to the base layer 12 and the contact electrode 19, respectively.

The contact electrode 19 may be obtained by electroplating the surface of the conductive protective layer 16. The seed layer (not shown) may employ a material suitable for realizing ohmic contact with the second conductivity type semiconductor layer.

The ohmic contact material may include at least one of materials such as ITO, ZnO, graphene layer, Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, and Ni / Ag, Zn / Ag, Ni / Al, Zn / Al, Pd / Ag, Pd / Al, Ir / Ag. Ir / Au, Pt / Ag, Pt / Al, Ni / Ag / Pt, or the like, may be employed in two or more layers. For example, after sputtering an Ag / Ni / Cr layer as a seed layer, Cu / Ni may be electroplated to form a desired contact electrode 19.

If necessary, after the contact electrode 19 is formed, a polishing process may be applied so that the contact electrode 19 has a flat top surface.

The contact electrode 19 used in the present embodiment is a form in which a reflective metal layer is introduced, and it can be understood that light is extracted in the direction of the substrate, but is not limited thereto. The contact electrode 19 may be formed of ZnO, graphene, or ITO. By employing a transparent electrode material such as can be extracted light in the direction of the nano light emitting structure (15).

FIG. 10 illustrates a modified example of the nanostructure semiconductor light emitting device of FIG. 1, in which a pyramidal nano light emitting structure 415 is formed. FIG. 11 illustrates another modified example of the nanostructure semiconductor light emitting device of FIG. 1, in which a current blocking layer 517 is formed at an end portion of the nanolight emitting structure 515 unlike the modified example of FIG. 10. In this case, the insulating member surrounding the nano light emitting structure 515 may be omitted and the contact electrode 519 may be charged.

Next, a light emitting diode package according to another embodiment of the present invention will be described. 7 is a cross-sectional view of a nanostructure semiconductor light emitting device according to another embodiment of the present invention.

In the case of the present embodiment, there is a difference that the current blocking layer 117 is further formed at the end of the nano light emitting structure 115 as compared with the embodiment described above. Since other configurations are the same as the above-described embodiment, the description will be mainly focused on other configurations.

As shown in FIG. 7, the nano light emitting structure 115 of the present embodiment has a difference in that a current blocking layer 117 having a thickness of t 2 is formed at an end thereof. The current blocking layer 117 is formed by oxidizing the nano light emitting structure 117. Specifically, the current blocking layer 117 may be formed through O ₂ plasma treatment. The current blocking layer 117 is not formed on the surface of the nano light emitting structure 115 on which the conductive protective layer 116 is formed, and the end and base layers of the nano light emitting structure 115 on which the conductive protective layer 116 is not formed. It may be formed only on the top surface of (112). In the present embodiment, Ga ₂ O ₃ may be used as the current blocking layer 117, and the current blocking layer 117 may be formed to a thickness of about 5 nm to about 200 nm.

FIG. 8 is a modification of the nanostructure semiconductor light emitting device of FIG. 7, in which a current blocking layer 223 is additionally formed on the conductive protection layer 216. The current blocking layer 223 insulates the upper portion of the nano light emitting structure 215 from the contact electrode 219 to flow current only to the side of the nano light emitting structure 215. However, the current blocking layer 223 may be formed by adjusting the amount of impurities doped in the upper or lower portion of the active layer 215b in addition to the upper portion of the conductive protective layer 216. In this case, since the current blocking layer 223 can be formed through MOCVD, there is an advantage in that the current blocking layer 223 can be formed in a process of manufacturing a nanostructure semiconductor light emitting device without an additional process.

Next, a light emitting diode package according to another embodiment of the present invention will be described. 9 is a cross-sectional view of a nanostructure semiconductor light emitting device according to another embodiment of the present invention.

In the case of the present embodiment, there is a difference in that the upper portion of the nano light emitting structure 315 is removed, and the current blocking layer 323 is further formed on the removed cross-section compared with the above-described embodiment. The rest of the configuration is the same as the above-described embodiment. The nano light emitting structure 315 having such a configuration insulates the upper portion of the nano light emitting structure 315 from the contact electrode 319 as in the modification of FIG. 8 so that current flows only to the side of the nano light emitting structure 215. It works.

Since the nanostructure semiconductor light emitting device having the above structure is blocked from leakage current generated through the end of the nano light emitting structure 15, the light emitting efficiency is improved. 12 is a graph showing the leakage current reduction effect of the nanostructure semiconductor light emitting device of the present invention.

Each of the three curved lines in FIG. 12 is a general case in which no current blocking layer is formed (0 sec), and a case in which a nano structure semiconductor light emitting device is formed of an O ₂ plasma at a temperature of 300 ° C. for 90 seconds with an intensity of 60 W ( 90sec), nanostructures nanostructures current of the semiconductor light emitting device in the case of forming the current blocking layer 300 seconds the O ₂ plasma to 60W intensity of the semiconductor light-emitting device at a temperature of 300 ℃ (300sec) - represents the voltage relationship.

When applied to each nanostructure semiconductor light emitting device with a voltage of 5V (forward voltage), it can be seen that the current of 15.4mA, 13.4mA, and 5.11mA flows in 0sec, 90sec, and 300sec, respectively. In addition, when a voltage of -5V (reverse voltage) is applied, it can be seen that currents of 0.88 mA, 0.48 mA, and 0.063 mA flow in 0 sec, 90 sec, and 300 sec, respectively. Based on this, if the value of (current forward voltage) / (current reverse voltage) is calculated, 0sec, 90sec, and 300sec are 21, 28, and 82, respectively, and when the current blocking layer is formed, It can be seen that the value of current) / (current of reverse voltage) increases significantly. This is because the value of the reverse current is greatly reduced, which shows that the leakage current is reduced.

Such a new nanostructure semiconductor light emitting device may be implemented using various manufacturing methods. 3A to 3F are cross-sectional views of main processes illustrating a manufacturing process of a nanostructure semiconductor light emitting device according to an embodiment of the present invention.

The manufacturing method begins with providing a base layer 12 made of a first conductivity type semiconductor.

As shown in FIG. 3A, a base layer 12 may be provided by growing a first conductivity type semiconductor on the substrate 11.

The base layer 12 is formed on the substrate 11, and may not only provide a crystal growth surface for growing the nano light emitting structure, but may also be provided as a structure for electrically connecting one side polarities of the nano light emitting structure to each other. Therefore, as described above, the base layer 12 is formed of a semiconductor single crystal having electrical conductivity. When the base layer 12 is directly grown, the substrate 11 may be a substrate for crystal growth.

The substrate 11 may be sapphire, SiC, Si, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , GaN. The substrate 11 may have a top surface on which hemispherical irregularities are formed. The unevenness is not limited to hemispherical shape, and may be variously modified. For example, the unevenness may be a shape having a cross section such as a triangle, a rectangle, and a trapezoid. By introducing such irregularities, not only the light extraction efficiency can be improved, but also the defect density can be reduced. In consideration of these effects, factors such as the cross-sectional shape, size and / or distribution of the unevenness may be variously selected.

The base layer 12 may be a nitride semiconductor that satisfies Al _x In _y Ga ₁ _-x- _y N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1) It may be doped with n-type impurities such as Si to have a form. For example, the thickness of the base layer 12 provided for growth of the nanocores 15a may be 1 μm or more. In consideration of the subsequent electrode forming process, the thickness of the base layer 12 may be 3 to 10㎛. The base layer 12 may include GaN having an n-type impurity concentration of 1 × 10 ¹⁸ / cm 3 or more. The buffer layer may be further formed before the base layer is formed.

In a particular example, the substrate 11 may be a Si substrate, in which case Al _y Ga _(1-y) N (0 ≦ _y ≦ 1) may be used as the buffer layer. For example, the buffer layer may have a structure in which two or more layers having different compositions are repeatedly stacked a plurality of times. The buffer layer may include a grading structure in which the composition of Al is gradually reduced or increased.

Next, as shown in FIG. 3B, a mask 13 having a plurality of openings H and interposing an etch stop layer is formed on the base layer 12.

The mask 13 employed in the present embodiment is formed on the first material layer 13a formed on the base layer 12 and on the first material layer 13a and formed of the first material layer 13a. The second material layer 13b having an etching rate greater than the etching rate may be included.

The first material layer 13a serves as the etch stop layer. That is, the first material layer 13a has an etching rate lower than that of the second material layer 13b under the same etching conditions.

At least the first material layer 13a is an electrically insulating material, and if necessary, the second material layer 13b may be an insulating material. The first and second material layers 13a and 13b may be different materials for a desired etch rate difference. For example, the first material layer 13a may be SiN, and the second material layer 13b may be SiO ₂ . Alternatively, the difference in the etching rate may be implemented using the pore density. In this case, the first and second material layers 13a and 13b may be formed of the same material having different pore densities.

The total thickness of the first and second material layers 13a and 13b may be designed in consideration of the height of the desired nano light emitting structure. The first material layer 13a has a thickness smaller than the thickness of the second material layer 13b. The etch stop level by the first material layer 13a is 1 / th of the total height of the mask 13 from the surface of the base layer 12 and the total thickness of the first and second material layers 13a and 13b. It can be located at three or less points.

The total height of the mask 13 and the total thickness of the first and second material layers 13a and 13b may be 1 μm or more, preferably 5 to 10 μm. The first material layer 13a may be 0.5 μm or less.

After the first and second material layers 13a and 13b are sequentially formed on the base layer 12, a plurality of openings H may be formed to expose regions of the base layer 12. The size of each opening H may be designed in consideration of the size of the desired nano light emitting structure. For example, the opening may be formed to be 500 nm or less in width and further 200 nm.

The opening H may be manufactured using a semiconductor process, and for example, the opening H having a high aspect ratio may be formed by using a deep etching process. The aspect ratio of the opening (H) may be implemented in 5: 1 or more, even 10: 1 or more.

The planar shape and arrangement of the opening H may be variously implemented. For example, in the case of a planar shape, it may be implemented in various ways, such as polygon, rectangle, oval, circle.

E1 and E2 regions of the mask 13 are regions where electrodes are to be formed in a subsequent process, and the opening H may not be formed in this region.

Next, as illustrated in FIG. 3C, a plurality of nanocores 15a are formed by growing a first conductivity type semiconductor in an exposed region of the base layer 12 so that the plurality of openings H are filled. .

The nitride single crystal constituting the nanocore 15a may be formed using a MOCVD or MBE process, and the mask 13 may serve as a mold of a grown nitride single crystal to correspond to the shape of the opening. Can be provided. That is, the nitride single crystal is selectively grown in the region of the base layer 12 exposed to the opening H by the mask 13 to fill the opening H, and the filled nitride single crystal is formed in the opening of the opening H. It may have a shape corresponding to the shape.

Next, as shown in FIG. 3D, the mask 13 is partially removed using the etch stop layer to expose side surfaces of the plurality of nanocores 15a.

In the present embodiment, an etching process is applied under the condition that the second material layer 13b can be selectively removed, and only the second material layer 13b is removed and the first material layer 13a is left. Can be. The first material layer 13a is used as an etch stop layer in the present etching process, and the active layer 15b and the second conductive semiconductor layer 15c are prevented from being connected to the base layer 12 in the subsequent growth process. Can play a role.

Next, as shown in FIG. 3E, after removing the second material layer 43, the nanocore 45a may be further heat-treated. Through such a heat treatment process, the surface of the nanocore 15a may be formed into a more stable crystal surface such as a nonpolar plane or a semipolar plane to improve the quality of subsequent grown crystals. The heat treatment conditions are carried out at least 900 ° C. and can be converted to a desired stable crystal surface by performing for several minutes to several tens of minutes.

For example, when grown using the C (0001) surface of the sapphire substrate, the nanocore shown in Figure 4a can be converted to an unstable curved non-polar surface (m surface) by heat treatment at 900 ℃ or more. The stabilization of the crystal surface may be implemented by a high temperature heat treatment process. This principle is difficult to explain clearly, but it can be understood that partial regrowth proceeds so that the residual source gas is deposited to have a stable crystal surface when the source gas remains in the chamber or the rearrangement of the crystal located on the surface at high temperature. .

In particular, in the case of regrowth, the heat treatment process may be performed in an atmosphere in which the source gas remains in the chamber, or may be heat treated under a condition in which a small amount of source gas is intentionally supplied. By heat treatment in such a residual atmosphere, partial regrowth may be performed so that the source gas reacts to the surface of the nanocore to have a stable crystal plane, and as shown in FIG. 3E, the size of the nanocore may be slightly increased.

Next, as shown in FIG. 3F, the active layer 15b and the second conductivity-type semiconductor layer 15c are sequentially grown on the surfaces of the plurality of nanocores 15a.

Through this process, the nano light emitting structure 15 is provided with a first conductive semiconductor as a nano core 15a, and an active layer 15b and a second conductive semiconductor layer 15b surrounding the nano core 15a are shell layers. It may have a core-shell structure provided by. In addition, the nano light emitting structure 15 has a side surface having a first crystal surface (I) substantially perpendicular to the crystal surface of the base layer 12, and an upper portion that is a second crystal surface (II) different from the first crystal surface (I) It can have

The active layer 15b may have a multi-quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked, for example, a nitride semiconductor, and a GaN / InGaN structure may be used. However, a single quantum well (SQW) may be used. You can also use the.

The second conductive type semiconductor layer (15c) can decision satisfying the p-type _{Al x In y Ga 1 -x- y} N. The second conductivity type semiconductor layer 15c may further include a current blocking layer (not shown) adjacent to the active layer 15b. The current blocking layer (not shown) may have a structure in which a plurality of n-type Al _x In _y Ga ₁ _-x- _y N layers having a plurality of different compositions or a layer of Al _y Ga _(1-y) N are stacked. The band gap is larger than that of the active layer 15b to prevent electrons from falling into the second conductivity-type (p-type) semiconductor layer 15c.

As described above, the nano light emitting structure 15 employed in the present embodiment is illustrated as a rod-shape as a core-shell structure, but is not limited thereto, such as a pyramid structure or a structure in which a pyramid and a rod are combined. It may have a different shape.

The active layer 15b may have a multi-quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked, for example, a nitride semiconductor, and a GaN / InGaN or GaN / AlGaN structure. Alternatively, a single quantum well (SQW) structure may be used.

4A to 4E are cross-sectional views of main processes illustrating an example of a current blocking layer forming process that may be applied to the nanostructure semiconductor light emitting device obtained in FIG. 3F.

First, as shown in FIG. 4A, the conductive protective layer 16 is formed on the surface of the nano light emitting structure 15 and the surface of the first material layer 13a. The conductive protective layer 16 may be formed of a material such as Ni / Au to prevent the nano light emitting structure 15 from being damaged during a plasma treatment in a subsequent process. The conductive protective layer 16 is formed so that the nano light emitting structure 15 has a thin thickness while being sufficient not to be damaged in the plasma process, thereby preventing the light emitted from the active layer 15b from being absorbed or reflected. It is preferable. In this embodiment, the conductive protective layer 16 may be formed to a thickness of about 1 μm or less.

Next, as shown in FIG. 4B, the conductive protective layer 16 formed on the surface of the first material layer 13a and the first material layer 13a is removed. Removal of the first material layer 13a and the conductive protective layer 16 may be performed through a chemical etching process. Specifically, the first material layer 13a and the conductive protective layer 16 may be performed through a wet etching process using a buffered oxide etchant (BOE). This process can be understood as removing the first material layer 13a in contact with the nano light emitting structure in order to oxidize the end of the nano light emitting structure 15 in a subsequent process. Therefore, the first material layer 13a may not be completely removed, and it is sufficient that at least an end portion of the active layer 15b of the nano light emitting structure 15 is removed to such an extent that an oxide film is formed in a subsequent process. 4B illustrates a case where the first material layer 13a is completely removed.

Next, as shown in FIG. 4C, the current blocking layer 17 is formed in the region including the end portion of the active layer 15b of the nano light emitting structure 15. The current blocking layer 17 may be formed to include at least an end portion of the active layer 15b. When the first material layer 13a is completely removed in the previous process, the current blocking layer 17 is formed only on the upper portion of the base layer 12, the end of the nano light emitting structure 15, and a part of the nano core 15a ′. This can be formed.

As described above, the end portion of the light emitting nanostructure 15 is in direct contact with the first material layer 13a. In this case, the surface of the nano light emitting structure 15 which is in contact with the first material layer 13a generates stress due to a material difference from the first material layer 13a. ) Crystallinity is reduced to form an amorphous surface. The first and second conductivity-type semiconductor layers formed on the amorphous surface do not form a normal P-N junction, and thus leakage current may occur. Since the leakage current causes a problem of lowering the luminous efficiency of the entire nano light emitting structure 15, if the current is replaced by an insulator or the amorphous surface is removed, the leakage current is fundamentally reduced. The luminous efficiency of the light emitting nanostructures 15 may be improved.

The present embodiment forms a current blocking layer in which an end portion of the nano light emitting structure 15 in which leakage current is generated is replaced by an oxide film, thereby fundamentally blocking a path through which the leakage current can flow through the end of the nano light emitting structure 15. It was.

The current blocking layer 15 may be formed through O ₂ plasma treatment. The O ₂ plasma treatment forms an oxide film on the surface of the semiconductor layer, but when the conductive material layer is formed on the surface of the semiconductor layer, the oxide film is not formed on the surface of the semiconductor layer. Therefore, in the previous process, the current blocking layer 17 is not formed on the surface of the nano light emitting structure 150 in which the conductive protective layer 16 'is formed, and the nano light emitting structure 15 in which the conductive protective layer 16' is not formed. The current blocking layer 17 is formed only at the end of the bottom and the upper surface of the base layer 12. In the present embodiment, Ga ₂ O ₃ may be formed as the current blocking layer 17, and the current blocking layer 17 may be formed to a thickness of about 5 nm to about 200 nm.

Next, as illustrated in FIG. 4D, the current blocking layer 17 may be removed by etching. The current blocking layer 17 may be removed through a chemical etching process, and specifically, may be performed through a wet etching process using a buffered oxide etchant (BOE).

Next, as shown in FIG. 4E, the insulating support member 18 is filled around the nano light emitting structure 15 to expose at least one region of the conductive protection layer 16 ′, and each conductive protection is performed. A contact electrode 19 is formed which electrically connects layer 16 '. An insulating protective layer 20 may be formed on the contact electrode 19.

The insulating support member 18 is a support for supporting the nano light emitting structure 15 to be firmly maintained. Specifically, TEE (TetraEthylOrthoSilane) is used to easily realize the filling of spaces between the nano light emitting structures 15. , BoroPhospho Silicate Glass (BPSG), CVD-SiO ₂ , Spin-on Glass (SOG), and Spin-on Delectric (SOD) materials may be used. However, the insulating support member 18 is advantageous when the nano light emitting structure 15 is particularly rod-shaped, but may not be formed when the pyramidal shape.

The contact electrode 19 may be formed of an ohmic contact material capable of realizing ohmic contact with the conductive protective layer 16 ′. For example, Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt and Au may include at least one, and may be provided in a single layer or a plurality of layers. In addition to such an electrode material, the contact electrode 19 may employ a transparent electrode material such as ITO, and ZnO or graphene may be used as necessary.

The insulating protective layer 20 may be used as long as it is an electrically insulating material capable of providing a passivation structure in a semiconductor process. As the insulating protective layer 20, a protective layer including an insulating material such as SiO ₂ or SiN _x may be used as the insulating support member 18 described above. In detail, the insulating protective layer 20 may include TEE (TetraEthylOrthoSilane), BPSG (BoroPhospho Silicate Glass), CVD-SiO ₂ , and SOG (Spin-), so as to easily fill the space between the nano light emitting structures 15. on Glass), SOD (Spin-on Delectric) material can be used.

In the present embodiment, the contact electrode 19 is provided in a thin layer form along the surface of the conductive protective layer 16 ', and is illustrated in such a manner as to fill the insulating protective layer 20 serving as a passivation layer. As shown in FIG. 11, the contact electrode 519 may be formed into a thick film, and thus, the contact electrode 519 may be changed to fill a space between the nano light emitting structures 515.

In the nanostructure semiconductor light emitting device illustrated in FIG. 4E, electrodes may be formed in various structures. 5A to 5C are cross-sectional views of main processes illustrating an example of an electrode forming process.

As shown in FIG. 5A, a portion of the base layer 12 may be exposed by selectively removing the insulating protective layer 20 and the insulating support member 18.

The exposed region O of the base layer 12 may provide a region where the first electrode is to be formed. The removal process may be implemented by an etching process using a photolithography process. When the nano light emitting structure 15 is positioned in the region O to be etched, a process of removing the nano light emitting structure is also required. However, as shown in FIG. 3B, the nano light emitting structure 15 may be formed in the regions E1 and E2 where the electrodes will be formed. Since the core 15a is not grown, there may be no nano light emitting structure 15 removed in the present process.

Subsequently, as shown in FIG. 5B, photoresist PR having first and second openings e1 and e2 may be formed.

The first and second openings e1 and e2 may define regions of formation of the first and second electrodes, respectively. In this process, the first opening e1 may expose a portion of the base layer 12, and the second opening e2 may expose a portion of the contact electrode 19.

Next, as illustrated in FIG. 5C, first and second electrodes 21a and 21b may be formed in the first and second openings e1 and e2. As the electrode material used in the present process, the common electrode material of the first and second electrodes 21a and 21b may be used. For example, the material for the first and second electrodes 21a and 21b may be Au, Ag, Al, Ti, W, Cu, Sn, Ni, Pt, Cr, Sn, TiW, AuSn, or eutectic metals thereof. It may include.

Subsequently, as illustrated in FIG. 1, an additional passivation layer 22 may be formed. The passivation layer 22 may be provided as a protective layer to protect the nano light emitting structure 15 together with the insulating protective layer 20. The passivation layer 22 may not only cover and protect the exposed semiconductor region, but also firmly maintain the first and second electrodes 21a and 21b. The passivation layer 22 may be made of the same or similar material as the insulating protective layer 20.

The mask employed in the above embodiment exemplifies a form composed of two material layers, but the present invention is not limited thereto and may be implemented in a form employing three or more material layers.

The nano semiconductor light emitting device according to the embodiment described above may be implemented in various packages.

13 and 14 show an example of a package employing the semiconductor light emitting device described above. However, the structure in which the nano-semiconductor light emitting device is mounted is not limited to the illustrated one, and may be mounted in a so-called flip-chip structure in which electrodes are disposed toward the mounting surface of the package body 502.

The semiconductor light emitting device package 500 illustrated in FIG. 13 may include a semiconductor light emitting device 501, a package body 502, and a pair of lead frames 503.

The semiconductor light emitting device 501 may be the nano semiconductor light emitting device described above. The semiconductor light emitting device 501 may be mounted on the lead frame 503 and electrically connected to the lead frame 503 through a wire (W).

If necessary, the semiconductor light emitting device 501 may be mounted in a region other than the lead frame 503, for example, the package body 502. In addition, the package body 502 may have a cup shape to improve the reflection efficiency of the light, the encapsulation body 505 made of a light-transmitting material to encapsulate the semiconductor light emitting device 501 and the wire (W) in the reflective cup. Can be formed.

The semiconductor light emitting device package 600 illustrated in FIG. 14 may include a semiconductor light emitting device 601, a mounting substrate 610, and an encapsulation 603.

A wavelength conversion unit may be formed on the surface and the side surface of the semiconductor light emitting device 601. The semiconductor light emitting device 601 may be mounted on the mounting substrate 610 and electrically connected to the mounting substrate 610 through a wire (W).

The mounting substrate 610 may include a substrate body 611, an upper electrode 613, a lower electrode 614, and a through electrode 612 connecting the upper electrode 613 and the lower electrode 614. The mounting substrate 610 may be provided as a substrate such as a PCB, MCPCB, MPCB, FPCB, etc. The structure of the mounting substrate 610 may be applied in various forms.

The wavelength converter 602 may include a phosphor, a quantum dot, or the like. Although the encapsulation 603 may be formed as a dome-shaped lens structure with an upper surface convex, according to the embodiment, the light is directed through the upper surface of the encapsulation 603 by forming the surface as a convex or concave lens structure. It is possible to adjust the angle.

The nanostructure semiconductor light emitting device and the package having the same according to the above-described embodiment can be advantageously applied to various applications.

15 and 16 show an example of a backlight unit employing a nanostructure semiconductor light emitting device according to an embodiment of the present invention.

Referring to FIG. 15, the backlight unit 1000 includes a light source 1001 mounted on a substrate 1002 and one or more optical sheets 1003 disposed thereon. The light source 1001 can use the above-mentioned semiconductor light emitting element or the package provided with the semiconductor light emitting element.

In the backlight unit 1000 of FIG. 14, the light source 1001 emits light toward the upper portion where the liquid crystal display device is disposed, whereas the backlight unit 2000 of another example illustrated in FIG. 16 is mounted on the substrate 2002. The light source 2001 may emit light in a lateral direction, and the light thus emitted may be incident on the light guide plate 2003 and converted into a surface light source. Light passing through the light guide plate 2003 is emitted upward, and a reflective layer 2004 may be disposed on the bottom surface of the light guide plate 2003 to improve light extraction efficiency.

17 is an exploded perspective view showing an example of a lighting device employing a semiconductor light emitting device according to an embodiment of the present invention.

The lighting apparatus 3000 illustrated in FIG. 17 is illustrated as a bulb-shaped lamp as an example, and includes a light emitting module 3003, a driver 3008, and an external connector 5010.

In addition, it may further include external structures such as the outer and inner housings 3006 and 3009 and the cover portion 3007. The light emitting module 3003 may include a light source 3001 having the above-described semiconductor light emitting device package structure or the like and a circuit board 3002 on which the light source 3001 is mounted. For example, the first and second electrodes of the semiconductor light emitting device described above may be electrically connected to the electrode patterns of the circuit board 3002. In this embodiment, one light source 3001 is illustrated in a form mounted on the circuit board 3002, but a plurality of light sources 3001 may be mounted as necessary.

The outer housing 3006 may act as a heat dissipation unit, and may include a heat dissipation plate 3004 and a heat dissipation fin 3005 surrounding the side surface of the lighting device 3000 to be in direct contact with the light emitting module 3003 to improve the heat dissipation effect. Can be. The cover 3007 may be mounted on the light emitting module 3003 and have a convex lens shape. The driver 3008 may be mounted on the inner housing 3009 and connected to an external connection part 3010 such as a socket structure to receive power from an external power source. In addition, the driver 3008 serves to convert and provide an appropriate current source capable of driving the semiconductor light emitting device 3001 of the light emitting module 3003. For example, the driver 3008 may be configured as an AC-DC converter or a rectifier circuit component.

18 shows an example in which the semiconductor light emitting device according to the embodiment of the present invention is applied to a head lamp.

Referring to FIG. 18, a head lamp 4000 used as a vehicle light includes a light source 4001, a reflector 4005, and a lens cover 4004, and the lens cover 4004 is a hollow guide. 4003 and lens 4002. The light source 4001 may include the above-described semiconductor light emitting device or a package having the semiconductor light emitting device.

The head lamp 4000 may further include a heat dissipation unit 4012 for dissipating heat generated from the light source 4001 to the outside, and the heat dissipation unit 4012 may include a heat sink 4010 and a cooling fan to perform effective heat dissipation. 4011. In addition, the head lamp 4000 may further include a housing 4009 for fixing and supporting the heat dissipating part 4012 and the reflecting part 4005, and the housing 4009 has a main body part 4006 and heat dissipating on one surface thereof. The center portion 4012 may be provided with a central hole 4008 for mounting.

The housing 4009 may include a front hole 4007 fixed to the reflector 4005 on the upper side of the light source 4001 on the other surface of the housing 4009 which is integrally connected to the one surface and is bent in a right direction. Accordingly, the front side is opened by the reflector 4005, and the reflector 4005 is fixed to the housing 4009 so that the open front corresponds to the front hole 4007, and the light reflected through the reflector 4005 is reflected. It may exit through the front hole 4007.

The invention is not limited by the embodiments described above and the accompanying drawings, which are intended to be limited by the appended claims. Accordingly, various forms of substitution, modification, and alteration may be made by those skilled in the art without departing from the technical spirit of the present invention described in the claims, which are also within the scope of the present invention. something to do.

11: substrate
12: base layer
15: nano light emitting structure
15a: Nanocore
15b: active layer
15c: second conductive semiconductor layer
16 ': conductive protective layer
18: insulating support member
19: contact electrode
20: insulating protective layer
22: passivation layer
21a: first electrode
21b: second electrode

Claims

A base layer made of a first conductivity type semiconductor;
A plurality of nanocores each disposed on the base layer and formed of a first conductivity type semiconductor and divided into a first region and a second region in a vertical direction from the base layer, and a second region of the plurality of nanocores A plurality of nano light emitting structures having an active layer and a second conductivity type semiconductor layer sequentially disposed on a surface of the semiconductor layer;
A conductive protective layer disposed separately on the surface of the second conductive semiconductor layer of the plurality of nano light emitting structures in units of the nano light emitting structure; And
And a current blocking layer obtained by oxidizing at least an end of the active layer.

The method of claim 1,
The current blocking layer is a nanostructure semiconductor light emitting device, characterized in that the end portion of the second conductive semiconductor layer and the first region of the nano-core is oxidized.

The method of claim 2,
The current blocking layer is a nanostructure semiconductor light emitting device, characterized in that extending from the first region of the nanocore to the surface of the base layer.

The method of claim 1,
The current blocking layer is a nanostructure semiconductor light emitting device, characterized in that formed in a thickness of 5nm ~ 200nm.

The method of claim 1,
The conductive protective layer is a nano-structure semiconductor light emitting device, characterized in that made of a metal material.

The method of claim 4, wherein
The conductive protective layer is a nanostructure semiconductor light emitting device characterized in that it has a light transmittance.

The method of claim 1,
And the nano light emitting structure has a side surface having a first crystal surface that is substantially perpendicular to a crystal surface of the base layer, and an upper end portion that is a second crystal surface different from the first crystal surface.

The method of claim 1,
The first region of the nanocores has a width smaller than the second region of the nanocores.

A base layer made of a first conductivity type semiconductor;
An active layer and a second conductive semiconductor layer disposed on the base layer and spaced apart from a plurality of nanocores formed of a first conductivity type semiconductor, and spaced apart from an upper surface of the base layer, and sequentially disposed on surfaces of the plurality of nanocores; A plurality of nano light emitting structure having;
A conductive protective layer disposed separately on the surface of the second conductive semiconductor layer in units of the nano light emitting structure; And
And an insulating support member disposed between the nano light emitting structures to cover a portion of the conductive protective layer.
And the insulating support member extends to a region where the active layer is not formed in the nanocores so as to be positioned at an end surface of the active layer and an adjacent surface of the active layer.

The method of claim 9,
The nanostructure semiconductor light emitting device of claim 2, wherein the region in which the nanocore is located has a higher level surface than other regions.