KR102037265B1 - Multi layered ceramic capacitor and method of manufacturing the same - Google Patents

Multi layered ceramic capacitor and method of manufacturing the same Download PDF

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Publication number
KR102037265B1
KR102037265B1 KR1020140178939A KR20140178939A KR102037265B1 KR 102037265 B1 KR102037265 B1 KR 102037265B1 KR 1020140178939 A KR1020140178939 A KR 1020140178939A KR 20140178939 A KR20140178939 A KR 20140178939A KR 102037265 B1 KR102037265 B1 KR 102037265B1
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South Korea
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electrode
ceramic body
dielectric layer
dummy
internal
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KR1020140178939A
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KR20160071610A (en
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이장현
최지숙
김경훈
문지희
박미옥
김민향
이순철
이승열
김경준
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삼성전기주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Abstract

The present invention is a ceramic body in which a plurality of dielectric layers are stacked, the first external electrode and the second external electrode formed on both sides of the ceramic body and spaced apart from each other on the same dielectric layer of the ceramic body, each exposed through both ends of the ceramic body And a dummy electrode and an internal electrode electrically connected to the first external electrode or the second external electrode, respectively, wherein the internal electrode and the dummy electrode are alternately arranged when the dielectric layer is stacked to form an overlap part of which overlaps. Since the contact between the internal electrode and the external electrode is further improved by further including vertically connected vias, the capacitance of the multilayer ceramic capacitor is not reduced.

Description

Multilayer Ceramic Capacitor and Method for Manufacturing the Same {MULTI LAYERED CERAMIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a multilayer ceramic capacitor and a method of manufacturing the same.

Multi-layered ceramic capacitors (MLCCs), a multilayer chip component, can be used in various electronic devices because of their small size, capacity, and ease of mounting.

For example, the multilayer ceramic capacitor may be used as an imaging device such as a liquid crystal display (LCD) and a plasma display panel (PDP), a computer, personal digital assistancts (PDAs), and a mobile phone. It can be used as a capacitor in the form of a chip mounted on a printed circuit board of various electronic products to charge or discharge electricity.

The multilayer ceramic capacitor is formed by stacking a plurality of ceramic sheets printed with internal electrodes, and includes a ceramic body including a cover part covering upper and lower portions of the stacked ceramic sheets and an external electrode formed on both sides of the ceramic body connected to the internal electrodes. Is formed.

The capacitance of the multilayer ceramic capacitor is designed by the number of stacked internal electrodes. A multilayer ceramic capacitor having a large number of internal electrodes may not be a big problem in securing capacitance even when some internal electrodes and external electrodes are not electrically connected.

However, in a multilayer ceramic capacitor having a small capacitance, some internal electrodes may not be electrically connected to an external electrode when a crack occurs due to warpage in the set after being mounted on a substrate.

In this case, the multilayer ceramic capacitor having a small number of stacks does not have a capacitance within a range designed by the product unless the connection reliability of the external electrode and some internal electrodes is secured.

Japanese Laid-Open Patent Publication 2005-0081297

The present invention was devised to solve the above-mentioned disadvantages and problems in the conventional multilayer ceramic capacitor, and includes a ceramic body for stacking a dielectric layer having a dummy electrode and an internal electrode spaced apart from each other. The purpose of the present invention is to provide a multilayer ceramic capacitor including an overlap portion in which an inner electrode and a dummy electrode overlap each other, and a via connecting upper and lower internal electrodes and the dummy electrode to each other.

The object of the present invention is a ceramic body in which a plurality of dielectric layers are stacked, the first external electrode and the second external electrode formed on both end surfaces of the ceramic body and the same dielectric layer of the ceramic body spaced apart from each other, A dummy electrode and an internal electrode electrically connected to the first external electrode or the second external electrode, respectively exposed through the cross-section, wherein the internal electrode and the dummy electrode are alternately arranged when the dielectric layer is stacked to form an overlap part. In addition, since the overlap part further includes a vertically connected via, a multilayer ceramic capacitor having improved contact between the internal electrode and the external electrode is provided.

In this case, another object of the present invention is to form an internal electrode and a dummy electrode spaced apart from each other on the same dielectric layer, to form a ceramic body by stacking a plurality of dielectric layers, vias connecting the dummy electrode up and down And forming a first external terminal and a second external terminal on both sides of the ceramic laminate, wherein the dummy electrode and the internal electrode are exposed through both end surfaces of the ceramic body, respectively. And a multilayer ceramic capacitor manufacturing method electrically connected with the first external electrode and the second external electrode.

As described above, the multilayer ceramic capacitor according to the present invention is composed of a ceramic body in which dummy electrodes formed on one dielectric layer and internal electrodes alternately formed up and down alternately, and thus, have good rigidity and do not bend external force.

In addition, the multilayer ceramic capacitor according to the present invention includes an overlap portion in which the dummy electrode and the internal electrode overlap vertically, and includes a via electrically connecting the dummy electrode and the internal electrode of the overlap portion, so that some internal electrodes are connected to the external electrode. If not, the remaining internal electrode or dummy electrode is connected to the external electrode has the advantage that the capacitance is not reduced.

1 is a cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention.
2 is a cross-sectional view of a multilayer ceramic capacitor according to another embodiment of the present invention.
3 is a flow chart showing a method for manufacturing a multilayer ceramic capacitor according to the present invention.

Advantages and features of the present invention, techniques for achieving them, and the like will become apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. This embodiment may be provided to make the disclosure of the present invention complete, and to fully inform the scope of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, 'comprise' and / or 'comprising' refers to a component, step, operation and / or element that is mentioned in the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions. It will be described through the drawings.

1 is a cross-sectional view of a multilayer ceramic capacitor 100 according to an embodiment of the present invention. As shown, the present invention comprises a ceramic body 110 in which a plurality of dielectric layers 111 are stacked and external electrodes 150 formed on both ends of the ceramic body, and are spaced apart from each other on the dielectric and exposed through both sides of the ceramic body, respectively. The dummy electrode 130 and the internal electrode 120 are electrically connected to the external electrode.

The dielectric layer 111 may include a material capable of obtaining sufficient capacitance. That is, the dielectric layer may include a ceramic material, but is not limited thereto. The dielectric layer may include ceramic powder, ceramic additives, organic solvents, plasticizers, binders or dispersants, and the like.

The dielectric layer 111 may be composed of a ceramic green sheet, and a ceramic powder, a polymer, a solvent, and the like, such as barium titanate (BaTiO 3 ) may be mixed to prepare a slurry, and then the slurry may be transferred to a carrier film through a method such as a doctor blade. It may be prepared by coating and drying on a carrier film to produce a sheet shape having a thickness of several μm.

The internal electrode 120 may be formed of a conductive material capable of storing and emitting charges, and may be formed on the dielectric 111. The conductive material may include one material selected from silver (Ag), lead (Pb), platinum (Pt), nickel (Ni), copper (Cu), or a combination thereof.

As the dielectrics are stacked, the internal electrodes 120 may be stacked to face each other with the dielectric layer 111 interposed therebetween. In this case, the internal electrode 120 may be electrically connected to the external electrode 150 formed on the side of the ceramic body.

In detail, the internal electrodes 120 are alternately disposed between the dielectric layers 111 so as to be electrically connected to the first external electrodes 151 and the second external electrodes 152, and the internal electrodes overlap with each other. The area can be configured to perform capacitor functions.

Meanwhile, the dummy electrode 130 may be formed on the same dielectric, spaced apart from the internal electrodes, and electrically connected to the first external electrode or the second external electrode, respectively, while being exposed through both end surfaces of the ceramic body. Herein, the dummy electrode 130 may provide rigidity to the multilayer ceramic capacitor 100 by reinforcing the weak rigid part on the dielectric layer 111 without forming a capacitance.

The internal electrode connected to the first external electrode 151 may be the first internal electrode 121, and the internal electrode connected to the second external electrode 152 may constitute the first internal electrode 122. The second dummy electrode 132 is provided in the dielectric layer on which the first internal electrode 121 is formed, so that the first internal electrode 121 is connected to the first external electrode 151 and the second dummy electrode 132 is second external. It may be connected to the electrode 152. In addition, the first dummy electrode 131 is spaced apart from the dielectric layer 111 on which the second internal electrode 122 is formed. In this case, the second internal electrode 122 is formed of the second external electrode 152 and the first dummy. The electrodes 131 may be connected to the first external electrodes 151, respectively.

In this case, the dielectric layers 111 may be alternately arranged in a form in which left and right are changed when stacked. Accordingly, overlapping portions 160 may be formed at both ends of the ceramic body 110 to partially overlap the dummy electrode and the internal electrode in the vertical direction. That is, the overlap unit 160 is a portion where the first internal electrode 121 and the first dummy electrode 131 overlap vertically or the second internal electrode 122 and the second dummy electrode 132 overlap vertically. Say part.

The overlap unit 160 may be electrically connected to the first internal electrode 121 and the first dummy electrode 131 through the via 140. Since the via 140 connects the internal electrodes not connected to the external electrodes with the remaining internal electrodes or dummy electrodes connected to the vias, the vias 140 do not form an error of a previously designed capacitance.

Meanwhile, the shortest horizontal distance from the external electrode to the via is called L1, the distance from the via to the internal electrode not connected to the via is called L2, the length of the dummy electrode is called L3, and the horizontal separation between the dummy electrode and the internal electrode. If the distance is L4,

First, L1 is formed smaller than L4. This, the multilayer ceramic capacitor is accompanied by a plasticization process to remove the internal binder (Binder), where L1 is larger than L4 may increase the delamination between layers and cracks during the ceramic body firing may increase the defective rate . The following table shows the crack failure rate along the length of L1 and L4.

L1 (㎛) L4 (㎛) Plastic Cracking Rate 100 400 0% 200 300 9.80% 300 200 15.50% 400 100 25.50%

As shown in Table 1, if L4 is larger than L1, it can be seen that the probability of crack occurrence during firing increases.

Next, L1 is formed longer than 10 micrometers.

When the external electrode 150 is formed, a step of cutting the side end of the ceramic body 110 is involved. At this time, when the distance between the via 140 and the external electrode 150 is smaller than 10 μm, the via is exposed to the side during cutting of the side of the ceramic body, and thus some connection of the via is lost, so that the first internal electrode 121 and the first internal electrode 121 are separated. Electrical connection of the dummy electrode 131 may be broken, and similarly, electrical connection between the second internal electrode 122 and the second dummy electrode 132 may be broken.

Next, the via 140 has a diameter d of greater than 10 μm and smaller than L1. The multilayer ceramic capacitor 100 includes a process of firing the ceramic body 110 after the process of stacking the plurality of dielectric layers 111 and forming the vias 140. In this case, the via may be disconnected in the process of pressing and heating the ceramic body. Therefore, the via must be larger than at least 10 μm to electrically connect the dummy electrode and the internal electrode of the overlap part in the process of forming the ceramic body. When the via diameter is larger than L1, the via of the ceramic body may be short-circuited with the external electrode, and the area for vertically supporting the dummy electrode may be reduced, causing cracks. Table 2 below shows the relationship between L1 and d.

L1 (㎛) d (μm) Short occurrence rate with external electrode 100 10 0% 100 50 34.4% 100 100 68.8% 100 200 100.0%

As shown in Table 2, it can be seen that as d becomes larger than L1, the short generation rate between the via and the external electrode increases.

2 is a cross-sectional view showing another embodiment of the present invention. Here, the configuration and difference of the embodiment of FIG. 1 will be described, and the repeated description will be avoided.

As shown, the present invention is a ceramic body 110 in which a plurality of dielectric layers 111 are stacked, the first external electrode 151 and the second external electrode 152 formed on both sides of the ceramic body and the same of the ceramic body A dummy electrode 130 and an inner electrode 120 spaced apart from each other on a dielectric layer and electrically connected to the first external electrode or the second external electrode, respectively, being exposed through both end surfaces of the ceramic body. And the dummy electrode may be alternately disposed when the dielectric layer is stacked to form an overlap portion 160 overlapping with each other, and the overlap portion may be electrically connected through the via 140.

The length L3 of the dummy electrode may be greater than the length of the external electrode that is extended by the external electrode leaded from the upper and lower portions of the ceramic body. Although the dummy electrode 130 is not configured to secure the capacitance of the capacitor, the thin ceramic capacitor is weak to warpage and is affected by the warpage of the substrate after being mounted on the substrate. The dummy electrode 130 may increase the stiffness of the ceramic body to prevent bending of the multilayer ceramic capacitor. In particular, when the dummy electrode is larger than the horizontal length of the external electrode, the rigidity is increased so that the internal electrodes may be shorted due to dielectric bending. Problems can be avoided.

Next, a method of manufacturing a multilayer ceramic capacitor according to the present invention will be described. 3 is a flowchart illustrating a method of manufacturing a multilayer ceramic capacitor according to the present invention.

The method of manufacturing a multilayer ceramic capacitor according to the present invention includes stacking a plurality of dielectric layers to form a ceramic body (S110), forming a via connecting a dummy electrode and an internal electrode in the ceramic body (S120), and a ceramic body. The step of firing (S130) and the step of forming an external electrode on the ceramic body side (S140).

First, in the forming of the ceramic body 110, the internal electrodes 120 and the dummy electrodes 130 are spaced apart from each other on the same dielectric layer 111. In addition, when the plurality of dielectric layers are stacked, the internal electrodes and the dummy electrodes are alternately arranged. In this case, the dummy electrodes and the internal electrodes may be partially overlapped with each other to form the overlap portion 160.

In detail, the first internal electrode 121 and the second dummy electrode 132 are spaced apart from each other on the same dielectric layer, and one end of the first internal electrode 121 is connected to the first external electrode 151 and the second dummy electrode. One end of the electrode 132 is connected to the second external electrode 152. A second internal electrode 122 and a first dummy electrode 131 are formed in the stacked adjacent dielectric layers, and one end of the second external electrode 152 and the first external electrode 151 are respectively connected. Therefore, the overlap part 160 may be a portion in which the first internal electrode and the first dummy electrode overlap each other or a portion in which the second internal electrode and the second dummy electrode overlap each other in the vertical direction.

Next, when the ceramic body 110 is formed, the via 140 may be formed to electrically connect the internal electrode 120 and the dummy electrode 130 of the overlap unit 160. The dummy electrode 130 does not constitute an active region that directly forms capacitance, but provides rigidity of the ceramic body and may be connected to the internal electrode through the via 140. Therefore, even if some of the internal electrodes are disconnected from the external electrode, if the remaining of some of the electrodes or the dummy electrode is effectively connected to the external electrode, the designed capacitance can be maintained.

Next, the ceramic body 110 is fired, and both sides of the ceramic body are cut to expose one end of the internal electrode 120 and the dummy pattern 130 on both sides of the ceramic body. In this case, the first internal electrode and the second dummy electrode are exposed in different directions, and the second internal electrode and the first dummy electrode are exposed in different directions, respectively. As a result, the first internal electrode and the first dummy electrode are exposed on one side of the ceramic body, and the second internal electrode and the second dummy electrode are exposed on the other side of the ceramic body.

The foregoing detailed description illustrates the present invention. In addition, the foregoing description merely shows and describes preferred embodiments of the present invention, and the present invention can be used in various other combinations, modifications, and environments. That is, changes or modifications may be made within the scope of the concept of the invention disclosed in this specification, the scope equivalent to the disclosed contents, and / or the skill or knowledge in the art. The above-described embodiments are for explaining the best state in carrying out the present invention, the use of other inventions such as the present invention in other state known in the art, and the specific fields of application and uses of the present invention. Various changes are also possible. Accordingly, the detailed description of the invention is not intended to limit the invention to the disclosed embodiments. Also, the appended claims should be construed to include other embodiments.

100. Multilayer Ceramic Capacitors
110. Ceramic body
111. Dielectric Layer
120. Internal Electrode
121. First internal electrode
122. Second internal electrode
130. Dummy electrode
131. First dummy electrode
132. Second dummy electrode
140.Via
150. External electrode
151. First external electrode
152. Second external electrode
160. Overlap

Claims (13)

A ceramic body in which a plurality of dielectric layers are stacked;
First and second external electrodes formed on both end surfaces of the ceramic body; And
A dummy electrode and an inner electrode spaced apart from each other on the same dielectric layer of the ceramic body and electrically connected to the first external electrode or the second external electrode, respectively, while being exposed through both end surfaces of the ceramic body.
The internal ceramics and the dummy electrodes alternately arranged along the stacking direction of the dielectric layer are electrically connected to each other by vias formed in the dielectric layer.
The method of claim 1,
The multilayer ceramic capacitor is a multilayer ceramic capacitor L1 is smaller than L4.
(L1 is the shortest horizontal length from the external electrode to the via, and L4 is the horizontal separation distance between the dummy electrode and the internal electrode.)
The method of claim 1,
The multilayer ceramic capacitor is a multilayer ceramic capacitor L1 is longer than 10㎛.
Where L1 is the shortest horizontal length from the external electrode to the via
The method of claim 1,
The multilayer ceramic capacitor has a via diameter greater than 10 μm and smaller than L1.
Where L1 is the shortest horizontal length from the external electrode to the via
Forming internal electrodes and dummy electrodes spaced apart from each other on the same dielectric layer;
Forming a ceramic body by stacking the plurality of dielectric layers such that the internal electrodes and the dummy electrodes are alternately disposed along the stacking direction of the dielectric layer;
Forming a via in the dielectric layer, the via connecting the internal electrode and the dummy electrode up and down;
Firing the ceramic body; And
Forming first external electrodes and second external electrodes on both end surfaces of the ceramic body; Including,
The dummy electrode and the internal electrode are exposed through both end surfaces of the ceramic body, respectively, and a method of manufacturing a multilayer ceramic capacitor electrically connected to the first external electrode and the second external electrode.
delete delete The method of claim 5,
The multilayer ceramic capacitor manufacturing method of the multilayer ceramic capacitor L1 is smaller than L4.
(L1 is the shortest horizontal length from the external electrode to the via, and L4 is the horizontal separation distance between the dummy electrode and the internal electrode.)
The method of claim 5,
The multilayer ceramic capacitor manufacturing method of a multilayer ceramic capacitor L1 is longer than 10um.
Where L1 is the shortest horizontal length from the external electrode to the via
A ceramic body in which a plurality of dielectric layers are stacked;
First and second external electrodes formed on both end surfaces of the ceramic body;
A first internal electrode exposed through one end surface of the ceramic body and electrically connected to the first external electrode;
A second internal electrode exposed through the other end surface of the ceramic body and electrically connected to the second external electrode;
A first dummy electrode spaced apart from the second internal electrode on the same dielectric layer and exposed through one end surface of the ceramic body to be electrically connected to the first external electrode; And
And a second dummy electrode spaced apart from the first internal electrode on the same dielectric layer and exposed through the other end surface of the ceramic body and electrically connected to the second external electrode.
The multilayer ceramic capacitor is electrically connected to the first internal electrode, the first dummy electrode, the second internal electrode, and the second dummy electrode by vias formed in the dielectric layer, respectively.
A ceramic body in which a plurality of dielectric layers are stacked;
First and second external electrodes formed on both end surfaces of the ceramic body; And
A dummy electrode and an inner electrode spaced apart from each other on the same dielectric layer of the ceramic body and electrically connected to the first external electrode or the second external electrode while being exposed through both end surfaces of the ceramic body, respectively.
The ceramic body,
An active part in which a part of the internal electrode overlaps the stacking direction of the dielectric layer; And
A region which is distinguished from the active part, and includes an overlap part in which the internal electrode and the dummy electrode are alternately disposed along the stacking direction of the dielectric layer on both end surfaces of the ceramic body,
And the inner electrode and the dummy electrode of the overlap part are electrically connected by vias formed in the dielectric layer of the overlap part.
Forming internal electrodes and dummy electrodes spaced apart from each other on the same dielectric layer;
Forming a ceramic body by stacking the plurality of dielectric layers such that the internal electrodes and the dummy electrodes are alternately disposed along the stacking direction of the dielectric layer;
Forming a via in the dielectric layer, the via connecting the internal electrode and the dummy electrode up and down;
Firing the ceramic body; And
Forming first and second external electrodes on both sides of the ceramic body;
The dummy electrode and the internal electrode are exposed through both end surfaces of the ceramic body, respectively, and are electrically connected to the first external electrode and the second external electrode.
The ceramic body,
An active part in which a part of the internal electrode overlaps the stacking direction of the dielectric layer; And
A region which is distinguished from the active part, and includes an overlap part in which the internal electrode and the dummy electrode are alternately disposed along the stacking direction of the dielectric layer on both end surfaces of the ceramic body,
And the inner electrode and the dummy electrode of the overlap part are electrically connected by the vias formed in the dielectric layer of the overlap part.
A ceramic body in which a plurality of dielectric layers are stacked;
First and second external electrodes formed on both end surfaces of the ceramic body;
A first internal electrode exposed through one end surface of the ceramic body and electrically connected to the first external electrode;
A second internal electrode exposed through the other end surface of the ceramic body and electrically connected to the second external electrode;
A first dummy electrode spaced apart from the second internal electrode on the same dielectric layer and exposed through one end surface of the ceramic body to be electrically connected to the first external electrode; And
And a second dummy electrode spaced apart from the first internal electrode on the same dielectric layer and exposed through the other end surface of the ceramic body and electrically connected to the second external electrode.
The ceramic body,
An active part overlapping a portion of the first internal electrode and the second internal electrode along a stacking direction of the dielectric layer at a central side of the ceramic body;
A first overlap part of the ceramic body, in which the first internal electrode and the first dummy electrode are alternately disposed and partially overlapped along the stacking direction of the dielectric layer; And
On the other end side of the ceramic body, the second internal electrode and the second dummy electrode along the stacking direction of the dielectric layer includes a second overlap portion which is partially overlapping,
The first internal electrode and the first dummy electrode are electrically connected by a first via formed in the dielectric layer of the first overlap part.
And the second internal electrode and the second dummy electrode are electrically connected by a second via formed in the dielectric layer of the second overlap part.

KR1020140178939A 2014-12-12 2014-12-12 Multi layered ceramic capacitor and method of manufacturing the same KR102037265B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101452126B1 (en) * 2013-08-08 2014-10-16 삼성전기주식회사 Embedded multilayer ceramic electronic part and print circuit board having embedded multilayer ceramic electronic part

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JP2005081297A (en) 2003-09-10 2005-03-31 Yodogawa Medekku Kk Substrate surface cleaning apparatus
JP4167231B2 (en) * 2005-01-13 2008-10-15 Ｔｄｋ株式会社 Multilayer capacitor and method for adjusting equivalent series resistance of multilayer capacitor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101452126B1 (en) * 2013-08-08 2014-10-16 삼성전기주식회사 Embedded multilayer ceramic electronic part and print circuit board having embedded multilayer ceramic electronic part

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