KR102036918B1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR102036918B1
KR102036918B1 KR1020120150092A KR20120150092A KR102036918B1 KR 102036918 B1 KR102036918 B1 KR 102036918B1 KR 1020120150092 A KR1020120150092 A KR 1020120150092A KR 20120150092 A KR20120150092 A KR 20120150092A KR 102036918 B1 KR102036918 B1 KR 102036918B1
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South Korea
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signal
level
external power
power source
abandoned
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KR1020120150092A
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Korean (ko)
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KR20140080384A (en
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김생환
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에스케이하이닉스 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Abstract

The semiconductor memory device is generated by pumping to the first external power source in response to a final power-up signal enabled when a first external power source reaches a first target level and the second external power source reaches a second target level. A pumping voltage supply unit supplying a pumping voltage, a control signal generation unit receiving the pumping voltage and generating a control signal driven by the pumping voltage when the final power-up signal is enabled, and in response to the control signal And a switch unit which is turned on and generates an internal power source driven by a second external power source and supplies the internal power source to the internal circuit.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of stably operating an internal circuit supplied with heterogeneous levels.

In general, a semiconductor memory device includes a power-up signal generation circuit for detecting whether an external power source has risen to a predetermined target level. The power-up signal generation circuit senses the level of the external power supply, and when the external power supply rises to a predetermined target level, the power transitions from a logic low level to a logic high level (in some embodiments, from a high level to a low level) Generate the up signal. Since the power-up signal includes information on whether or not the external power source is raised to the target level and stabilized, the internal circuit of the semiconductor memory device receives the power-up signal to determine an operation section.

However, in recent years, as the low power characteristic becomes more important, there are cases where two or more external power sources are used in the internal circuit of the semiconductor memory device. For example, the first external power source is used to generate the pumping voltage VPP, which is an internal voltage having a higher level than the external power source, and the second external power source is used to operate the internal circuit of the semiconductor memory device.

The first and second external power sources are externally applied, but when the first external power source is applied later than the second external power source, the level of the first external power source may not have a level sufficient to generate the pumping voltage VPP. . In this case, a phenomenon occurs in which the level of the pumping voltage VPP is lower than that of the first external power source. In addition, when the first external power source is applied later than the second external power source, the level of the second external power source is higher than the pumping voltage VPP, so that a well bias may be reversed.

A semiconductor memory device capable of stably operating an internal circuit supplied with heterogeneous levels is disclosed.

To this end, the present invention is generated by pumping to the first external power in response to the final power-up signal is enabled when the first external power reaches the first target level, the second external power reaches the second target level. A pumping voltage supply unit supplying the pumped voltage, a control signal generation unit receiving the pumping voltage and generating a control signal driven by the pumping voltage when the final power-up signal is enabled, and responding to the control signal. The present invention provides a semiconductor memory device including a switch unit which is turned on and generates an internal power source driven by a second external power source and supplies the internal power source to an internal circuit.

In addition, the present invention buffers the final power-up signal enabled when the first external power source reaches the first target level and the second external power source reaches the second target level in response to the deep power down mode signal. A buffer signal generation unit for generating a buffer signal, a level conversion unit for converting the level of the buffer signal to generate a conversion signal, a latch unit for latching the conversion signal to generate a control signal, and in response to the control signal Provided is a semiconductor memory device including a switch unit which is turned on and generates an internal power source driven by a second external power source and supplies the internal power source to an internal circuit.

According to the present invention, the external power supply having the heterogeneous level reaches the target level, and the voltage is supplied to the internal circuit after the pumping voltage level is normally generated, so that the internal circuit supplied with the heterogeneous level can be stably operated. have.

In addition, according to the present invention, by setting the level of the pumping voltage using the level of the first external power source before pumping the pumping voltage, it is possible to prevent a malfunction caused by setting the pumping voltage to a level lower than the first external power source. .

Further, according to the present invention, after the external voltages reach the target level regardless of the order in which the external power supplies are applied, the well bias is reversed by supplying the internal power generated from the second external power supply to the internal circuit. There is also an effect that can prevent the phenomenon from occurring.

1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an example embodiment of a power-up signal generator included in the semiconductor memory device shown in FIG. 1.
FIG. 3 is a circuit diagram of an example embodiment of the first detector included in the power-up signal generator shown in FIG. 2.
FIG. 4 is a circuit diagram of an embodiment of a second detector included in the power-up signal generator shown in FIG. 2.
FIG. 5 is a diagram illustrating an embodiment of a pumping voltage supply unit included in the semiconductor memory device shown in FIG. 1.
FIG. 6 is a diagram illustrating an embodiment of a control signal generator included in the semiconductor memory device shown in FIG. 1.
FIG. 7 is a circuit diagram of an embodiment of a level converter included in the control signal generator shown in FIG. 6.
8 is a diagram illustrating an example of an internal circuit included in the semiconductor memory device shown in FIG. 1.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, the semiconductor memory device according to the present embodiment includes a power-up signal generation unit 1, a pumping voltage supply unit 2, a control signal generation unit 3, a switch unit 4, and an internal circuit. 5) consists of. The power-up signal generator 1 generates a first power-up signal PWRUP1 that is enabled at a logic high level when the first external power supply VDD1 reaches the first target level. In addition, the power-up signal generator 1 is enabled at a logic high level when the first external power supply VDD1 reaches the first target level and the second external power supply VDD2 reaches the second target level. Generate the final power-up signal PWRUP_F. The first and second target levels may be set at various levels according to the embodiment. The pumping voltage supplier 2 supplies a pumping voltage VPP generated by being pumped from the first external power supply VDD1 when the final power-up signal PWRUP_F is enabled at a logic high level. The control signal generation unit 3 receives the first external power supply VDD1, the second external power supply VDD2, and the pumping voltage VPP so that the first power-up signal PWRUP1 and the final power-up signal PWRUP_F are supplied. When enabled and the deep power down mode signal DPD is disabled, the control signal CTR driven by the pumping voltage VPP is generated. The switch unit 4 is turned on when the control signal CTR is driven by the pumping voltage VPP to drive the internal power supply VDD2T supplied to the internal circuit 5 to the second external power supply VDD2. The deep power down mode signal DPD stops generation of an internal voltage including a pumping voltage VPP to reduce power consumption while the first external power source VDD1 and the second external power source VDD2 are applied. When the deep power down mode is entered, the signal is enabled to the logic high level.

2 is a diagram illustrating an example of the power-up signal generator 1.

As shown in FIG. 2, the power-up signal generator 1 includes a first detector 11, a second detector 12, and a signal synthesizer 13. When the first external power supply VDD1 reaches the first target level, the first detector 11 generates a first power-up signal PWRUP1 that is enabled at a logic high level. When the second external power supply VDD2 reaches the second target level, the second detector 12 generates a second power-up signal PWRUP2 that is enabled at a logic high level. When both the first power-up signal PWRUP1 and the second power-up signal PWRUP2 are enabled at a logic high level, the signal synthesis unit 13 generates a final power up signal PWRUP_F that is enabled at a logic high level. do. In summary, the final power-up signal PWRUP_F generated by the power-up signal generation unit 1 has the first external power supply VDD1 reaching the first target level and the second external power supply VDD2 reaching the second target level. When it reaches, it is enabled to logic high level.

3 is a circuit diagram of an example of the first detector 11.

As illustrated in FIG. 3, the first sensing unit 11 includes a resistor R11, an NMOS transistor N11, and a buffer 111. The resistor element R11 is connected between the first external power source VDD1 and the node nd11. The NMOS transistor N11 is connected between the node nd11 and the ground voltage VSS and is turned on in response to the first external power source VDD1. The buffer unit 111 includes inverters IV11 and IV12 driven by a first external power source VDD1 and a ground voltage VSS, and buffers a signal of the node nd11 to generate a first power-up signal ( PWRUP1). The resistive element R11 supplies a charge to the node nd11, and the NMOS transistor N11 emits a charge of the node nd11. As the level of the first external power source VDD1 increases, the level of the node nd11 increases when the charge supplied through the resistor R11 is set to be larger than the charge emitted through the NMOS transistor N11. Accordingly, the first power-up signal PWRUP1 output from the buffer 111 transitions to the logic high level when the first external power supply VDD1 reaches the first target level.

4 is a circuit diagram of an example of the second sensing unit 12.

As shown in FIG. 4, the second sensing unit 12 includes a resistor R12, an NMOS transistor N12, and a buffer unit 121. The resistor element R12 is connected between the second external power source VDD2 and the node nd12. The NMOS transistor N12 is connected between the node nd12 and the ground voltage VSS and turned on in response to the second external power source VDD2. The buffer unit 121 includes inverters IV13 and IV14 driven by the second external power source VDD2 and the ground voltage VSS, and buffers a signal of the node nd12 to generate a second power-up signal ( PWRUP2). The resistive element R12 supplies electric charge to the node nd12, and the NMOS transistor N12 emits electric charge of the node nd12. As the level of the second external power supply VDD2 increases, the level of the node nd12 increases when the charge supplied through the resistor R12 is set to be greater than the charge emitted through the NMOS transistor N12. Therefore, the second power-up signal PWRUP2 output from the buffer unit 121 transitions to the logic high level when the second external power supply VDD2 reaches the second target level.

5 is a diagram according to an embodiment of the pumping voltage supply unit 2.

As shown in FIG. 5, the pumping voltage supply unit 2 includes a voltage pump 21 and an initial setting unit 22. The voltage pump 21 receives the first external power source VDD1 and pumps the pumping voltage VPP when the final power-up signal PWRUP_F is enabled at a logic high level. The voltage pump 21 may be implemented by a general voltage pump circuit. The initial setting unit 22 sets the node nd2 at which the pumping voltage VPP is output before the pumping voltage VPP is pumped by the pumping voltage supplying unit 2 to the level of the first external power supply VDD1. That is, the initial setting unit 22 sets the pumping voltage VPP to the level of the first external power supply VDD1 before the pumping voltage VPP is pumped so that the pumping voltage VPP is applied to the first external power supply VDD1. It prevents malfunction caused by being lower than the level.

6 is a diagram according to an embodiment of the control signal generator 3.

As shown in FIG. 6, the control signal generator 3 includes a buffer signal generator 31, a level converter 32, a latch 33, a first setter 34 and a second setter ( 35).

The buffer signal generator 31 includes inverters IV31 and IV32 and a NAND gate ND31 driven by the second external power supply VDD2 and the ground voltage VSS. When the deep power down mode signal DPD is disabled at a logic low level, the buffer signal generator 31 buffers the final power up signal PWRUP_F to generate a buffer signal BF. When the final power-up signal PWRUP_F is enabled at the logic high level in the deep power down mode, the buffer signal BF is driven at the level of the second external power supply VDD2.

The level converting unit 32 converts the level of the buffer signal BF to generate the converted signal CVT. When the buffer signal BF is at the level of the second external power supply VDD2, the conversion signal CVT is converted to the level of the pumping voltage VPP.

The latch unit 33 includes inverters IV33 and IV34 and an NMOS transistor N32 driven by a pumping voltage VPP and a ground voltage VSS. The latch unit 33 latches and buffers the conversion signal CVT to generate the control signal CV. When the conversion signal CVT is at the level of the pumping voltage VPP, the control signal CTR is generated at the level of the pumping voltage VPP.

The first setting unit 34 includes an inverter IV33 and an NMOS transistor N31 driven by a first external power source VDD1 and a ground voltage VSS. The first setting unit 34 receives the first power-up signal PWRUP1 which is disabled at a logic low level before the first external power supply VDD1 reaches the first target level, and turns on the NMOS transistor N31 that is turned on. The conversion signal CVT is set to the level of the ground voltage VSS.

The second setting unit 35 includes an NMOS transistor N33 that is turned on in response to the deep power down mode signal DPD to set the control signal CTR to the level of the ground voltage VSS. The second setting unit 35 sets the control signal CTR to be disabled at the logic low level in the deep power down mode.

In the control signal generator 3 configured as described above, the first external power supply VDD1 reaches the first target level while the second external power supply VDD2 reaches the second target level in a state not in the deep power down mode. When reaching, the control signal CTR driven to the level of the pumping voltage VPP is generated. The driving of the control signal CTR with the pumping voltage VPP is attenuated by the moon turn voltage of the NMOS transistor included in the switch unit 4 so that the level of the internal power supply VDD2T is higher than that of the second external power supply VDD2. This is to reduce the generated low.

7 is a circuit diagram of an embodiment of the level converter 32.

As shown in FIG. 7, the level converter 32 includes a first driver 321 and a second driver 322.

The first driver 321 is connected between the pumping voltage VPP and the node nd33 and is turned on between the PMOS transistor P31, the pumping voltage VPP, and the node nd34 that are turned on in response to the voltage of the node nd32. A PMOS transistor P32 connected and turned on in response to a voltage of a node nd31, a PMOS transistor P33 and a node connected between a node nd33 and a node nd31 and turned on in response to a buffer signal BF. and a PMOS transistor P34 connected between the node nd34 and the node nd32 and turned on in response to an output signal of the inverter IV36. The first driver 321 pumps the node nd32 to which the conversion signal CVT is output by the PMOS transistors P32 and P34 which are turned on when the buffer signal BF is at the level of the second external power supply VDD2. It is driven by the voltage VPP. Meanwhile, the first driver 321 drives the node nd31 to the pumping voltage VPP by the PMOS transistors P31 and P32 turned on when the buffer signal BF is at the level of the ground voltage VSS.

The second driver 322 is connected between the node nd31 and the ground voltage VSS and is connected between the NMOS transistor N34 and the node nd32 and the ground voltage VSS turned on in response to the buffer signal BF. And an NMOS transistor N35 and a second external power source VDD2 and a ground voltage VSS that are turned on in response to an output signal of the inverter IV36 and driven to invert and buffer and output the buffer signal BF. IV36). The second driver 322 drives the node nd31 to the ground voltage VSS by the NMOS transistor N34 which is turned on when the buffer signal BF is at the level of the second external power source VDD2. On the other hand, the first driver 321 supplies the node nd32 to which the conversion signal CVT is output by the NMOS transistor N35 which is turned on when the buffer signal BF is at the level of the ground voltage VSS. ).

The level converting unit 32 configured as described above drives the conversion signal CVT to the pumping voltage VPP when the buffer signal BF is at the level of the second external power supply VDD2, and the buffer signal BF is The conversion signal CVT is driven to the ground voltage VSS at the level of the ground voltage VSS.

8 is a view according to one embodiment of the internal circuit 5.

As shown in FIG. 8, the internal circuit 5 is composed of a ferry region internal circuit 51 and a core region internal circuit 52. As shown in FIG. The ferry area internal circuit 51 operates by receiving the first external power source VDD1 and the second external power source VDD2. The core region internal circuit 52 operates by receiving a first external power supply VDD1 and an internal power supply VDD2T. Here, the core region internal circuit 52 refers to an internal circuit included in the core region where the memory cell is formed, and the ferry region internal circuit 51 refers to an internal circuit included in the ferry region adjacent to the core region. Unlike the ferry region internal circuit 51, the core region internal circuit 52 operates by receiving the internal power supply VDD2T. This is because the internal power supply VDD2T is applied after the first external power supply VDD1 reaches the first target level and the second external power supply VDD2 reaches the second target level, so that the second external power supply VDD2 is applied. This is to prevent a well bias reversal phenomenon generated when the level is higher than the pumping voltage VPP generated from the first external power supply VDD1.

The operation of the semiconductor memory device of the present embodiment described above is as follows.

In the deep power down mode, since the control signal CTR is disabled at the logic low level by the deep power down mode signal DPD disabled at the logic low level, the internal power supply VDD2T supplied to the internal circuit 52 of the core region. This second external power source VDD2 is not driven.

In the non-deep power-down mode, the final power-up is enabled to the logic high level after the first external power supply VDD1 reaches the first target level and the second external power supply VDD2 reaches the second target level. The pumping voltage VPP is pumped by the signal PWRUP_F and supplied to the control signal generation unit 3. The control signal generator 3 buffers the final power-up signal PWRUP_F and converts it to the level of the pumping voltage VPP to generate the control signal CTR. When the control signal CTR is driven at the level of the pumping voltage VPP, the internal power supply VDD2T supplied to the core region internal circuit 52 is driven by the second external power supply VDD2.

In summary, the semiconductor memory device of the present embodiment pumps the pumping voltage VPP after the first external power supply VDD1 reaches the first target level and the second external power supply VDD2 reaches the second target level. do. In this case, the pumping voltage VPP is driven by the first external power source VDD1 even before being pumped, and is generated lower than the level of the first external power source VDD1 to prevent a malfunction. In addition, the internal power supply VDD2T supplied to the core region internal circuit 52 has the first external power supply VDD1 reaching the first target level and the second external power supply VDD2 reaching the second target level. In this case, a well bias reversal phenomenon generated when the second external power supply VDD2 is at a level higher than the pumping voltage VPP generated from the first external power supply VDD1 may be prevented from occurring.

1: power-up signal generation unit 2: pumping voltage supply unit
3: control signal generation unit 4: switch unit
5: internal circuit 11: first sensing unit
12: second detection unit 13: signal synthesis unit
21: voltage pump 22: initial setting section
31: buffer signal generator 32: level converter
33: latch portion 34: first setting portion
35: second setting unit 321: first driving unit
322: second drive unit 51: ferry region internal circuit
52: core area internal circuit

Claims (22)

When the first external power source reaches the first target level and the second external power source reaches the second target level, the pumping voltage generated by pumping from the first external power source is supplied in response to the last power-up signal enabled. A pumping voltage supply unit;
A control signal generator configured to receive the pumping voltage and generate a control signal driven by the pumping voltage when the final power-up signal is enabled; And
And a switch unit which is turned on in response to the control signal to generate an internal power source driven by a second external power source and supply the internal power source to an internal circuit.
Claim 2 has been abandoned upon payment of a set-up fee. The semiconductor memory device of claim 1, wherein the pumping voltage is set at an initial level by the first external power source before being pumped in response to the final power-up signal.
Claim 3 has been abandoned upon payment of a set-up fee. The method of claim 1, wherein the pumping voltage supply unit
A voltage pump for pumping the pumping voltage and outputting the pumped voltage to an internal node when the final power-up signal is enabled; And
And an initial setting unit configured to set the internal node to an initial level by a first external voltage before the final power-up signal is enabled.
Claim 4 has been abandoned upon payment of a setup registration fee. The method of claim 1, wherein the control signal generation unit
A buffer signal generation unit configured to generate a buffer signal by buffering the final power up signal in response to a deep power down mode signal;
A level converting unit converting the level of the buffer signal to generate a converted signal; And
And a latch unit configured to latch the converted signal to generate the control signal.
Claim 5 was abandoned upon payment of a set-up fee. The semiconductor device of claim 4, wherein the deep power down mode signal is enabled when the deep power down mode signal enters a deep power down mode in which generation of an internal voltage including the pumping voltage is stopped while the first and second external power sources are applied. Memory device.
Claim 6 has been abandoned upon payment of a setup registration fee. The semiconductor memory device of claim 4, wherein the level converter is configured to receive the buffer signal having the level of the second external power source and generate the converted signal having the level of the pumping voltage.
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, wherein the level converter
A first driver configured to drive the converted signal to the level of the pumping voltage when the level of the buffer signal is the level of the second external power source; And
And a second driver configured to drive the level of the converted signal to the level of the ground voltage when the level of the buffer signal is the level of the ground voltage.
Claim 8 has been abandoned upon payment of a set-up fee. The semiconductor memory device of claim 4, wherein the control signal generator further comprises a first setter configured to set the converted signal to a disabled state in response to a first external power source.
delete Claim 10 has been abandoned upon payment of a setup registration fee. The method of claim 1, wherein the internal circuit
A core region internal circuit located in a core region where a memory cell is formed and operated by receiving the first external power and the internal power; And
And a ferry region internal circuit positioned in a peripheral region of the core region to operate by receiving the first external power and the second external power.
Claim 11 was abandoned upon payment of a set-up fee. The method of claim 1,
A first detector configured to generate a first power-up signal of level shifting when the first external power source reaches the first target level;
A second detector configured to generate a second power-up signal for level shifting when the second external power source reaches the second target level; And
And a signal synthesizing unit configured to synthesize the levels of the first power up signal and the second power up signal to generate the final power up signal.
In response to the deep power down mode signal, when the first external power reaches the first target level and the second external power reaches the second target level, the buffered final power-up signal is enabled to generate a buffer signal. A buffer signal generator;
A level converting unit converting the level of the buffer signal to generate a converted signal;
A latch unit for latching the converted signal to generate a control signal; And
And a switch unit which is turned on in response to the control signal to generate an internal power source driven by a second external power source and supply the internal power source to an internal circuit.
Claim 13 was abandoned upon payment of a set-up fee. The semiconductor memory device of claim 12, wherein the deep power down mode signal is enabled when the deep power down mode signal enters a deep power down mode in which generation of an internal voltage is stopped while the first and second external power sources are applied.
Claim 14 was abandoned upon payment of a set-up fee. The method of claim 12, wherein the level converting unit receives the buffer signal having the level of the second external power and has a level of a pumping voltage generated by being pumped to a level higher than that of the first and second external power. A semiconductor memory device for generating a converted signal.
Claim 15 was abandoned upon payment of a set-up fee. The method of claim 14, wherein the level conversion unit
A first driver configured to drive the converted signal to the level of the pumping voltage when the level of the buffer signal is the level of the second external power source; And
And a second driver configured to drive the level of the converted signal to the level of the ground voltage when the level of the buffer signal is the level of the ground voltage.
Claim 16 was abandoned upon payment of a set-up fee. The semiconductor memory device of claim 12, further comprising a first setting unit configured to set the converted signal to a disabled state in response to the first external power source.
delete Claim 18 was abandoned when the set registration fee was paid. The method of claim 12,
And a pumping voltage supply unit configured to supply a pumping voltage generated by pumping from the first external power source to the level converter and the latch unit in response to the last power-up signal.
Claim 19 was abandoned upon payment of a set-up fee. 19. The semiconductor memory device of claim 18, wherein the pumping voltage is set at an initial level by the first external power source before being pumped in response to the final power-up signal.
Claim 20 was abandoned when the set registration fee was paid. 19. The method of claim 18, wherein the pumping voltage supply unit
A voltage pump for pumping the pumping voltage and outputting the pumped voltage to an internal node when the final power-up signal is enabled; And
And an initial setting unit configured to set the internal node to an initial level by a first external voltage before the final power-up signal is enabled.
Claim 21 has been abandoned upon payment of a set-up fee. The method of claim 12, wherein the internal circuit
A core region internal circuit located in a core region where a memory cell is formed and operated by receiving the first external power and the internal power; And
And a ferry region internal circuit positioned in a peripheral region of the core region to operate by receiving the first external power and the second external power.
Claim 22 was abandoned upon payment of a set-up fee. The method of claim 12,
A first detector configured to generate a first power-up signal of level shifting when the first external power source reaches the first target level;
A second detector configured to generate a second power-up signal for level shifting when the second external power source reaches the second target level; And
And a signal synthesizing unit configured to synthesize the levels of the first power up signal and the second power up signal to generate the final power up signal.
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