KR102036904B1 - Methods for manufacturing a Array substrate for liquid crystal display - Google Patents

Methods for manufacturing a Array substrate for liquid crystal display Download PDF

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KR102036904B1
KR102036904B1 KR1020120130519A KR20120130519A KR102036904B1 KR 102036904 B1 KR102036904 B1 KR 102036904B1 KR 1020120130519 A KR1020120130519 A KR 1020120130519A KR 20120130519 A KR20120130519 A KR 20120130519A KR 102036904 B1 KR102036904 B1 KR 102036904B1
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South Korea
Prior art keywords
silicon oxide
liquid crystal
oxide film
crystal display
array substrate
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KR1020120130519A
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Korean (ko)
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KR20140063308A (en
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이준희
손정호
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엘지디스플레이 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

According to an embodiment of the present invention, the method includes: (A) injecting a substrate 215 having a metal layer, a silicon oxide film, and a photoresist film having a contact hole pattern to be formed on the silicon oxide film 213 into a chamber; (B) forming a contact hole in the silicon oxide film by dry etching the silicon oxide film exposed to the barrier by generating plasma using a process gas including NF 3 and Ar; (C) generating a plasma using a process gas containing NF 3 , O 2 to remove by-products formed around the photoresist film and the contact hole; and a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: do.

Description

Method for manufacturing an array substrate for a liquid crystal display device {Methods for manufacturing a Array substrate for liquid crystal display}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an array substrate for a liquid crystal display device, and in particular, removes by-products generated during a process of patterning a silicon oxide film during a process of forming a TFT (hereinafter, referred to as an oxide semiconductor TFT) made of an oxide semiconductor. It is about how to.

In general, a liquid crystal display is a device for displaying a desired image by adjusting light transmittance of liquid crystal cells arranged in a matrix form according to image signal information. The display panel displays an image.

The liquid crystal display panel includes an array substrate in which a plurality of thin film transistors (TFTs) are integrated, a color filter substrate bonded to the array substrate to realize color, and a liquid crystal injected between the substrates. In a liquid crystal display panel, an electrical signal is input to each liquid crystal cell through each data line and gate line, and TFTs disposed in each liquid crystal cell are turned on or off in accordance with this signal to drive a driving voltage to each liquid crystal cell. Act to authorize or block.

The TFT includes a gate electrode, an active layer, a source electrode, and a drain electrode. In general, a TFT mainly uses an active layer made of Si. Nowadays, researches on oxide semiconductor TFTs in which active layers are composed of TFTs are being actively conducted, and oxide semiconductors can maintain their characteristics even at a very thin nanometer level, thereby overcoming the limitations of Si semiconductors. It is attracting attention as a semiconductor.

1 shows a schematic cross-sectional view of an oxide semiconductor TFT constructed in a top gate manner.

The TFT 7 overlaps the gate electrode 15 formed on the substrate 11 and the gate electrode 15 over the gate insulating film 11 and forms a channel between the source electrode 25 and the drain electrode 35. (37) and an etch stopper (ES) to protect the semiconductor layer 37 from the etching liquid flowing through the separated portion between the source electrode 25 and the drain electrode 35.

On the other hand, the gate electrode 15 is covered with the gate insulating film 21, and the source electrode 25 and the drain electrode 35 are covered with the protective film 41.

Here, the semiconductor layer 37 is composed of an oxide, and generally includes IGZO (InGaZnO 4 ). This IGZO (InGaZnO 4 ) is advantageous in that it can be formed by a deposition method using a conventional Si-based TF T such as sputtering.

Insulating layers such as the gate insulating film 21 and the protective film 41 are made of a silicon oxide film because the nitride film SiNx affects the reliability of the oxide semiconductor when the semiconductor layer 37 is made of an oxide semiconductor.

On the other hand, when connecting wires existing in different layers, the two wires are connected through contact holes. For example, as illustrated in FIG. 1, the pixel electrode 51 and the drain electrode 35 of the TFT that are layered with the passivation layer 41 therebetween are connected to each other through a contact hole CH formed in the passivation layer 41. do.

The contact hole CH is formed by dry etching the protective film 41 as a barrier by the photoresist PR. The protective film 41 is made of a silicon oxide film and needs to be exposed to a high density plasma.

However, when exposed to high-density plasma, as shown in FIG. 2, the modified photoresist and the etched silicon oxide meet and have a problem in that a by-product (original) is formed and deposited again around the contact hole.

The present invention has been devised in such a background and aims at removing by-products generated in the production of oxide semiconductor TFTs.

In one embodiment of the present invention, (A) a step of injecting a substrate 215, a metal layer, a silicon oxide film, a photoresist film having a contact hole pattern to be formed on the silicon oxide film 213 sequentially stacked; (B) forming a contact hole in the silicon oxide film by dry etching the silicon oxide film exposed to the barrier by generating a plasma by using a first process gas including NF 3 and Ar; (C) generating a plasma by using a second process gas including NF 3 and O 2 to remove by-products formed around the photoresist film and the contact hole; and a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: Initiate.

The first process gas includes NF 3 3400-3600 (sccm), Ar 650-750 (sccm), and in the step (B), when the process time is 104 seconds, the pressure in the chamber is 10Mtorr, the source power Is 40 (kW) and the bias power is 40 (kW).

The second process gas includes NF 3 100 (sccm) and O 2 2000 (sccm). In the step (C), when the process time is 10 seconds, the pressure in the chamber is 10 Mtorr, and the source power is 40 ( kW) and the bias power is 40 (kW).

According to an embodiment of the present invention, even though the silicon oxide film used as the insulating film in the oxide semiconductor TFT is exposed to the high density plasma to produce the by-product, the by-product can be removed to remove the by-product.

1 is a view showing a schematic cross-sectional view of an oxide semiconductor TFT configured by a top gate method.
FIG. 2 is a SEM photograph showing the appearance of by-products formed around the contact hole by exposure to a high density plasma.
3 is a view for explaining a schematic configuration of an inductively coupled plasma processing apparatus.
4 is a flowchart illustrating a method of removing by-products according to an embodiment of the present invention.
FIG. 5 is a process diagram schematically showing the removal method of FIG. 4.
6 is a SEM photograph showing a state in which a contact hole is formed in a silicon oxide film by a first process gas.
FIG. 7 is a SEM photograph showing the removal of photoresist and by-products by the second process gas.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The plasma processing apparatus may be divided into a capacitively coupled plasma method, an inductively coupled plasma method, and an electron resonance plasma method according to the plasma forming method, and the present invention may be achieved in an inductively coupled plasma method in which a high density plasma is formed.

3 illustrates a schematic configuration of an inductively coupled plasma processing apparatus. The inductively coupled plasma processing apparatus includes an antenna and generates a high density plasma by an induction electric field formed by applying high frequency power to the antenna.

In FIG. 3, the inductively coupled plasma processing apparatus includes a chamber 11, a susceptor 13 positioned inside the chamber 11, on which a substrate s is seated, and a lead located above the chamber 11. 15). The lead 15 includes a lead frame 151 having a plurality of rectangular frames, a plurality of windows 153 provided in each of the plurality of rectangular frames, and an inductively coupled plasma antenna 153 provided on the window 153. do. One side of the inductively coupled plasma antenna 155 is connected with a first power supply unit 19 for supplying high frequency power, and a second power supply unit 18 for supplying bias power is connected to the susceptor 13. Matching units 171 and 173 are positioned between the inductively coupled plasma antenna 155 and the first power supply unit 19 and between the susceptor 13 and the second power supply unit 18 to transfer RF power through impedance matching. Increase the efficiency

In addition, the inductively coupled plasma processing apparatus further includes a pumping unit 111 and a gas supply unit 112. The pumping unit 111 pumps the internal pressure of the chamber 11 to be 10 Mtorr or less, and the gas supply unit 112 injects the process gas into the chamber 11.

 Hereinafter, a method of removing the byproduct around the contact hole formed in the silicon oxide film with the inductively coupled plasma processing apparatus configured as described above will be described with reference to FIGS. 4 and 5. 4 is a flowchart illustrating a method of removing by-products according to an embodiment of the present invention, and FIG. 5 is a process diagram schematically showing this.

In step S11, the substrate 215 in which the metal layer 211, the silicon oxide film 213 covering the first metal layer, and the photoresist film 215 having a contact hole pattern to be formed on the silicon oxide film 213 are sequentially stacked. To the inside of the chamber 11 (Fig. 5 (a)).

In step S12, the first process gas including NF 3 3400-3600 (sccm) and Ar 650-750 (sccm) is supplied into the chamber 11 through the gas supply unit 112 to barrier the photoresist film 215. The silicon oxide film 213 exposed by the dry etching is dry etched to form a contact hole CH in the silicon oxide film 213 (FIG. 5B). Preferably, the first process gas includes Ar 700 (sccm) when NF 3 3500 (sccm).

In this step, the chamber 11 pressure is 9-11 (Mtorrr), the process time is 100-110 seconds, the source power applied to the inductively coupled plasma antenna 155 is 37-42 (kW), and the susceptor The bias power applied to (13) is also 37-42 (kW). Preferably, when the process time is 104 seconds, the chamber 11 pressure is 10 (Mtorrr), the source power applied to the inductively coupled plasma antenna 155 is 40 (kW), the bar is applied to the susceptor 13 Earth power is also 40 kW.

6 is a scanning electron microscope (SEM) photograph in which a contact hole CH is formed in the silicon oxide layer 213 according to step S12. As shown in FIG. 6, when the silicon oxide film 213 is exposed to a high density plasma, the modified photoresist and the etched silicon oxide may meet to form a by-product and be deposited again around the contact hole CH.

In operation S13, a second process gas including NF 3 95-105 (sccm) and O 2 1950-2050 (sccm) is supplied into the chamber 11 through the gas supply unit 112 to provide a photoresist film 215. Dry etch by-products. Preferably, the second process gas comprises O 2 2000 (sccm) when NF 3 100 (sccm).

The process parameter of this step (S13), the chamber 11 pressure is 9-11 (Mtorrr), the process time is 8-12 seconds, the source power applied to the inductively coupled plasma antenna 155 is 37-42 ( kW) and the bias power applied to the susceptor 13 is also 37-42 (kW). Preferably, when the process time is 10 seconds, the chamber 11 pressure is 10 (Mtorr), the source power 40 (kW), the bias power 40 (kW).

7 is a scanning electron microscope (SEM) image after the step S13. As can be seen from this photo, it can be seen that the by-products that existed around the contact hole (CH) were removed cleanly.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

(A) injecting a substrate in which a metal layer, a silicon oxide film which is a nonmetal oxide layer, and a photoresist film having a contact hole pattern to be formed on the silicon oxide film, are sequentially stacked;
(B) forming a contact hole in the silicon oxide film by dry etching the silicon oxide film exposed to the barrier by generating a plasma by using a first process gas including NF 3 and Ar;
(C) generating a plasma using a second process gas including NF 3 and O 2 to remove by-products formed around the photoresist film and the contact hole;
Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 1,
The first process gas comprises NF 3 3400-3600 (sccm), Ar 650-750 (sccm) manufacturing method of an array substrate for a liquid crystal display device. The method of claim 2,
In the step (B), when the process time is 104 seconds, the pressure of the chamber is 10Mtorr, the source power is 40 (kW), the bias power is 40 (kW) manufacturing method of the array substrate for a liquid crystal display device. The method of claim 1,
And the second process gas comprises NF 3 100 (sccm) and O 2 2000 (sccm). The method of claim 4, wherein
In the step (C), when the process time is 10 seconds, the pressure of the chamber is 10Mtorr, the source power is 40 (kW), the bias power is 40 (kW) manufacturing method of an array substrate for a liquid crystal display device. The method of claim 1,
The step (C) is a step of removing the dispersion formed by the modification of the modified photoresist film material and the etched silicon oxide film material, the manufacturing method of the array substrate for a liquid crystal display device.
KR1020120130519A 2012-11-16 2012-11-16 Methods for manufacturing a Array substrate for liquid crystal display KR102036904B1 (en)

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KR102036904B1 true KR102036904B1 (en) 2019-10-25

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266609A (en) * 2006-03-28 2007-10-11 Tokyo Electron Ltd Method of removing residues from substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080064611A (en) * 2007-01-05 2008-07-09 삼성전자주식회사 Etching method of metal oxide on metal layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266609A (en) * 2006-03-28 2007-10-11 Tokyo Electron Ltd Method of removing residues from substrate

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