KR102031272B1 - Memoryless Common-Mode Insensitive and Low-Pulling VCOs - Google Patents

Abstract

A voltage controlled oscillator (VCO) is disclosed. The VCO includes an active device. The VCO includes an active device, the active device comprising an n-type transistor having a drain, a gate, and a bulk; A p-type transistor having a drain, a gate, and a bulk; A first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor; A second capacitor coupled between the drain of the n-type transistor and the drain of the p-type transistor; And a third capacitor coupled between the bulk of the n-type transistor and the bulk of the p-type transistor, wherein the n-type transistor and the p-type transistor share a common source. The VCO includes a tuning block coupled to the common source to form a common gate amplifier and includes at least one tuning element coupled to the active device to change the overall capacitance of the VCO.

Description

Memoryless Common-Mode Insensitive and Low-Pulling VCOs

Cross Reference to Related Applications

This application is part of a U.S. patent application (14 / 745,261) filed June 19, 2015, entitled "ACTIVE DEVICE WHICH HAS A HIGH BREAKDOWN VOLTAGE, IS MEMORY-LESS, TRAPS EVEN HARMONIC SIGNALS AND CIRCUITS USED THEREWITH." And US Provisional Application (62 / 100,397), filed January 6, 2015, entitled "VERY LOW PHASE NOISE, MEMORYLESS COMMON-MODE INSENSITIVE, AND LOW PULLING VCO WITH CAPACITOR BANKS AS TUNING." (e) Allegedly in accordance with the provisions, both US applications are incorporated herein by reference in their entirety as a reference to the present invention.

In general, the invention relates to wireless devices and, more particularly, to voltage controlled oscillators used in such devices.

Wireless products are being used in various environments, such as mobile (eg, cellular and Wi-Fi handsets) or non-mobile (eg, access points and routers for Wi-Fi). A voltage-controlled oscillator or VCO is an electronic oscillator whose oscillation frequency is controlled by a voltage input. The input voltage applied determines the instantaneous oscillation frequency. As a result, modulating the signals applied to the control input can cause frequency modulation (FM) or phase modulation (PM). The VCO may also be part of a phase-locked loop. The VCO can be used as an amplifier in these products to amplify received or transmitted signals. As the wireless product market evolves, the need for more bandwidth and more data is growing day by day across mobile and non-mobile networks, increasing the demand for high efficiency and linearity. Thus, communicating such data over these networks is becoming increasingly difficult. For example, as networks evolve, bandwidth increases and at the same time signal integration becomes more dense, such as the 802.11ax standard for Wi-Fi applications. As a result, the in-band and out of band noise of the VCO becomes very important. In addition, VCO pulling is a very important issue. This is especially important if you have a high-power amplifier for integration. In addition, existing VCO architectures rely on buffers to center the output of the core VCO before driving the inverter chain following the core. These buffers consume most of the power and are another source of noise and failure problems.

VCO tuning range is another problem. The VCO tuning range is limited by the noise and parasitic components of the capacitor banks.

The device and circuit according to the invention solve these problems.

A voltage controlled oscillator (VCO) and a circuit used therewith are disclosed. In a first aspect, the VCO includes an active device. The VCO includes an active device, which includes an n-type transistor having a drain, a gate and a bulk and a p-type transistor having a drain, a gate and a bulk. The n-type transistor and the p-type transistor share a common source.

The active device also includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor; A second capacitor coupled between the drain of the n-type transistor and the drain of the p-type transistor; And a third capacitor coupled between the bulk of the n-type transistor and the bulk of the p-type transistor.

A differential voltage controlled oscillator (VCO) is also disclosed. The differential VCO includes first and second active devices. Each of the first and second active devices also includes an n-type transistor having a drain, a gate, and a bulk. Each of the first and second active devices also includes a nine-type transistor having a drain, a gate, and a bulk. The n-type transistor and the p-type transistor share a common source. Each of the first and second active devices also includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor. Each of the first and second active devices also includes a second capacitor coupled between the drain of the n-type transistor and the drain of the p-type transistor. Each of the first and second active devices also includes a third capacitor coupled between the bulk of the n-type transistor and the bulk of the p-type transistor. The differential VCO also includes a fourth capacitor coupled between the bulk of the n-type transistor of the first active device and the shared source of the second active device. The differential VCO also includes a fifth capacitor coupled between the bulk of the p-type transistor of the first active device and the shared source of the second active device. The differential VCO also includes a sixth capacitor coupled between the bulk of the n-type transistor of the second active device and the shared source of the first active device. The differential VCO also includes a seventh capacitor coupled between the bulk of the p-type transistor of the second active device and the shared source of the first active device. The differential VCO also includes a tuning block coupled to the common source to form a common gate amplifier. The differential VCO also includes at least one first tuning element coupled between the drain of the n-type transistor of the first active device and the drain of the n-type transistor of the second active device. The differential VCO also includes at least one second tuning element coupled between the sources of n-type and p-type transistors of the first active device and the sources of n-type and p-type transistors of the second active device. . Finally, the differential VCO also includes at least one third tuning element coupled between the drain of the p-type transistor of the first active device and the drain of the p-type transistor of the second active device. Here, the differential VCO has a high breakdown voltage, memory-less, very low close in and far phase noise, and supply and ground disturbance. Because of its very low sensitivity to), it is low pulling and captures even harmonic signals.

The VCO includes a tuning block coupled to a common source to form a common gate amplifier and includes at least one tuning element coupled to the active device to change the overall capacitance of the VCO. VCO has high breakdown voltage, is memory-less, has very low close-in and wave phase noise, and has very low sensitivity to power and ground disturbances, so it is low pulling and captures even harmonic signals.

The VCO has a high breakdown voltage because each of the n-type and p-type devices sees a fraction of the total supply voltage, and is memory-less because the gate capacitance and n-type and This is because bulk capacitors that combine p-type bulk capture common mode signals coupled to the critical nodes of the devices and capture even harmonic signals. This combination of n-type and p-type also distinguishes even and odd signals generated during class AB or B or C operation.

The system and method according to the present invention provides an amplifier circuit, which can be combined with a transformer to obtain increased gain and positive feedback for voltage controlled oscillator (VCO) applications. The resulting device does not require buffers and memory because the output signal can be removed from each common source centered with respect to the supply, thus being smaller in size and less power than conventional VCOs. Can be used.

1A is a schematic diagram of an active device used in a voltage controlled oscillator according to the present invention.
FIG. 1B is a block diagram of the active device shown in FIG. 1A.
1C is a schematic diagram of a differential active device used in a voltage controlled oscillator in accordance with the present invention.
1D is a schematic diagram of a differential active device including a capacitive tuning element for use in a voltage controlled oscillator in accordance with the present invention.
FIG. 1E is a block diagram of the differential active device shown in FIG. 1D.
2a is a first embodiment of a tuning block according to the invention.
2b is a second embodiment of a tuning block according to the invention.
3A is a block diagram of a common gate amplifier in accordance with the present invention.
3B is a block diagram of a combined common gate and common source amplifier in accordance with the present invention.
4A is a block diagram of a first embodiment of a differential common gate amplifier in accordance with the present invention.
4B is a block diagram of a second embodiment of a differential common gate amplifier in accordance with the present invention.
4C is a block diagram of a differentially coupled common gate and common source amplifier in accordance with the present invention.
4D is a block diagram of one embodiment of a single ended voltage controlled oscillator (VCO) in accordance with the present invention.
4E is a block diagram of one embodiment of a differential VCO arranged in a common-gate, common-source configuration in accordance with the present invention.
4F is a block diagram of one embodiment of a cascaded VCO of CG-CS in accordance with the present invention.
4G is a block diagram of one embodiment of a differential VCO arranged in a common-gate configuration in accordance with the present invention.
4H is a block diagram of one embodiment of a cascaded VCO of CG according to the present invention.
4I is a block diagram of one embodiment of a cascaded VCO of a CG and CG-CS combination according to the present invention.
5 is a diagram of two differential common gate active devices connected to inductive differential tuning blocks in accordance with the present invention.
6 is a diagram of three common gate differential active devices connected to inductive differential tuning blocks in accordance with the present invention.
7 is a diagram of four differential common gate active devices connected to inductive differential tuning blocks in accordance with the present invention.
8 is a diagram illustrating a case where a drain current is added before a loop in a VCO according to the present invention.
9 is a diagram illustrating a case where a drain current is added after a loop in a VCO according to the present invention.

In general, the present invention relates to wireless devices, and more particularly to voltage controlled oscillators used in such devices. The following description is presented to enable one skilled in the art to make and use the invention and is provided in the context of the present application and its requirements. Various modifications to the preferred embodiments and general principles and features described herein will be apparent to those skilled in the art. Thus, the present invention is not limited to the illustrated embodiments, but is to be accorded the widest scope consistent with the principles and features described herein.

1A is a schematic diagram of an active device 100 used in a voltage controlled oscillator in accordance with the present invention. Examples of use within the active device and amplifier circuits include "ACTIVE DEVICE WHICH HAS A HIGH BREAKDOWN VOLTAGE, IS MEMORY-LESS, TRAPS EVEN HARMONIC SIGNALS AND CIRCUITS USED, which are pending US patent applications and are owned by the assignee of the present application. The US application filed "THE REWITH" (filed June 19, 2015). The active device 100 includes an n-type transistor 102 including a gate gn, a drain dn, and a bulk bn and a p-type transistor including a gate gp, a drain dp, and a bulk bp. 104. The n-type transistor 102 and the p-type transistor 104 share a common source. The active device 100 includes a first capacitor 106 connected between gn and gp, and a third capacitor 110 connected between bn and bp, connected between dn and dp. The active device 100 has a high breakdown voltage due to four terminals (gate, drain bulk and source) and is memory-less and even harmonic signals when used with certain amplifiers, such as a class AB amplifier. captures even harmonic signals.

FIG. 1B is a block diagram of the active device 100 shown in FIG. 1A. The n-type transistor 102 may be an NPN bipolar or any other active device using gallium arsenide (GaAs). The p-type transistor 104 may be any other active complementary device using PNP bipolar or gallium arsenide (GaAs). The n-type transistor 102 may be further protected by a cascade NMOS circuit. The p-type transistor 104 may be further protected by a cascaded PMOS circuit. Capacitor 106 may be a variable capacitor and may have a series resistor and / or a series inductor, all of which may be variable. Capacitor 106 may be further divided into N capacitors with arbitrary series elements. Capacitor 108 may be a variable capacitor and may have a series resistor and / or series inductor, both of which may be variable. Capacitor 108 may be further divided into N capacitors with arbitrary series elements. Capacitor 110 may be a variable capacitor and may have a series resistor and / or a series inductor, all of which may be variable. Capacitor 110 may be further divided into N capacitors with arbitrary series elements.

More capacitors can be coupled between dn and gn, between dn and gp, between dp and gp, and between dp and gn (parasitic or non-parasitic). Such capacitors may be variable or may have passive or active elements in series, such as inductors, resistors, transformers, and the like. Node gp may be connected to a bias network. Such a bias network may include passives such as resistors, capacitors, inductors, transformers, and combinations thereof. The bias may also include any active elements.

If cascade transistors are used for both n-type and p-type or either, additional capacitors may be needed to connect the cascade n-type drain to the cascade p-type drain, similar to capacitor 110. Also, a capacitor that connects cascade n-type bulk to cascade p-type bulk may be similar to capacitor 108. Also, similar to capacitor 106, a capacitor can be coupled from the cascade n-type gate to the cascade p-type gate.

1C is a schematic diagram of a differential active device 150 used in a voltage controlled oscillator in accordance with the present invention. The differential active device 150 includes first and second active devices 100 connected in a differential manner. The differential active device includes capacitors 190 and 192 in both active devices 100, which are connected to the source from the bulk of each of the transistors 102 and 104. Capacitors 190 and 192 improve linearity, stability, and magnetic gain at the high frequencies of common gate active device 150. Capacitor 106 connecting the common gates of the n-type devices and the common gates of the p-type devices is powered, grounded, and any common from self-generated even harmonics (by VCO or amplifiers belonging to classes AB, B, C). The mode signal can be captured, thus improving the problems associated with VCO pooling and memory effects.

Capacitor 108, which connects the bulk of the n-type device to the bulk of the p-type device, provides a path for any even harmonics generated by the AB, B, C, ... class operation of the VCO or amplifier. In addition, providing filtering from any power or ground noise to any bulk node improves problems associated with VCO pooling or memory effects.

1D is a schematic diagram of a differential active device 151 including capacitive tuning elements 194a, 194b, 196 used in a voltage controlled oscillator in accordance with the present invention. Differential active device 151 includes those similar to FIG. 1C. Tuning elements 194a and 194b are coupled between the drains of active devices 100 to provide coarse tuning adjustment for device 151. Tuning element 196 is coupled between sources of active devices 100 to provide fine tuning adjustment for device 151. Tuning elements 194a, 194b and 196 are used to change the effective capacitance of the device 151 (including any parasitic capacitance that is not shown but is apparent). It can also change the center frequency of the entire VCO structure. The tuning element 194a may be a variable capacitor and may have a series resistor and / or a series inductor, all of which may be variable. Tuning element 194a may be further divided into N capacitors with arbitrary series elements. The tuning element 194b may be a variable capacitor and may have a series resistor and / or a series inductor, all of which may be variable. Tuning element 194b may be further divided into N capacitors with arbitrary series elements. The tuning element 110 may be a variable capacitor and may have a series resistor and / or a series inductor, all of which may be variable. Tuning element 110 may be further divided into N capacitors with arbitrary series elements.

FIG. 1E is a block diagram of the differential active device shown in FIG. 1D. Similar to FIG. 1A, in each of the active devices, n-type transistor 102 may be an NPN bipolar or any other active device using gallium arsenide (GaAs). The p-type transistor 104 may be any other active complementary device using PNP bipolar or gallium arsenide (GaAs). The n-type transistor 102 may be further protected by cascaded NMOS or NPN circuits. The p-type transistor 104 may be further protected by a cascaded PMOS or PNP circuit. Capacitor 106 may be a variable capacitor and may have a series resistor and / or a series inductor, all of which may be variable. Capacitor 106 may be further divided into N capacitors with arbitrary series elements. Capacitor 108 may be a variable capacitor and may have a series resistor and / or series inductor, both of which may be variable. Capacitor 108 may be further divided into N capacitors with arbitrary series elements. Capacitor 110 may be a variable capacitor and may have a series resistor and / or a series inductor, all of which may be variable. Capacitor 110 may be further divided into N capacitors with arbitrary series elements.

More capacitors can be coupled between dn and gn, between dn and gp, between dp and gp, and between dp and gn (parasitic or non-parasitic). Such capacitors may be variable or may have passive or active elements in series, such as inductors, resistors, transformers, and the like. Node gp may be connected to a bias network. Such a bias network may include passives such as resistors, capacitors, inductors, transformers, and combinations thereof. The bias may also include any active elements.

When using cascade transistors for both n-type and p-type or either, additional capacitors may be needed to connect the cascade n-type drain to the cascade p-type drain, similar to capacitor 110. Also, a capacitor that connects cascade n-type bulk to cascade p-type bulk may be similar to capacitor 108. Also, similar to capacitor 106, a capacitor can be coupled from the cascade n-type gate to the cascade p-type gate.

If the active device 100 of FIG. 1A or the differential active device 150 or 151 of FIGS. 1C and 1D are driven in a class AB or B or C or D or any other class except Class A, respectively, Device 151 generates even and odd harmonic output currents flowing through nodes dn and dp. The active device 151 can distinguish even and odd harmonics by generating current flow in similar directions at nodes dn and dp in the case of odd harmonics such as the main signal or third harmonic. However, active device 100 will generate current in opposite directions at nodes dn and dp for even harmonics such as 2nd, 4th, 5th, etc. In addition, the filtering operation caused by the capacitors 110, 108 and 106 will affect the magnitude of even harmonics flowing through the dn and dp nodes.

2A is a first embodiment of a tuning block 200 according to the present invention. The single ended tuning block 200 includes two inputs dn and dp, one output s, a voltage supply (vdd) and ground (gnd). The input signals in the form of current may be provided to nodes dn and dp as l_in_n and l_in_p, respectively. Tuning block 200, which may include, but is not limited to, all or some combinations of passive elements, inductors, capacitors, resistors, and transformers, receives l_in_n and l_in_p under the conditions l_s> l_in_n + l_in_p and nodes It has the function of providing the output current l_s at S. The tuning block 200 is used to provide a linear output signal regardless of power. The combination of the tuning block 200 and the active device 100 forms a common gate amplifier.

3A is a block diagram of a single-ended common gate amplifier in accordance with the present invention. The common gate amplifier includes an active device 100 coupled to the tuning block 200. In this embodiment, the current l_s from the tuning block 200 is provided to the source connection S of the active device 100. Due to the common gate operation of the device 100, the current l_s will be split and part of it is directed to dn as output current l_out_n and the other part is directed to dp as output current l_out_p. Gates gn and gp of active device 100 are coupled to bias lines (no signal is applied to gn and gp). Bulk nodes, bn and bp are also coupled to the respective bias lines.

When the active device 100 operates in class AB, B, C, D, and F modes, different even and odd harmonic currents are generated inside the active device 100. These currents are directed towards dn and dp. For even harmonics, such as AM (amplitude modulation) current and second harmonic, the direction of current flow through dn and dp is reversed. However, for odd harmonics, such as the main signal current and third harmonic, the directions of the output currents through dn and dp are the same.

2B is a second embodiment of a tuning block 200 'in accordance with the present invention. The single ended tuning block 200 'includes two inputs dn and dp, three outputs s, gn and gp. The single ended tuning block 200 'has a power supply vvd and ground gnd. The input signal in the form of current enters nodes dn and dp as l_in_n and l_in_p, respectively. Tuning block 200 ', which may include, but is not limited to, a combination of all or a portion of passive elements, inductors, capacitors, resistors, and transformers, receives l_in_n and l_in_p under the condition l_s> l_in_n + l_in_p and then the node. It has the function of providing the output current l_s at S. Output gp and gn are voltages, which will drive nodes gn and gp of active device 100. As shown in FIG. 3B, the common-gate / common source amplifier operation is obtained by coupling the tuning block 200 ′ with the active device 100.

Also, the tuning block 200 ′ may transmit only the gate information gn and gp and may not transmit information in the S node. In this case, the S node can be grounded or connected to any passive or active device such as a resistor, capacitor, inductor, transformer, or both. In this particular example, the combination of tuning block 200'and active device 100 forms a common-source amplifier.

3B is a block diagram of a combined common gate and common source amplifier of the single-ended form according to the present invention. The common gate and common source amplifier include an active device 100 coupled to the tuning block 200 ′. In this embodiment, the current l_s from the tuning block 200 'is provided to the source connection S of the active device 100. Due to the device's common gate operation for any current input to node s, current l_s will be split and part of it is directed to dn as output current l_out_n and part to dp as output current l_out_p. Gates gn and gp of active device 100 are connected to a bias line and driven by output nodes gn and gp of the tuning block. In addition, the bulk nodes bn and bp are connected to respective bias lines. Nodes gn and gp may be further connected to respective biases separated from the main signal.

4A is a block diagram of a first embodiment of a differential common gate amplifier 400 in accordance with the present invention. Amplifier 400 includes differential tuning block 200 coupled to first and second active devices 151. The differential tuning block 200 includes four inputs dn_in +, dp_in +, dn_in-, dp_in- and two outputs S + and S-. A power supply vvd and ground gnd are provided. Input signals in the form of current are input to nodes dn_in +, dp_in +, dn_in-, dp_in- as l_in_n +, l_in_p + and l_in_n- and l_in_p-, respectively. Tuning block 200, which may include, but is not limited to, passive components, inductors, capacitors, resistors, and / or combinations of transformers, may include l_s +> (l_in_n +) + (l_in_p +) and l_s-> (l_in_n-) + ( Under the condition l_in_p-), it has the function of receiving l_in_n +, l_in_p + and l_in_n-, l_in_p- and processing them to output currents l_s + and l_s- at nodes S + and S-, respectively.

In this embodiment, the current l_s from the tuning block 200 is provided to the source connection S of the active device 151+. Due to the common gate operation of the device 151+, the current l_s will be split, part of which is directed to dn as the output current l_out_n and the other part to dp as the output current l_out_p. Gates gn and gp of the active device are connected to bias lines (no signal is applied to gn and gp). In addition, bulk nodes bn and bp are connected to respective bias lines.

Similarly, in this embodiment, the current l_s from the tuning block 200 is provided to the source connection S of the active device 151-. Due to the common gate operation of the device 151-, current l_s will be split, part of which is directed to dn as output current l_out_n, and part of which is directed to dp as output current l_out_p. Gates gn and gp of the active device are connected to bias lines (no signal is applied to gn and gp). In addition, bulk nodes bn and bp are connected to respective bias lines.

Any number of capacitors or variable capacitors may be connected between the + and − nodes of the inputs and the tuning block 200. In addition, any number of capacitors or variable capacitors may be connected between the + and − nodes of the inputs, outputs, gates, bulks, and may be connected to the inputs and outputs of the active device 151+ and the active device 151-. have. For example, cross capacitors or variable capacitors include dn + and dn-; dp + and dp-; dn- and dp +; may be linked between dn + and dp− and / or any combination thereof. In addition, these capacitors or variable capacitors may include series resistors or series inductance or parallel resistors or parallel inductors that do not affect or alter the present invention.

4B is a block diagram of a second embodiment of a differential common gate amplifier in accordance with the present invention. Amplifier 400 includes differential tuning block 200 coupled to first and second active devices 151. The differential tuning block 200 includes four inputs dn_in +, dp_in +, dn_in-, dp_in- and two outputs S + and S-. A power supply vvd and ground gnd are provided. Input signals in the form of current are input to nodes dn_in +, dp_in +, dn_in-, dp_in- as l_in_n +, l_in_p + and l_in_n- and l_in_p-, respectively. The power source vvd is on the left side and ground gnd is on the right side. Tuning block 200, which may include, but is not limited to, passive components, inductors, capacitors, resistors, and / or combinations of transformers, may include l_s +> (l_in_n +) + (l_in_p +) and l_s-> (l_in_n-) + ( Under the condition l_in_p-), it has the function of receiving l_in_n +, l_in_p + and l_in_n-, l_in_p- and processing them to output currents l_s + and l_s- at nodes S + and S-, respectively.

In this embodiment, the current l_s from the tuning block 200 is provided to the source connection S of the active device 151+. Due to the common gate operation of the device 151+, the current l_s will be split, part of which is directed to dn as the output current l_out_n and the other part to dp as the output current l_out_p. Gates gn and gp of the active device are connected to bias lines forming a virtual ground between + and-(no differential signal is applied to gn and gp). Bulk nodes, bn and bp are also connected to respective bias lines.

Similarly, in this embodiment, the current l_s from the tuning block 200 is provided to the source connection S of the active device 151-. Due to the common gate operation of the device 151-, current l_s will be split, a portion of which is directed to dn as output current l_out_n and another portion to dp as output current l_out_p. Gate gn- is connected to gate gn + to form a virtual ground, which shares a common bias voltage vbias_n. Similarly, gp- and gp + are connected together to form a virtual ground and share a common bias voltage bias_p. Bulk nodes bn- and bp- are also connected to their respective bias lines.

Any number of capacitors or variable capacitors may be connected between the + and − nodes of the inputs and outputs of the tuning block 200. Likewise, any number of capacitors or variable capacitors may be coupled between the + and − nodes of the input and outputs, gates, bulks and sources of the active device 151+ and the active device 151−. For example, cross capacitors or variable capacitors include dn + and dn-; dp + and dp-; dn- and dp +; may be linked between dn + and dp− and / or any combination thereof. In addition, these capacitors or variable capacitors may include series resistors or series inductance or parallel resistors or parallel inductors that do not affect or alter the present invention.

4C is a block diagram of an embodiment of a differential coupled common gate and common source amplifier in accordance with the present invention. Amplifier 400 includes differential tuning block 200 coupled to first and second active devices 151. The differential tuning block 200 includes four inputs n +, p +, n-, p- and six outputs S +, S-, gn +, gn-, gp + and gp-. Power supplies vdd and gnd are also provided for the necessary biasing of all active devices supplying nodes dn +, dn-, dp + and dp-.

The input signals are in the form of currents and are provided to nodes n +, p + and n-, p- as l_in_n +, l_in_p + and l_in_n- and l_in_p- respectively. Tuning block 200, which may include, but is not limited to, all or some combinations of passive components such as inductors, capacitors, resistors, and transformers, includes l_s +> (l_in_n +) + (l_in_p +) and l_s-> (l_in_n-) + Under the condition of (l_in_p-), it has the function of receiving l_in_n +, l_in_p +, l_in_n- and l_in_p- and processing them to output to l_s + and l_s- at nodes S + and S-, respectively.

The other four output nodes of tuning block 200 are connected to the positive and negative n-type and p-type gates of active device 151+ and active device 151-, respectively, to form a differential common gate-common source amplifier. .

Current l_s + is provided to active device 151+ source connection S. Due to the common gate operation of the device, the current l_s + will be split, partly directed to dn + as the output current l_out_n + and the other part to dp + as the output current l_out_p +. Gates gn + and gp + of active device 151+ are coupled to bias lines (no signal is applied to gn + and gp +). Bulk nodes, bn + and bp + are also connected to their respective bias lines.

Similarly, current l_s- is input to active device 151- source connection S. Due to the common gate operation of the active device 151-, the current l_s-will be split, part of which is directed to dn- as the output current l_out_n and part of which is directed to dp- as the output current l_out_p-.

Any number of capacitors or variable capacitors may be coupled between the + and − nodes of the inputs and outputs, gates and bulks and sources of the tuning block 200. Likewise, any number of capacitors or variable capacitors may be coupled between the + and − nodes of the active device 151+ and the inputs and outputs of the active device 151−. For example, cross capacitors or variable capacitors include dn + and dn-; dp + and dp-; dn- and dp +; may be linked between dn + and dp− and / or any combination thereof. In addition, these capacitors or variable capacitors may include series resistors or series inductance or parallel resistors or parallel inductors that do not affect or alter the present invention.

4D is a block diagram of one embodiment of a single-ended voltage controlled oscillator (VCO) 400 in accordance with the present invention. As shown, the active device 100 is directly connected to the tuning block 200 through a source and in a feedback relationship through a drain.

4E is a block diagram of an embodiment of a differential VCO 400 'in accordance with the present invention. As shown, the active device 151 is directly connected to the tuning block 200 through a source and a gate and in a feedback relationship through a drain.

Figure 4f is a block diagram of an embodiment of a cascaded VCO 400 "in accordance with the present invention. Figure 4f illustrates a common source tuning and cascade of active devices. However, common gate or common gate, common source or even common source. Mix and match of may be implemented according to the present invention.

4G is a block diagram of an embodiment of a differential VCO 410 in accordance with the present invention. As shown, the active device 151 is directly connected to the tuning block 200 in a feedback relationship directly through the source and through the drain. Effective loop feedback has a positive signal to ensure oscillation.

4H is a block diagram of an embodiment of a cascaded VCO 410 'in accordance with the present invention. 4H shows a common gate tuning and cascade of active devices. However, a mix and match of common gates or common gates, common sources or even common sources may be implemented according to the present invention. The dashed line means that there can be many such blocks.

4I is a block diagram of one embodiment of a cascaded VCO 420 in accordance with the present invention. 4I shows a cascade of common gate tuning and active devices with common gate tuning and active devices. The dashed line means that there may be many combinations of common gate active and tuning devices or common gate, common source active and tuning devices.

5 is a diagram of two differential active devices coupled to inductive tuning blocks to form a VCO 500 in accordance with the present invention. FIG. 5 shows how to use a passive inductance with a common gate amplifier to obtain a positive feedback loop where gain is greater than 1 and gain is close to 2. FIG. Clusters of inductors 200 are coupled to each other. This satisfies the condition that the source current is above each drain current specified by the tuning block function. Although not shown in FIG. 5, not only can the same polarity sources be connected together, but the same polarity dn or dp can be connected to each other without changing the function. For example, S + and 151 of each active device may be connected together. Alternatively, the S- of each active device can be connected together.

6 is a diagram of three differential active devices coupled to an inductive tuning block to form a VCO 600 in accordance with the present invention. Figure 6 shows how passive inductance with a common gate amplifier is used to obtain a positive feedback loop with gain greater than 1 and gain closer to 3. Clusters of inductors 200 are coupled to each other. This satisfies the condition that the source current is above each drain current specified by the tuning block function. Although not shown in FIG. 6, not only the same polarity sources may be connected together, but the same polarity dn or dp may be connected to each other without changing the function. For example, S + and 151 of each active device may be connected together. Alternatively, the S- of each active device can be connected together.

7 is a diagram of four differential active devices coupled to an inductive tuning block in accordance with the present invention. Figure 7 shows that this positive feedback allows the gain to be greater than or equal to four. All inductors grouped within the dashed ellipses are connected to each other. Equal polarity source nodes of each active device may be connected together without changing the invention. In addition, the same polarity dn and dp nodes of each active device can be connected together without changing the present invention.

8 is a diagram illustrating drain currents of two active devices are summed before a loop in the VCO 800 according to the present invention. In this way, the drain currents of the two devices are added first and the drains are coupled to the source in a positive feedback manner. Similarly, all or some of the same polarity source furnaces from each differential active device to other differential active devices can be connected to each other without changing the invention.

9 illustrates that drain currents are summed before a loop in the VCO 900 in accordance with the present invention. In this way, drain currents are added first and the three drains are coupled to the source in a positive feedback manner. Similarly, all or some of the same polarity source furnaces from each differential active device to other differential active devices can be connected to each other without changing the invention.

The system and method according to the present invention provides an amplifier circuit that can be combined with a transformer to obtain increased gain and positive feedback for a voltage controlled oscillator (VCO) application. The resulting device does not require a buffer or memory, so it is smaller in size and uses less power than traditional VCOs.

Although the invention has been described in accordance with the illustrated embodiments, those skilled in the art will readily recognize that there may be variations to the embodiments, and such variations will fall within the spirit and scope of the invention. . Accordingly, many modifications may be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims (7)

As a voltage controlled oscillator (VCO),
An active device, the active device comprising an n-type transistor having a drain, a gate, and a bulk; A p-type transistor having a drain, a gate, and a bulk; A first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor; A second capacitor coupled between the drain of the n-type transistor and the drain of the p-type transistor; And a third capacitor coupled between the bulk of the n-type transistor and the bulk of the p-type transistor, wherein the n-type transistor and the p-type transistor share a common source;
A tuning block coupled to the common source to form a common gate amplifier; And
At least one tuning element coupled to the active device to change the overall capacitance of the VCO
Including,
The VCO is memory-less and captures even harmonic signals. The method of claim 1,
Each of the first, second, and third capacitors includes any of a variable capacitor, a capacitor connected in series with a resistor, a capacitor connected in parallel with a resistor, a capacitor connected in series with a inductor, and a capacitor connected in parallel with the inductor. Characterized by a voltage controlled oscillator. The method of claim 1,
Said at least one tuning element comprises any of inductors, capacitors, resistors and transformers, said at least one tuning element comprising two inputs and an output . Differential voltage controlled oscillator (VCO),
First and second active devices, each of the first and second active devices comprising an n-type transistor having a drain, a gate, and a bulk; A p-type transistor having a drain, a gate, and a bulk; A first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor; A second capacitor coupled between the drain of the n-type transistor and the drain of the p-type transistor; And a third capacitor coupled between the bulk of the n-type transistor and the bulk of the p-type transistor, wherein the n-type transistor and the p-type transistor share a common source;
A fourth capacitor coupled between the bulk of the n-type transistor of the first active device and the shared source of the second active device;
A fifth capacitor coupled between the bulk of the p-type transistor of the first active device and the shared source of the second active device;
A sixth capacitor coupled between the bulk of the n-type transistor of the second active device and the shared source of the first active device;
A seventh capacitor coupled between the bulk of the p-type transistor of the second active device and the shared source of the first active device;
A tuning block coupled to the common source to form a common gate amplifier
At least one first tuning element coupled between the drain of the n-type transistor of the first active device and the drain of the n-type transistor of the second active device;
At least one second tuning element coupled between the sources of n-type and p-type transistors of the first active device and the sources of n-type and p-type transistors of the second active device; And
At least one third tuning element coupled between the drain of the p-type transistor of the first active device and the drain of the p-type transistor of the second active device
Including,
The differential VCO is memory-less and captures even harmonic signals. The method of claim 4, wherein
Each of the first, second, and third capacitors includes any of a variable capacitor, a capacitor connected in series with a resistor, a capacitor connected in parallel with a resistor, a capacitor connected in series with a inductor, and a capacitor connected in parallel with the inductor. Differential voltage controlled oscillator. The method of claim 4, wherein
Each of the first, second, and third tuning elements includes any of inductors, capacitors, resistors, and transformers, each of the first, second, and third tuning elements having two inputs; And a single output. The method of claim 4, wherein
The first and third tuning elements are used for coarse tuning of the differential VCO, and the second tuning elements are used for fine tuning of the differential VCO.

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