KR102029025B1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

Info

Publication number
KR102029025B1
KR102029025B1 KR1020120136387A KR20120136387A KR102029025B1 KR 102029025 B1 KR102029025 B1 KR 102029025B1 KR 1020120136387 A KR1020120136387 A KR 1020120136387A KR 20120136387 A KR20120136387 A KR 20120136387A KR 102029025 B1 KR102029025 B1 KR 102029025B1
Authority
KR
South Korea
Prior art keywords
bank
signal
output
data
input
Prior art date
Application number
KR1020120136387A
Other languages
Korean (ko)
Other versions
KR20140068648A (en
Inventor
김승봉
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120136387A priority Critical patent/KR102029025B1/en
Publication of KR20140068648A publication Critical patent/KR20140068648A/en
Application granted granted Critical
Publication of KR102029025B1 publication Critical patent/KR102029025B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

Abstract

The semiconductor memory device may be enabled in response to a bank address for selecting a cell block included in a bank during a read operation in a first output mode and a mode setting signal for determining the number of data bits output in a single read operation. A selection signal generation unit for generating a data and outputting data on a first input / output line to a first DQ pad in response to the selection signal or entering data on a second input / output line in response to the selection signal; It includes a data output unit for output to the DQ pad.

Figure R1020120136387

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device for outputting data in accordance with an output mode.

At present, as the process technology of semiconductor memory devices including DDR SDRAM (Double Data Rate Synchronous DRAM) is rapidly developed, the degree of integration increases, and tens of millions of memory cells are provided in the semiconductor memory device.

The memory bank concept has been introduced to efficiently control such memory cells and to improve operating performance. Thus, the current semiconductor memory device is composed of a plurality of memory banks, each memory bank is composed of memory cells (memory cells).

On the other hand, semiconductor memory devices are designed to operate in accordance with data width options. The data width option allows users to set their own data width, which is defined in the specification. For example, in a semiconductor memory device having 16 input / output pads PAD, when the data width option is set to X16 mode, data input / output operations are performed through the 16 input / output pads, and the data width option is set to X8 mode. When it is set, data input / output operation is performed through 8 data input / output pads among 16 input / output pads, and data input / output through 4 data input / output pads among 16 input / output pads when the data width option is set to X4 mode. The operation is performed.

Here, in the X16 mode, all memory banks included in the semiconductor memory device are selected and operated. In the X4 / X8 mode, only the corresponding memory bank is selected and operated. That is, when two memory banks are provided in the semiconductor memory device, the sub word lines SWL of the two selected memory banks are activated in the X16 mode, and the sub word lines of the selected memory bank are activated in the X8 mode, and X4 In the mode, a sub word line of a selected cell block is activated according to a level state of a specific low bank address signal in one selected memory bank to perform data input / output operations.

The present invention provides a semiconductor memory device in which a plurality of banks can selectively output data of an input / output line according to an output mode.

To this end, the present invention provides a bank address for selecting a cell block included in a bank during a read operation in a first output mode and a selection that is enabled in response to a mode setting signal for determining the number of data bits output in one read operation. A selection signal generation unit for generating a signal and when entering the first output mode, outputting data on a first input / output line to a first DQ pad in response to the selection signal, or outputting data on a second input / output line; 1 provides a semiconductor memory device including a data output unit for outputting to a DQ pad.

The present invention also provides a first bank including a first cell block for loading data on a first input / output line and a second cell block for loading data on a second input / output line, a third cell block for loading data on the first input / output line; A second bank including a fourth cell block for loading data on the second input / output line and one of the first to fourth cell blocks included in the first and second banks during a read operation in a first output mode; A selection signal generation unit for generating an enable signal in response to a bank address for performing the operation and a mode setting signal for determining the number of data bits output in one read operation; and the selection signal when entering the first output mode. And a data output unit configured to output data loaded on the first input / output line to the first DQ pad or output data loaded on the second input / output line to the first DQ pad. Provided is a semiconductor memory device.

According to the present invention, an area of a semiconductor memory device can be reduced by sharing a multiplexer capable of selectively outputting data of input / output lines according to an output mode.

1 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a selection signal generation unit included in the semiconductor memory device shown in FIG. 1.
FIG. 3 is a circuit diagram of a multiplexer included in the semiconductor memory device shown in FIG. 1.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

1 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, a semiconductor memory device according to an exemplary embodiment of the present invention includes a first bank 10, a second bank 20, a selection signal generator 30, and a data output unit 40. do.

The first bank 10 receives the bank address BK_ADD, the first bank active signal BK_ACT <1>, the first bank lead signal BK_RD <1>, and the mode setting signal X4 to activate the word line. And the first cell block 11 and the second input / output line GIO <which load the first to fourth data D <1: 4> on the first input / output lines GIO <1: 4> by performing a read operation. 5: 8>) and the second cell block 12 carrying the fifth to eighth data D <5: 8>. Here, the bank address BK_ADD is one of addresses for selecting a cell block included in a bank during a read operation, and the first bank active signal BK_ACT <1> activates a word line of the first bank 10. The first bank lead signal BK_RD <1> is a signal enabled during a read operation of the first bank 10. In addition, the mode setting signal X4 is enabled at a logic high level in the first output mode in which the number of bits of data output by one read operation is set to 4 bits, and the number of bits of data output by one read operation is 8 bits. The signal is disabled to a logic low level in the set second output mode.

The second bank 20 receives the bank address BK_ADD, the second bank active signal BK_ACT <2>, the second bank lead signal BK_RD <2>, and the mode setting signal X4 to activate the word line. And the third cell block 21 and the second input / output line GIO <which load the first to fourth data D <1: 4> on the first input / output lines GIO <1: 4> by performing a read operation. 5: 8>, the fourth cell block 22 carries the fifth to eighth data D <5: 8>. Here, the second bank active signal BK_ACT <2> is a signal for activating a word line of the second bank 20, and the second bank lead signal BK_RD <2> is a read of the second bank 20. This signal is enabled during operation.

The selection signal generation unit 30 receives the mode setting signal X4 that is enabled when the first output mode is entered and buffers the bank address BK_ADD to generate the selection signal SEL. That is, the selection signal SEL is logic when the first cell block 11 of the first bank 10 or the third cell block 21 of the second bank 20 is selected during a read operation in the first output mode. Generated at low level. In addition, the selection signal SEL is logic when the second cell block 12 of the first bank 10 or the fourth cell block 22 of the second bank 20 is selected during a read operation in the first output mode. Generated at a high level. In addition, the selection signal SEL is generated at a logic low level during a read operation in the second output mode.

The data output unit 40 may include data loaded on the first input / output lines GIO <1: 4> or second input / output lines GIO <5: 8 according to the level of the selection signal SEL during the read operation in the first output mode. The multiplexer 41 for selectively transferring the data contained in the &quot;) to the first to fourth transfer data TD <1: 4> and buffering the first to fourth transfer data TD <1: 4> A second output driver for buffering the data on the first output driver 42 and the second input / output lines GIO <5: 8> output to the first DQ pad 50 and outputting the buffered data to the second DQ pad 60. 43). Here, the second output driver 43 is not driven in the first output mode. In addition, the first and second DQ pads 50 and 60 are provided with the number of first and second input / output lines GIO <1: 4> and GIO <5: 8>, respectively. It is preferable to output the data contained in GIO <1: 4>, GIO <5: 8>).

2 is a circuit diagram of the selection signal generation unit 30 included in the semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2, the selection signal generation unit 30 includes first to third transfer units 31 to 33.

The first transfer unit 31 latches the bank address BK_ADD to generate the first latch signal LATCH <1> when the first bank selection signal BK_SEL <1> is enabled. ), When the mode setting signal X4 is enabled at the logic high level by entering the first output mode, the first read selection signal RD_SEL <1> is input to generate the first switching signal SW <1>. And a first transfer gate T30 that receives the first logic unit 311 and the first switching signal SW <1> and transfers the first latch signal LATCH <1> as the selection signal SEL. do. Here, the first bank selection signal BK_SEL <1> is a signal that is enabled when the first bank 10 is selected according to a combination of addresses input from the outside. The first read select signal RD_SEL <1> is a signal in which the first bank 10 is selected and enabled during the read operation.

The second transfer unit 32 latches the bank address BK_ADD to generate the second latch signal LATCH <2> when the second bank selection signal BK_SEL <2> is enabled. When the mode setting signal X4 is enabled at the logic high level, the second read signal RD_SEL <2> is input to generate the second switching signal SW <2>. And a second transfer gate T31 that receives the second logic unit 321 and the second switching signal SW <2> and transfers the second latch signal LATCH <2> as the selection signal SEL. do. Here, the second bank selection signal BK_SEL <2> is a signal that is enabled when the second bank 20 is selected according to a combination of addresses input from the outside. The second read select signal RD_SEL <2> is a signal in which the second bank 20 is selected and enabled in the read operation.

The third transfer unit 33 is a third transfer gate T32 that transfers the ground voltage VSS to the selection signal SEL when the mode setting signal X4 is disabled at the logic low level in the second output mode. It is composed.

3 is a circuit diagram of a multiplexer 40 included in a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, in the multiplexer 41, when the selection signal SEL is input at a logic low level, the transfer gates T40, T42, T44, and T46 are turned on, and the transfer gates T41, T43, T45, T47 is turned off to transfer the data on the first input / output lines GIO <1: 4> to the first to fourth transfer data TD <1: 4>, and the selection signal SEL is at a logic high level. When input to the transfer gates (T41, T43, T45, T47) is turned on, the transfer gates (T40, T42, T44, T46) is turned off and loaded on the second input and output lines (GIO <5: 8>). The data is transmitted to the first to fourth transfer data TD <1: 4>. The inversion selection signal SELB is a signal generated by inverting the selection signal SEL.

The operation of the semiconductor memory device configured as described above will be described with reference to FIGS. 1 to 3, wherein the third cell block 21 of the second bank 20 is selected in the first output mode and the fourth cell. A case in which the block 22 is selected will be described below, and a case in which the second bank 20 is selected in the second output mode will be described below.

First, a case in which the third cell block 21 of the second bank 20 is selected in the first output mode will be described below.

The first transfer unit 31 of the selection signal generation unit 30 receives the mode setting signal X4 which is enabled at the logic high level and thus selects the bank address BK_ADD because the first bank 10 is not selected. Do not pass to (SEL). The second latch 320 of the second transfer unit 32 receives a second bank selection signal BK_SEL <2> enabled at a logic high level to latch a logic low level bank address BK_ADD to logic low The second latch signal LATCH <2> of the level is generated. The second logic unit 321 performs a negative logic operation on the logic high level second read selection signal RD_SEL <2> and the logic high level mode setting signal X4 to perform a logic low level second switching signal. Create (SW <2>). The transfer gate T31 receives the second switching signal SW <2> at the logic low level and is turned on to transfer the second latch signal LATCH <2> at the logic low level as the selection signal SEL. The third transfer unit 33 receives the logic high level mode setting signal X4 and the transfer gate T32 is turned off so that the ground voltage VSS is not transmitted to the selection signal SEL. That is, the selection signal generator 30 generates a logic low level selection signal SEL when the third cell block 21 of the second bank 20 is selected in the first output mode.

The multiplexer 41 of the data output unit 40 receives the logic low level selection signal SEL and the transfer gates T40, T42, T44, and T46 are turned on, and the transfer gates T41, T43, T45, T47 is turned off to transfer the data on the first input / output lines GIO <1: 4> to the transfer data TS <1: 4>. The first output driver 42 buffers the transfer data TS <1: 4> and outputs the buffered data to the first DQ pad 50. The second output driver 43 is not driven in the first output mode.

Next, a case in which the fourth cell block 22 of the second bank 20 is selected in the first output mode will be described.

The first transfer unit 31 of the selection signal generation unit 30 receives the mode setting signal X4 which is enabled at the logic high level and thus selects the bank address BK_ADD because the first bank 10 is not selected. Do not pass to (SEL). The second latch 320 of the second transfer unit 32 receives the second bank selection signal BK_SEL <2> enabled at the logic high level to latch the logic high level bank address BK_ADD to logic high. The second latch signal LATCH <2> of the level is generated. The second logic unit 321 performs a negative logic operation on the logic high level second read selection signal RD_SEL <2> and the logic high level mode setting signal X4 to perform a logic low level second switching signal. Create (SW <2>). The transfer gate T31 receives the second switching signal SW <2> at the logic low level and is turned on to transfer the second latch signal LATCH <2> at the logic high level as the selection signal SEL. The third transfer unit 33 receives the logic high level mode setting signal X4 and the transfer gate T32 is turned off so that the ground voltage VSS is not transmitted to the selection signal SEL. That is, the selection signal generator 30 generates a logic high level selection signal SEL when the fourth cell block 22 of the second bank 20 is selected in the first output mode.

The multiplexer 41 of the data output unit 40 receives the logic high level selection signal SEL and the transfer gates T40, T42, T44, and T46 are turned off, and the transfer gates T41, T43, and T45 are turned off. T47 is turned on to transmit the data loaded on the second input / output lines GIO <5: 8> to the transfer data TS <1: 4>. The first output driver 42 buffers the transfer data TS <1: 4> and outputs the buffered data to the first DQ pad 50. The second output driver 43 is not driven in the first output mode.

Next, a case in which the second bank 20 is selected in the second output mode will be described.

The first transfer unit 31 of the selection signal generation unit 30 receives the mode setting signal X4 which is disabled at the logic low level and does not transmit the bank address BK_ADD to the selection signal SEL. The second transfer unit 32 receives the mode setting signal X4 which is disabled at the logic low level and does not transmit the bank address BK_ADD to the selection signal SEL. The third transfer unit 33 receives the mode setting signal X4 having a logic low level, and the transfer gate T32 is turned on to transfer the ground voltage VSS to the selection signal SEL. That is, when the second bank 20 is selected in the second output mode, the selection signal generator 30 generates a selection signal SEL having a logic low level.

The multiplexer 41 of the data output unit 40 receives the logic low level selection signal SEL and the transfer gates T40, T42, T44, and T46 are turned off, and the transfer gates T41, T43, and T45 are turned off. T47 is turned on to transmit the data loaded on the first input / output lines GIO <1: 4> to the transfer data TS <1: 4>. The first output driver 42 buffers the transfer data TS <1: 4> and outputs the buffered data to the first DQ pad 50. The second output driver 43 buffers the data on the second input / output lines GIO <5: 8> and outputs the buffered data to the second DQ pad 60.

The semiconductor memory device according to the embodiment of the present invention configured as described above has a plurality of banks sharing a multiplexer for selectively transferring data loaded on a first input / output line or data loaded on a second input / output line according to first and second output modes. The area can be reduced.

10. First Bank 11. First Cell Block
12. Second Cell Block 20. Second Bank
21. Third Cell Block 22. Fourth Cell Block
30. Selection signal generator 31. First transfer unit
32. Second delivery unit 33. Third delivery unit
40. Data output section 41. Multiplexer
42. First output driver 43. Second output driver
50. First DQ Pad 60. Second DQ Pad
310. First latch 311. First logic portion
320. Second latch 321. Second logic portion

Claims (20)

A first transfer unit buffering the bank address and transferring the selected bank signal when the first bank is selected in response to the mode setting signal for determining the number of data bits output in one read operation;
A second transfer unit buffering the bank address and transferring the selected bank signal when the second bank is selected in response to the mode setting signal; And
And a data output unit configured to output data loaded on a first input / output line to a first DQ pad or output data loaded on a second input / output line to the first DQ pad in response to the selection signal. A semiconductor memory device.
Claim 2 has been abandoned upon payment of a set-up fee. The method of claim 1, wherein the data output unit
When the second output mode is entered, the semiconductor memory transfers data loaded on the first input / output line to the first DQ pad and transfers data loaded on the second input / output line to a second DQ pad in response to the selection signal. Device.
Claim 3 has been abandoned upon payment of a set-up fee. The method of claim 1, wherein the first input / output line is connected to a first cell block included in the first bank and a third cell block included in the second bank, and the second input / output line is connected to the first bank. And a second cell block included in the second cell block and a fourth cell block included in the second bank.
Claim 4 has been abandoned upon payment of a setup registration fee. The display device of claim 1, wherein the selection signal has a first level when a first cell block of the first bank or a third cell block of the second bank is selected during a read operation in the first output mode. The second memory block of one bank or the fourth cell block of the second bank is a signal having a second level when the second cell block is selected.
Claim 5 was abandoned upon payment of a set-up fee. The semiconductor memory device of claim 4, wherein the selection signal is a signal having the first level during the read operation in a second output mode.
delete Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the first transfer unit
A first latch configured to generate a first latch signal by latching the bank address in response to a first bank selection signal enabled when the first bank is selected;
A first logic unit configured to generate a first switching signal by buffering a first read signal selected by the first bank and enabled during a read operation in response to the mode setting signal; And
And a first transfer element transferring the first latch signal as the selection signal in response to the first switching signal.
Claim 8 has been abandoned upon payment of a set-up fee. The method of claim 7, wherein the second transfer unit
A second latch for latching the bank address to generate a second latch signal in response to a second bank selection signal enabled when the second bank is selected;
A second logic unit configured to generate a second switching signal by buffering a second read selection signal selected in response to the mode setting signal and enabled during the read operation; And
And a second transfer element transferring the second latch signal as the selection signal in response to the second switching signal.
Claim 9 was abandoned upon payment of a set-up fee. The semiconductor memory device of claim 1, further comprising a third transfer unit configured to transfer a ground voltage as the selection signal when entering the second output mode in response to the mode setting signal.
Claim 10 has been abandoned upon payment of a setup registration fee. The method of claim 1, wherein the data output unit
A multiplexer configured to transfer data loaded on the first input / output line as transfer data or transfer data loaded on the second input / output line as the transfer data in response to the selection signal;
A first output driver buffering the transfer data and outputting the buffered data to the first DQ pad; And
And a second output driver for buffering the data loaded on the second input / output line and outputting the buffered data to a second DQ pad.
A first bank including a first cell block loading data on a first input / output line and a second cell block loading data on a second input / output line;
A second bank including a third cell block loading data on the first input / output line and a fourth cell block loading data on the second input / output line;
A first transfer unit buffering a bank address as a selection signal when the first bank is selected in response to a mode setting signal for determining the number of data bits output in one read operation;
A second transfer unit buffering the bank address and transferring the selected bank signal when the second bank is selected in response to the mode setting signal; And
When entering the first output mode, a data output for outputting data loaded on the first input / output line to a first DQ pad or outputting data loaded on the second input / output line to the first DQ pad in response to the selection signal. A semiconductor memory device comprising a portion.
Claim 12 was abandoned upon payment of a set-up fee. The method of claim 11, wherein the data output unit
When the second output mode is entered, the semiconductor memory transfers data loaded on the first input / output line to the first DQ pad and transfers data loaded on the second input / output line to a second DQ pad in response to the selection signal. Device.
Claim 13 was abandoned upon payment of a set-up fee. The method of claim 11, wherein the first input / output line is connected to the first cell block included in the first bank and the third cell block included in the second bank, and the second input / output line is connected to the first cell block. And a second cell block included in a bank and a fourth cell block included in the second bank.
Claim 14 was abandoned upon payment of a set-up fee. 12. The method of claim 11, wherein the selection signal has a first level when the first cell block of the first bank or the third cell block of the second bank is selected during a read operation in the first output mode. And a signal having a second level when the second cell block of the first bank or the fourth cell block of the second bank is selected.
Claim 15 was abandoned upon payment of a set-up fee. The semiconductor memory device of claim 14, wherein the selection signal is a signal having the first level during the read operation in a second output mode.
delete Claim 17 was abandoned upon payment of a set-up fee. The method of claim 11, wherein the first transfer unit
A first latch configured to generate a first latch signal by latching the bank address in response to a first bank selection signal enabled when the first bank is selected;
A first logic unit configured to generate a first switching signal by buffering a first read selection signal selected by the first bank in response to the mode setting signal and enabled during a read operation; And
And a first transfer element transferring the first latch signal as the selection signal in response to the first switching signal.
Claim 18 was abandoned when the set registration fee was paid. The method of claim 17, wherein the second transfer unit
A second latch for latching the bank address to generate a second latch signal in response to a second bank selection signal enabled when the second bank is selected;
A second logic unit configured to generate a second switching signal by buffering a second read signal selected by the second bank in response to the mode setting signal and enabled during the read operation; And
And a second transfer element transferring the second latch signal as the selection signal in response to the second switching signal.
Claim 19 was abandoned upon payment of a set-up fee. The semiconductor memory device of claim 11, further comprising a third transfer unit configured to transfer a ground voltage as the selection signal when the second output mode enters the second output mode in response to the mode setting signal.
Claim 20 was abandoned when the set registration fee was paid. The method of claim 11, wherein the data output unit
A multiplexer which transfers data of the first input / output line as transfer data or transfers data of the second input / output line as the transfer data in response to the selection signal;
A first output driver buffering the transfer data and outputting the buffered data to the first DQ pad; And
And a second output driver for buffering the data of the second input / output line and outputting the buffered data to a second DQ pad.
KR1020120136387A 2012-11-28 2012-11-28 Semiconductor memory device KR102029025B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120136387A KR102029025B1 (en) 2012-11-28 2012-11-28 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120136387A KR102029025B1 (en) 2012-11-28 2012-11-28 Semiconductor memory device

Publications (2)

Publication Number Publication Date
KR20140068648A KR20140068648A (en) 2014-06-09
KR102029025B1 true KR102029025B1 (en) 2019-10-07

Family

ID=51124363

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120136387A KR102029025B1 (en) 2012-11-28 2012-11-28 Semiconductor memory device

Country Status (1)

Country Link
KR (1) KR102029025B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102204390B1 (en) * 2014-09-12 2021-01-18 삼성전자주식회사 Memory device with fast fail cell repair
KR102251216B1 (en) * 2014-11-21 2021-05-12 삼성전자주식회사 Address-remapped memory chip, memory module and memory system including the same
KR102468283B1 (en) * 2015-11-09 2022-11-21 에스케이하이닉스 주식회사 Control circuit and memory device including the control circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100972866B1 (en) * 2008-06-27 2010-07-28 주식회사 하이닉스반도체 Data output controlling circuit
KR100956783B1 (en) * 2008-10-14 2010-05-12 주식회사 하이닉스반도체 Semiconductor Memory Apparatus
KR20110108558A (en) * 2010-03-29 2011-10-06 주식회사 하이닉스반도체 Semiconductor memory apparatus and its compress test method

Also Published As

Publication number Publication date
KR20140068648A (en) 2014-06-09

Similar Documents

Publication Publication Date Title
US11886754B2 (en) Apparatuses and methods for configuring I/Os of memory for hybrid memory modules
KR102086465B1 (en) Semiconductor device and method of driving the same
KR102043222B1 (en) Apparatuses, memories, and methods for address decoding and selecting an access line
CN107258000A (en) Method and apparatus for performing data manipulation in memory devices
US20150036439A1 (en) Semiconductor device
US7289385B2 (en) Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method
KR102029025B1 (en) Semiconductor memory device
US20150127870A1 (en) Semiconductor memory device
KR20080049625A (en) Semiconductor memory device
US20080229029A1 (en) Semiconductor Memory System Having Plurality of Ranks Incorporated Therein
KR20080022737A (en) Memory device and method for precharging memory device
KR100800160B1 (en) Data ouput circuit for semiconductor memory device
TWI787255B (en) Data control circuit, and semiconductor memory apparatus and semiconductor system including the same
US20110026337A1 (en) Data input/output circuit and semiconductor memory apparatus including the same
US9792970B2 (en) Semiconductor device and semiconductor system
KR102184706B1 (en) Semiconductor device and method of driving the same
US9558829B2 (en) System having a semiconductor integrated circuit device
KR20130046105A (en) Semiconductor memory device and operating method thereof
US10902907B1 (en) Output drivers, and related methods, memory devices, and systems
US20100246310A1 (en) Address converting circuit and semiconductor memory device using the same
US20070070670A1 (en) Semiconductor memory device
US8036045B2 (en) Data output control circuit
US7263014B2 (en) Semiconductor memory device having N-bit prefetch type and method of transferring data thereof
KR20190026232A (en) Electric device including register
KR102401877B1 (en) Semiconductor device and semiconductor system including thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant