KR102011945B1 - Black level compensating device of column parallel ADC - Google Patents

Abstract

Disclosed is a black level compensating device of a column parallel analog-to-digital converter (ADC) capable of suppressing the distortion of a signal caused by dark current to the maximum at high temperature/low brightness through amplification of a pre-amplifier. A black level compensating device of a column parallel ADC, as a black level compensating device included between pixels of a column parallel ADC and a pre-amplifier, comprises: a compensating capacitor (Cb) of which one end is connected between an output end of the pixel and a negative (-) input terminal of the pre-amplifier; and a current digital-to-analog converter (DAC) 1 connected to the other end of the compensating capacitor (Cb) and outputting voltage of a bottom plate (BP) corresponding to an optical black (OB) signal.

Description

Black level compensating device of column parallel ADC

The present invention relates to a thermal parallel analog-to-digital converter, and more particularly to a black level compensation device of a thermal parallel analog-to-digital converter.

1 is a diagram of the main block of a column parallel analog-to-digital converter with a preamp.

Referring to FIG. 1, a pixel 11 exists in the column parallel ADC 1, and an output of the pixel 11 is made of a signal vin. The pixel 11 and the current sink operate as a source follower.

vin is a pixel output signal. In a parallel parallel ADC, a Correlate Double Sampling (CDS) operation is performed to read the signal twice at a time interval. First, the reset level of the pixel 11 and the signal level of the pixel 11 are read.

While reading the reset level (Rx operation), pa_rst, a preamp reset signal, is connected between the negative input terminal and the output terminal of the preamplifier 12 so that the preamplifier output signal vin_pre is positive. +) Exported to the vref_pa level entered at the input terminal. Then, while qrst is connected at the rear end of the preamplifier 12, the negative input terminal of the comparator 13 enters the signal to fill the vin_rst capacitor C1. When the reset operation is complete, pa_rst switches off and waits for Tx to open.

The pixel signal is started by storing information in the pixel 11 and reading it through a Tx operation. Tx opens the pixel data and transitions to the vin signal. In this case, the vin signal is changed from high to low, and the larger the size of the stored pixel signal is, the more it falls. When the vin signal transitions, the size of the output vin_pre, which is a signal of the preamplifier 12, is determined according to the set gain. While qsig is floating (i.e., when the switch corresponding to qsig is turned on), the output signal of the preamplifier 12 is transmitted as a vin_sig signal to the positive input terminal of the comparator 13, and the vin_sig capacitor C2 ) Will fill that signal. After this operation, the CDS operation is complete. The qsig and qrst signals are off.

Among the vramp_cds signal and the vrst_cds signal, the vramp_cds signal, which is a signal present in the bottom plate of the comparator 13, has a constant slope from high to low to perform a ramp operation. do.

While the vramp_cds signal transitions low with a constant slope, the vin_sig signal present on the top plate also starts to transition at the same time. At the point where the vin_sig signal crosses the vin_rst level, the comparator 13 sends an output signal.

On the other hand, from the operation in which the vramp_cds signal transitions low, the signal of code <n: 0> ((n + 1) bit signal) is updated while continuously increasing the code in the memory 14 existing in the CDS block. .

On the basis of the time when the output signal of the comparator 13 is triggered high, the memory 14 is digitized while the currently updated code is stored.

2 is a timing diagram for the column parallel ADC of FIG. 1 using a preamplifier.

The Black Level Compensation (BLC) operation reads an output code corresponding to a non-lighting pixel (OB, Optical Black), and the output code is greater than " zero " Or if it is determined to be below "0", it is necessary to make it as close as possible to "0".

For example, if the vin_sig signal is 700mV higher than the vin_rst signal, a code corresponding to 700 at the cross point may be stored in the memory by the ramp operation.

That is, when the output code is floating or sinking by reading the optical black signal (OB signal), the corresponding code is changed to the analog signal through the current DAC. If the OB output is high before the ramp is performed, the offset of the vrst_cds signal is offset. Spawn to approximate the "0" code. Alternatively, if it is determined that the signal is less than or equal to the "0" code, an offset (high level) of the vramp_cds signal is raised so that only the pure signal is output by the pixel that receives the actual light.

3 is a conceptual diagram illustrating amplification of a preamplifier that amplifies a signal when a general pixel is read at low light, and FIG. 4 is a conceptual diagram illustrating a signal input to the preamplifier at low light, particularly at a high temperature, and amplification thereof.

The black level compensation (BLC) is controlled by vramp_cds and vrst_cds input to the comparator. Therefore, the distortion signal caused by the dark current in the low light condition (i.e., the maximum gain of the preamplifier at high temperature) is also amplified by the maximum gain of the preamplifier. Serious degradation is caused. As the temperature increases, the dark current of the pixel transistor also increases, which may be a problem in high temperature situations.

Since the signal amplified by the maximum gain of the preamplifier is out of the limit that can be adjusted by changing the offset of vramp_cds or vrst_cds, it may result in image quality that is difficult to recover. In this case, it was not possible to maximize the gain of the high preamplifier made to minimize the pixel noise, and the conventional black level compensation method was limited.

Korean Laid-Open Patent Publication No. 10-2007-0070990 (published Jul. 4, 2007)-Image sensor with automatic black level compensation

An object of the present invention is to provide a black level compensation device of a thermal parallel analog-to-digital converter capable of maximally suppressing distortion of a signal caused by dark current in a high temperature / low light condition through amplification of a preamplifier.

An object of the present invention is to provide a black level compensation device of a column-parallel analog-to-digital converter capable of maximizing a reduction effect of fixed pattern noise (FPN).

Other objects of the present invention will be readily understood through the following description.

According to an aspect of the present invention, a black level compensation device is included between a pixel and a preamplifier of a column parallel analog-to-digital converter (Column Parallel ADC) for digitally converting a pixel signal that is an analog signal, one end of which is the output end of the pixel and the A compensation capacitor Cb connected between the negative input terminal of the preamp; And a current DAC1 connected to the other end of the compensation capacitor Cb and outputting a bottom plate BP voltage corresponding to the optical black signal.

The current DAC1 inputs a digitized OB signal and a black level compensation (BLC) operation signal, converts the OB signal into an OB current which is an analog signal having a corresponding magnitude, and then converts the OB current according to the BLC operation signal. By reflecting it can change the BP voltage of the compensation capacitor.

The current DAC1 may include a low level output unit configured to output a predetermined low level voltage; An OB current converter configured to control on / off of a transistor according to a bit value of the OB signal to convert the OB signal into an OB current having a corresponding magnitude; And initially outputting the output of the low level output unit as the BP voltage of the compensation capacitor, and outputting the BP corresponding to the magnitude of the OB current converted by the OB current converter according to a black level compensation (BLC) operation signal. It may include a BP signal output unit for changing the magnitude of the voltage.

The low level output unit may include a LL transistor to which a VDD voltage is applied to a source terminal, and a drain terminal is connected to an output terminal of the BP signal output unit and turned on by a bias voltage applied to a gate terminal.

When the OB signal is a binary (n + 1) bit signal, the OB current converter includes a bit digit (BL) transistor corresponding to the number of bits (n + 1) of the OB signal, and the BL A bit value interlocker in which transistors are controlled on / off according to bit values assigned to respective bit positions of the OB signal; A current distribution including (n + 1) bit digit (BV) transistors 1: 1 matched to each of the BL transistors and configured to flow a current having a level corresponding to a bit digit corresponding to the matched BL transistors It may include wealth.

The (k + 1) -th BV transistor corresponding to the k-th bit of the OB signal among the BV transistors includes 2 ^{k + 1} current output (CL) transistors to which a predetermined bias voltage is applied to a gate terminal. It can deliver ^2k times more current than a BV transistor.

A bit value of a corresponding bit position among the OB signals is input to the BL transistor, and when the bit value is '0', the bit value is turned on, and when the bit value is '1', the bit value is turned off, and the OB signal is optical black. The OB code, which is the digital output value of the pixel, may be an inverted inversion code.

The BL transistor has a common gate structure in which gate ends thereof are connected to each other, and the OB current converter has (n + 1) BL transistors individually on / off controlled according to bit values of the OB signal, and the bit value is' The BP signal output unit may be introduced into the OB signal in which the current of the level corresponding to the bit position corresponding to 0 'is added.

The BP signal output unit may include: a BLC transistor to which the OB current flows into a source terminal, a drain terminal is connected to the output terminal, and a BLC operation signal is applied to a gate terminal; It may include a resistor connected between the drain terminal and the ground of the BLC transistor.

The BLC transistor may be turned on when the BLC operation signal transitions from high to low so that the OB current flows to the drain terminal, and the OB current meets the resistance to increase the level of the BP signal.

Meanwhile, according to another aspect of the present invention, a black level compensation device implemented in the preamplifier in a column parallel ADC structure using the preamplifier, comprising: a switch having one end connected to an output terminal of a pixel; And a compensation capacitor having one end connected between the other end of the switch and an input end of the preamplifier, wherein one end of the compensation capacitor is input with an output of the pixel and another end of the compensation capacitor with a black level compensation level. A black level compensation device for a thermal parallel ADC is provided.

The black level compensation level may be adjusted by connecting a current DAC1 and a resistor to the other end of the compensation capacitor.

The current DAC1 may operate by receiving an OB signal, which is an ADC output signal read from an optical black pixel, and a signal indicating a black level compensation operation.

Meanwhile, according to another aspect of the present invention, a black level compensation device implemented in the preamplifier in a column parallel ADC structure using a preamplifier, comprising a sink transistor and an enable connected between an output terminal of a pixel and an input terminal of the preamplifier Including a transistor, wherein the enable transistor is provided with a black level compensation device, characterized in that turned on by the enable signal generated by triggering the output of the temperature sensor.

The sink transistor is operated by a VCON signal, the VCON signal is generated by a current copy circuit, and the bias level of the VCON signal may be adjusted by adjusting a resistor.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

According to an embodiment of the present invention, the amplification of the preamplifier has an effect of suppressing distortion of a signal generated due to a dark current in a high temperature / low light condition as much as possible.

In addition, it is possible to maximize the reduction effect of the fixed pattern noise (FPN).

1 is a diagram of the main block of a column parallel analog-to-digital converter (Column Parallel ADC) with a preamp,
2 is a timing diagram for the column parallel ADC of FIG. 1 using a preamp;
3 is a conceptual diagram illustrating an amplification phenomenon of a preamplifier that amplifies a signal when a normal pixel is read at low light;
4 is a conceptual diagram illustrating a signal input to a preamplifier and amplification thereof at low light, particularly at high temperature;
5 is a circuit diagram showing a preamplifier of a column parallel ADC with a black level compensation device according to a first embodiment of the present invention;
6 is a diagram illustrating an implementation of the current DAC1 included in the black level compensation device according to the first embodiment;
7 is a diagram illustrating an example of an OB signal;
8 is a timing diagram illustrating a column parallel ADC operation using a preamplifier including a black level compensation device according to a first embodiment;
9 is a circuit diagram showing a preamplifier front end of a thermal parallel ADC having a black level compensation device according to a second embodiment of the present invention.
10 is a circuit diagram illustrating a preamplifier front end of a column parallel ADC having a black level compensation device according to a third embodiment of the present invention.
11 is a diagram illustrating an implementation of a current DAC2 included in a black level compensation device according to the second and third embodiments;
12 illustrates a temperature sensor and an enable signal using the same.

As the present invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described on the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

In addition, the components of the embodiments described with reference to the drawings are not limited to the corresponding embodiments, and may be implemented to be included in other embodiments within the scope of the technical spirit of the present invention. Even if the description is omitted, it is obvious that a plurality of embodiments may be reimplemented into one integrated embodiment.

In addition, in the description with reference to the accompanying drawings, the same components regardless of reference numerals will be given the same or related reference numerals and redundant description thereof will be omitted. In the following description of the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In addition, the terms “… unit”, “… unit”, “… module”, “… unit” described in the specification mean a unit that processes at least one function or operation, which means hardware or software or hardware and software. It can be implemented as a combination of.

FIG. 5 is a circuit diagram illustrating a preamplifier of a column parallel ADC having a black level compensation device according to a first embodiment of the present invention, and FIG. 6 is an implementation of the current DAC1 included in the black level compensation device according to the first embodiment. FIG. 7 is a diagram illustrating an example of an OB signal, and FIG. 8 is a timing diagram illustrating a column parallel ADC operation using a preamplifier including a black level compensation device according to a first embodiment.

Referring to FIG. 5, the circuit on the rear side of the preamplifier 12 including the comparator 13 is identically omitted when compared with the column parallel ADC shown in FIG. 1.

A switch is interposed between the pixel 11 and the preamp 12. The switch is controlled on / off by the px_en signal.

The compensation capacitor Cb is added to the vin signal after the switch. The current DAC1 20 is disposed on a bottom plate of the compensation capacitor Cb.

The current DAC1 20 is a digital analog converter, and an optical black signal (OB signal) OBb <n: 0> is input to the first input signal. The OB signal is a signal (OB code or inverted code) corresponding to the ADC output value of the optical black pixel (OB pixel) and may be a (n + 1) bit digital signal represented in binary. N is an integer of 0 or more.

In addition, the BLC operation signal blc_onb is input to the current DAC1 20 as the second input signal. As soon as the BLC operation signal blc_onb transitions from high to low, the voltage level vin_bot of the bottom plate of the compensation capacitor Cb is changed.

6 illustrates one embodiment of current DAC1 20.

The current DAC1 20 includes a low level output unit 30, an optical black (OB) current output unit 40, and a bottom plate (BP) signal output unit 50.

The low level output unit 30 is a portion such that the output signal vin_bot initially output from the current DAC1 20 indicates a specific low level. One side of the current DAC1 20 (far right in the drawing) LL (low level) transistors T31 and T32 disposed therein.

The first LL transistor T31 and the second LL transistor T23 are connected in series. A constant voltage vbias that is present to flow a current of a specific value is applied to the gate terminal of the first LL transistor T31, and the transistor T32 is always turned on at the gate terminal of the second LL transistor T32. VSS voltage is applied.

The VDD voltage is applied to the source terminal of the first LL transistor T31, and the source terminal of the second LL transistor T32 is connected to the drain terminal of the first LL transistor T31. The output signal vin_bot may be output to the drain terminal of the second LL transistor T32. Here, the second LL transistor T32 may be omitted.

On the other side (left side in the figure) of the current DAC1 20, an OB current converter 40 for outputting a current corresponding to the OB signal is disposed.

The OB current converter 40 includes a bit value interlocking unit including a number n + 1 bit position BL transistors T20 to T2n corresponding to the number of bits of an OB signal that is a (n + 1) bit digital signal. (44) and (n + 1) bit position value (BV) transistor stages T10 through which current flows at a level corresponding to the bit position corresponding to each of the (n + 1) BL transistors T20 to T2n. And a current distributor 42 comprising T1n).

The bit value interlock unit 44 controls ON / OFF of the BL transistors T20 to T2n corresponding to binary (n + 1) bit OB signals whose bit values are represented by '0' and '1'. Allow transistor operation linked to the bit value to be performed.

The BL transistor T2 * is a PMOS and may be turned on when a low level (ie, 0V) is applied to the gate terminal. That is, when the bit value of any bit position of the OB signal is '0', the corresponding BL transistor T2 * is turned on, and when the bit value is '1', the BL transistor T2 * is turned off. .

According to the operation of the BL transistor, the inverted code OBb <n: 0> in which the code OB <n: 0> corresponding to the ADC output value of the OB pixel is inverted may be applied to the OB signal. For example, when OB <9: 0> = 0100000000, OBb <9: 0> = 1011111111 may be input to the current DAC1 20 as an OB signal.

The current divider 42 flows a current having a magnitude corresponding to the bit position value allocated to each bit position of the binary (n + 1) bit.

The order is defined as the least significant bit being the 1st bit and the most significant bit being the (n + 1) th bit in the (n + 1) -bit OB signal. In this case, the bit position value of the bit position corresponding to the (k + 1) th bit is 2 ^k . Here, 0 ≦ k ≦ n.

At this time, if it is assumed that Io flows in the first BV transistor T10 corresponding to the first bit in the current distributor 42, the (k + 1) th BV transistor corresponding to the (k + 1) th bit ( T1k) is configured to flow 2 ^k Io. That is, the (k + 1) -th BV transistor corresponding to the k-th bit in the OB signal includes 2 ^{k + 1} current output (CL) transistors, so that it can flow 2 ^K times as much current as the first BV transistor. It becomes possible.

Here, each of the BL transistors T2 * is connected in a 1: 1 match with the BV transistor stage T1 * that supplies a current having a magnitude corresponding to the bit position value corresponding to the bit position of the BL transistor. For example, the (k + 1) -th BL transistor T2k is matched 1: 1 with the (k + 1) -th BV transistor stage T1k.

At this time, the (k + 1) th BV transistor stage T1k includes m (= 2 ^{k + 1} ) current output CL transistors.

A constant voltage is applied to the gate terminal of one CL transistor to output a current having a constant magnitude. For example, a current of 1 uA (= Io) can flow. In this case, 10 uA of current may flow for the 10 CL transistors. In the present embodiment, it is assumed that the resistance R is 1K ohm for convenience.

Accordingly, the current distributor 42 has (n + 1) BV transistor stages T10 to 1 (= 2 ⁰ ) uA, 2 (= 2 ¹ ) uA, ..., 2 ⁿ uA, respectively. T1n).

In the present exemplary embodiment, each transistor belonging to the bit value interlock 44 and the current divider 42 may be matched as follows.

In the 1 (= 0 + 1) -th BL transistor T20, the first BV transistor T10 including 1 (= 2 ⁰ ) CL transistors is 1: 1 matched, and the (n + 1) -th BL transistor T2n ) May be 1: 1 matched to the (n + 1) -th BV transistor T1n including 2 ⁿ CL transistors.

For example, a bit value (0 or 1) corresponding to the second bit position (meaning the order from the least significant bit) of the OB signal is applied to the gate terminal of the second BL transistor T21 to turn on the transistor. Control on / off.

The second BV transistor T11 that is matched 1: 1 with the second BL transistor T21 includes two CL transistors. When the bit value 0 is applied to the second BL transistor T21 and turned on, It will flow the current.

Since the (n + 1) BL transistors T20 to T2n have a common drain structure in which drain terminals are connected to each other, currents representing bit position values corresponding to the turned-on BL transistors are summed together so that the BP signal output unit will be described later. 50 is introduced into the optical black current (OB current). Here, OB current is a current having a magnitude corresponding to the OB signal.

The BP signal output unit 50 includes a BLC transistor T4 whose on / off is controlled by the BLC operation signal blc_onb applied to the gate terminal. A resistor R is connected to the drain terminal of the BLC transistor T4, and is connected to the drain terminal of the LL transistor T32 to become an output terminal of the current DAC1 20.

A source terminal of the BLC transistor T4 is connected to an output terminal of the OB current converter 44, that is, a common drain terminal of the BL transistors T20 to T2n, so that currents representing bit positions corresponding to the turned-on BL transistors are mutually different. The combined OB current is introduced.

When the BLC transistor T4 is turned on by the BLC operation signal, the OB current flows to the output terminal, and the voltage at the output terminal rises by a magnitude corresponding to the OB current by the resistor R connected to the drain of the BLC transistor T4. do.

Therefore, the BP signal vin_bot, which is initially outputted at the low level, may be output by increasing the level by a magnitude corresponding to the OB current.

The operation of the current DAC1 20 will be described as an example.

If you define the overall screen brightness of the image sensor as 0 to 1024 codes, it is normal for the OB pixels to have 0 code when read as a part with no light. In this case, it is assumed that a pixel having a 1V dynamic range becomes 1024 codes through the ADC.

If 256 codes are read when an OB pixel is read, the pixel output value needs to be lowered to be 0 code. The first input signal OBb <9: 0> = 1011111111 (OB <9: 0> = 0100000000 of the current DAC1 20 so that an analog value corresponding to 256 codes (assuming 256 mV) is outputted to perform this BLC operation. Reverse signal) is selected. Since blc_onb, the BLC compensation operation signal, is opened, an additional current of 256uA flows to meet the resistance (assuming 1K ohm), so the vin_bot level, which is the output signal of the current DAC1 (20), is increased by 256mV from the initial low level. Will print

8 shows an operation timing diagram of a column parallel ADC using a preamplifier having a black level compensation device according to the first embodiment. In particular, it shows how px_en, blc_onb, and vin_bot change to perform a black level compensation (BLC) operation.

When the pixel data is taken out through Tx (①), the vin_pre signal is combined with the accumulated signal and the signal generated by the dark current according to the high temperature, and outputs (②). At this time, the vin_pre signal is combined with the dark current signal + the video signal and outputted, so that the output is multiplied by the gain of the preamplifier 12.

After the vin_pre signal that is the output of the preamplifier 12 is settled, px_en (pixel enable signal) is turned off to be separated from the pixel 11 (3).

After the BLC compensation operation signal blc_onb transitions to the low level (4), the vin_bot signal (current DAC1 (20)) corresponds to the OB signal OBb <n: .0>, which is the output digital signal of the previously read OB pixel. ) Will raise the level (⑤).

The vin signal is also raised by the vin_bot signal, and vin_pre lowered to the opposite phase through the preamp gain is output (6).

In the state where the qsig signal is connected, the output signal of the preamplifier 12 is transmitted to vin_sig (⑦).

The vin_sig to which the black level compensation (BLC) is applied falls while having the slope while the vramp_cds of FIG. 1 performs the ramp operation (8). The code corresponding to the point of intersection with the vin_rst signal is sent to the final output of the column parallel ADC 1 (⑨).

9 is a circuit diagram illustrating a preamplifier front end of a thermal parallel ADC having a black level compensation device according to a second embodiment of the present invention, and FIG. 10 is provided with a black level compensation device according to a third embodiment of the present invention. FIG. 11 is a circuit diagram illustrating a preamplifier front end of one column parallel ADC, and FIG. 11 is an exemplary diagram illustrating an implementation of the current DAC2 included in the black level compensation device according to the second and third embodiments, and FIG. 12 is a temperature sensor and phosphorus using the same. A diagram showing an enable signal.

9 and 10, a circuit for removing only an output component generated by a dark current using a sink transistor Sink TR is illustrated.

Current DAC2 60 is a block that biases the VCON signal to operate the sink transistor with the appropriate current.

The vin signal (especially the vin current) is constantly raised by the dark current at high temperatures.

Therefore, if the enable transistor is connected as shown in FIG. 9 or the switch is connected as shown in FIG. 10, and a proper sink is performed during the period in which the enable signal (en signal) is floating, it is generated by dark current. Thus, the amount of signal amplified by the preamplifier 12 can be minimized.

Referring to Fig. 11, the configuration of the current DAC2 60 is shown.

According to the bias signal generated according to the reference current source, when Rb <n: 0> is properly adjusted with a resistor, a proper signal VCON signal can be generated.

Here, the bias signal can be made through a constant voltage (current) generator (eg, band gap, widlar voltage, current source). The bias transistors operated by the bias signal may flow currents having different levels (for example, current levels increasing by 2 times) similarly to the current distributor 42 shown in FIG. 6.

The Rb signal can be designed with registers that can be set via a chip controller. That is, the Rb signal is a value that can be set by the user by predicting the amount corresponding to the ADC output value of the OB pixel in advance. For example, if the dark current is 100mA in the currently developed product, the Rb signal may be set through pre-prediction to compensate for the amount of the dark current predicted in advance.

This signal is radiated to the input of the sink transistor, which depends on every column, to eliminate the signal generated by the dark current.

Referring to FIG. 12, the enable signal for operating the enable transistor may be generated by triggering an output of the temperature sensor to operate at a predetermined temperature.

For example, the bandgap reference generator may be expressed as a sum of VPTAT proportional to temperature and VCTAT inversely proportional to temperature. Here, VPTAT is a voltage that increases in proportion to the temperature using the BJT, VCTAT is a voltage that increases in inverse proportion to the temperature using the BJT.

A temperature sensor may be provided to enable the enable signal to be generated at a predetermined temperature using the VPTAT signal generated in the band gap.

Here, the temperature is specified to enable the setting according to the user. For example, products that are vulnerable to dark currents can operate at relatively low temperatures (eg 60-70 degrees), and products that are rather robust to dark currents can be operated at relatively high temperatures (eg 100 degrees or more). There will be.

Although the above has been described with reference to embodiments of the present invention, those skilled in the art may variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. And can be changed.

1: Thermal Parallel ADC 11: Pixels
12: preamplifier 13: comparator
14: memory 20: current DAC1
30: low level output unit 40: OB current conversion unit
50: BP signal output unit 60: current DAC2

Claims (15)

A black level compensation device included between a pixel and a preamplifier of a column parallel analog-to-digital converter (Column Parallel ADC) for digitally converting a pixel signal, which is an analog signal,
A compensation capacitor Cb having one end connected between an output terminal of the pixel and a negative input terminal of the preamplifier; And
And a current DAC1 connected to the other end of the compensation capacitor (Cb) and outputting a bottom plate (BP) voltage corresponding to an optical black (OB) signal.
The method of claim 1,
The current DAC1 inputs a digitized OB signal and a black level compensation (BLC) operation signal, converts the OB signal into an OB current which is an analog signal having a corresponding magnitude, and then converts the OB current according to the BLC operation signal. The black level compensation device of a column parallel ADC, characterized in that for changing the BP voltage of the compensation capacitor reflected.
The method of claim 1,
The current DAC1,
A low level output unit configured to output a predetermined low level voltage;
An OB current converter configured to control on / off of a transistor according to a bit value of the OB signal to convert the OB signal into an OB current having a corresponding magnitude; And
Initially, the output of the low level output unit is output as the BP voltage of the compensation capacitor, and the BP voltage is output corresponding to the magnitude of the OB current converted by the OB current converter according to a black level compensation (BLC) operation signal. Black level compensation device of a column-parallel ADC comprising a BP signal output to change the size of.
Claim 4 has been abandoned upon payment of a setup registration fee. The method of claim 3,
The low level output unit has a VDD voltage applied to a source terminal, and a drain terminal connected to an output terminal of the BP signal output unit, and includes a LL transistor turned on by a bias voltage applied to a gate terminal. ADC's black level compensation device.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 3,
When the OB signal is a binary (n + 1) bit signal,
The OB current converter,
And a number of bit position (BL) transistors corresponding to the number of bits (n + 1) of the OB signal, wherein the BL transistors are controlled on / off according to bit values assigned to each bit position of the OB signal. A bit value linking unit;
A current distribution including (n + 1) bit digit (BV) transistors 1: 1 matched to each of the BL transistors and configured to flow a current having a level corresponding to a bit digit corresponding to the matched BL transistors Black level compensation device of a thermal parallel ADC comprising a part.
Claim 6 has been abandoned upon payment of a setup registration fee. The method of claim 5,
Among the BV transistors, the (k + 1) th BV transistor corresponding to the kth bit in the OB signal includes ^{2k + 1} current output (CL) transistors to which a predetermined bias voltage is applied to a gate terminal.
Black level compensation device of a column-parallel ADC characterized by being able to flow 2 ^k times the current compared to the first BV transistor.
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6,
A bit value of a corresponding bit position among the OB signals is input to the BL transistor, and when the bit value is '0', the bit value is turned on, and when the bit value is '1', the BL transistor is turned off.
And the OB signal is an inverted code in which an OB code, which is a digital output value of an optical black pixel, is inverted.
Claim 8 has been abandoned upon payment of a set-up fee. The method of claim 7, wherein
The BL transistor has a common gate structure in which gate terminals are connected to each other.
The OB current converter may control (n + 1) BL transistors individually on / off according to the bit value of the OB signal, and the current of the level corresponding to the bit position corresponding to the bit value of '0' is summed. And the OB signal is introduced into the BP signal output unit.
Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8,
The BP signal output unit,
A BLC transistor in which the OB current flows into a source terminal, a drain terminal is connected to the output terminal, and a BLC operation signal is applied to a gate terminal;
And a resistor connected between the drain terminal and the ground of the BLC transistor.
Claim 10 has been abandoned upon payment of a setup registration fee. The method of claim 9,
The BLC transistor is turned on when the BLC operation signal transitions from high to low so that the OB current flows to the drain terminal, and the OB current meets the resistance to raise the level of the BP signal. Black level compensation device in parallel ADC.
Claim 11 was abandoned upon payment of a set-up fee. A black level compensation device implemented in a preamplifier in a column parallel ADC structure using a preamplifier,
A switch once connected to the output of the pixel; And
Comprising one end is connected between the other end of the switch and the input terminal of the preamplifier,
And an output of the pixel is input at one end of the compensation capacitor, and a black level compensation level is input at the other end of the compensation capacitor.
Claim 12 was abandoned upon payment of a set-up fee. The method of claim 11,
And the other end of the compensation capacitor connects a current DAC1 and a resistor to adjust the black level compensation level.
Claim 13 was abandoned upon payment of a set-up fee. The method of claim 12,
And the current DAC1 receives an OB signal, which is an ADC output signal read from an optical black pixel, and a signal indicating a black level compensation operation.
A black level compensation device implemented in a preamplifier in a column parallel ADC structure using a preamplifier,
A sink transistor and an enable transistor connected between an output terminal of the pixel and an input terminal of the preamplifier,
And the enable transistor is turned on by an enable signal generated by triggering an output of a temperature sensor.
The method of claim 14,
The sink transistor is operated by the VCON signal,
The VCON signal is generated by a current copy circuit, the black level compensation device characterized in that the bias level of the VCON signal is adjusted by adjusting the resistor.

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