KR102009458B1 - Method for measuring total ionizing dose effect of ranmdom access memory using fully depleted silicon on insulator process - Google Patents

Abstract

The present invention relates to a semiconductor memory device, an electronic circuit device using the semiconductor memory device, and a method for measuring the total ionizing dose effect for the device. The method of measuring the total ionizing dose effect may include a step of irradiating radiation to a cell or a semiconductor storage device including the cell, wherein the cell comprises six field effect transistors at least two of which are electrically connected; and a step of counting a failure occurring in at least one of the six field effect transistors according to the irradiation of the radiation, wherein the failure comprises at least one of a failure in a hold operation, a failure in a read operation, and a failure in a write operation.

Description

METHOD FOR MEASURING TOTAL IONIZING DOSE EFFECT OF RANMDOM ACCESS MEMORY USING FULLY DEPLETED SILICON ON INSULATOR PROCESS}

A method of measuring the total ionization dose effect on the stability of a memory device using a fully depleted silicon on insulator process.

Radiation from the outside can cause various problems in electronic components. In particular, semiconductors and integrated circuits using the same are vulnerable to the effects of radiation, and their performance gradually decreases when exposed to these radiations.

The degradation of the semiconductor or integrated circuit due to such radiation may be explained through a total ionizing dose (TID) effect or a single event effect (SEE). The total ionization dose effect is that when radiation is applied, a hole is formed on the oxide in the semiconductor to which radiation is applied, and as a result, a threshold voltage in the semiconductor is changed to generate a leakage current, thereby causing damage, destruction or alteration of the semiconductor. It means to induce. According to the total ionizing dose effect, components such as transistors are threatened with stability and reliability in an environment where radiation is applied. The single event effect means that when radiation is applied, the applied radiation creates an electron major pair in the semiconductor, leading to an unintended pulse current in the semiconductor. Accordingly, the semiconductor may be damaged, destroyed, or changed in data.

Due to the influence of radiation on such semiconductors, there is an increasing demand for improving the radiation resistance capability of semiconductors and the like in recent years. In particular, semiconductors and the like have been more affected by a small amount of radiation due to the recent miniaturization of the process, which further increases the need for improving radiation resistance performance of semiconductors or memory devices using the same.

For the efficient design and fabrication of semiconductors, integrated circuits, or other devices, a method for measuring the total ionization dose effect that enables the measurement of the effect of total ionization dose on a memory device using a fully depleted silicon on insulator process. Let's solve the problem.

In order to solve the above problems, a method of measuring the total ionization dose effect on the stability of a memory device using a fully depleted silicon on insulator process is provided.

A method of measuring the total ionization dose effect includes irradiating radiation to a cell or a semiconductor storage device including the cell, wherein the cell comprises six field effect transistors at least two of which are electrically connected; And counting a failure occurring in at least one of the six field effect transistors, wherein the failure includes at least one of a failure in a hold operation, a failure in a read operation, and a failure in a write operation. have.

The six field effect transistors include a first field effect transistor including a p field effect transistor that can be turned off, a second field effect transistor that includes a p field effect transistor that can be turned on, and the first field effect transistor. A third field effect transistor including an n field effect transistor corresponding to the second field effect transistor and a fourth field effect transistor corresponding to the second field effect transistor and set to an off state. Can be.

The first field effect transistor and the fourth field effect transistor may be set to an off state, and the second field effect transistor and the third field effect transistor may be set to an on state.

Counting the failure generated in at least one of the six field effect transistors in accordance with the irradiation of the radiation, at least one of the first to fourth field effect transistors in accordance with the irradiation of the radiation under a stress pattern At least one of counting a failure occurring and counting a failure occurring in at least one of the first field effect transistor or the fourth field effect transistor in response to the irradiation of the radiation under a pattern opposite to the stress pattern. can do.

The method of measuring the total ionization dose effect may further include performing a T-cad simulation on at least one of the first to fourth field effect transistors.

The method for measuring the total ionization dose effect is based on the T-cad simulation, whereby the electric field directions formed in the buried oxide of each of the first field effect transistor in the on state and the third field effect transistor in the on state are opposite to each other. The method may further include obtaining a result in which the second field effect transistor in an on state and the electric field direction formed in the buried oxide of each of the fourth field effect transistor in the on state are opposite to each other.

The method for measuring the total ionization dose effect may include setting at least one of the first field effect transistor to the fourth field effect transistor to at least one of an on state and an off state, and the first field effect transistor to the fourth electric field. The method may further include obtaining an energy band diagram of one surface cut in the vertical direction in the middle of the channel with respect to at least one of the effect transistors.

In the method for measuring the total ionization dose effect, the effect of the total ionization dose for the first field effect transistor or the second field effect transistor is based on the total ionization dose for the third field effect transistor or the fourth field effect transistor. The method may further include obtaining a result larger than the influence on the result.

The effect of the total ionization dose on the first field effect transistor or the second field effect transistor is greater than the effect on the total ionization dose on the third field effect transistor or the fourth field effect transistor. The step may include obtaining a result that the stability of the read operation, the hold operation, and the write operation of the first field effect transistor or the second field effect transistor decreases according to the influence of the total ionization dose.

The method of measuring the total ionizing dose effect may further comprise performing a mixed mode simulation on the voltage transfer curve for each of the irradiated and non-irradiated cases.

The method of measuring the total ionization dose effect may further comprise obtaining a transient output curve for writing 1 and 0, for the case where the cell has a fixed oxide density voltage.

The field effect transistor may be manufactured based on a fully depleted silicon on insulator process. The semiconductor memory device corresponds to a first field effect transistor including a p field effect transistor that can be turned off, a second field effect transistor that includes a p field effect transistor that can be turned on, and the first field effect transistor. A third field effect transistor comprising an n field effect transistor set in an on state and a fourth field effect transistor comprising an n field effect transistor corresponding to the second field effect transistor and in an off state, the fourth field effect transistor comprising: At least one of the first field effect transistor and the second field effect transistor may be one in which hold, read, and write operations are affected by the total ionization dose.

According to the measurement method of the total ionization dose effect described above, it is possible to measure the total ionization dose effect on the memory device using the fully depleted silicon-on-insulator process, and thus a semiconductor, integrated circuit, or various types having excellent radiation resistance performance. Efficient design and fabrication of the device becomes possible.

By using the measurement results according to the method for measuring the total ionization dose effect described above, it is possible to implement a semiconductor memory device or an electronic circuit having excellent radiation resistance while minimizing the influence on the total ionization dose.

By using the result of the measurement by the method for measuring the total ionization dose effect described above, it is possible to fabricate a semiconductor, etc., which is resistant to radiation, thereby prolonging the life of the semiconductor or the integrated circuit. The economic effect of reducing the maintenance cost of various devices (computing devices, mobile devices, display devices, household appliances, machine tools, aircraft, spacecraft and / or nuclear power generation devices, etc.) can also be obtained.

1 is a circuit diagram of an embodiment of a semiconductor memory device.
2 is a side cross-sectional view of one embodiment of a field-effect transistor (FET).
FIG. 3 is a graphical depiction of the experimental results for the pattern opposite to the overall bit failure and stress pattern of the hold operation for the biased SRAM (SRAM) in the stress pattern during radiation exposure.
FIG. 4 is a graphical representation showing experimental results for patterns that are opposite to the overall bit failure and stress patterns of read operations in stress patterns for stressed SRAMs in stress patterns during radiation exposure.
FIG. 5 is a graphical representation showing experimental results for patterns that are opposite to the overall bit failure and stress patterns of write operations for biased SRAMs in stress patterns during radiation exposure.
FIG. 6 illustrates an example of a T-cad (T-CAD, Technology CAD) simulation result for an electrostatic field when the first field effect transistor is in an off state.
FIG. 7 illustrates an example of a T-cad simulation result for an electrostatic field when the second field effect transistor is in an on state.
FIG. 8 illustrates an example of a T-cad simulation result for an electrostatic field when the third field effect transistor is in an on state.
FIG. 9 illustrates an example of a T-cad simulation result for an electrostatic field when the fourth field effect transistor is in an off state.
10 is an example of an energy band diagram for an n field effect transistor and a p field effect transistor, respectively, in an on state and an off state under conditions biased by irradiation.
11 is a graph showing an example of the vertical component of the electric field around the buried oxide interface for the p field effect transistor in the on state and the p field effect transistor in the off state.
FIG. 12 is a graph showing an example of a mixed mode simulation result of a voltage transfer curve (VTC) between irradiation and non-irradiation.
FIG. 13 is a graph showing an example of a transient output curve for the writing of 1 and 0 in cells with the same fixed oxide density voltage.
14 is a flowchart of one embodiment of a method of measuring the total ionization dose effect of a semiconductor memory device.

Like reference numerals refer to like elements throughout the specification unless otherwise specified. As used herein, the term “parts” added may be implemented in software or hardware. According to an embodiment, “parts” may be implemented as one component or one “part” may be implemented as a plurality of components. It is also possible.

When a part of the specification is connected to another part, it may mean a physical connection or an electrically connected according to the part and the other part. In addition, when a part includes another part, unless otherwise stated, it does not exclude another part other than the other part, it means that it may further include another part at the designer's choice. do.

The terms "first" and "second" are used to distinguish one part from another part, and unless otherwise specified, they do not mean sequential expressions. In addition, singular expressions may include plural expressions unless the context clearly indicates an exception.

Hereinafter, an embodiment of an electronic circuit device including a semiconductor storage device and a semiconductor storage device will be described with reference to FIGS. 1 to 12.

1 is a circuit diagram of an embodiment of a memory device.

The semiconductor storage device 1 may include, for example, 6 transistor ESRAM (hereinafter referred to as 6T-ESRAM). As shown in FIG. 1, the 6T-SRAM may include at least one cell 2 provided with a plurality of transistors 10 to 60.

According to an embodiment, at least one cell 2 may include six transistors 10 to 60. Each of the six transistors 10 to 40 may be implemented using a field effect transistor, and more specifically, each of the field effect transistors 10 to 60 may be, for example, a silicon-on insulator (SOI). It may be an Insulator or MOSFET (MOSFET), each of the field effect transistor (10 to 60) in the cell (2), respectively, the first field effect transistor (10), It is referred to as a two field effect transistor 20, a third field effect transistor 30, a fourth field effect transistor 40, a fifth field effect transistor 50, and a sixth field effect transistor 60.

In example embodiments, each of the first field effect transistor 10 and the second field effect transistor 20 may be a p field effect transistor (pFET). On the contrary, each of the third field effect transistor 30 and the fourth field effect transistor 40 may be an n field effect transistor (nFET). According to an embodiment, on the contrary, the first field effect transistor 10 and the second field effect transistor 20 are n field effect transistors, and the third field effect transistor 30 and the fourth field effect transistor 40 are p. It may also be a field effect transistor. In addition, the fifth field effect transistor 50 and the sixth field effect transistor 60 may also be n field effect transistors or p field effect transistors.

The first field effect transistor 10 and the third field effect transistor 30 may be electrically connected to each other through a conductor such as a circuit or a conductive line. In this case, the first field effect transistor 10 and the third field effect transistor 30 may be connected to each other through a drain and a source. In addition, the gates of each of these 10, 30 may be interconnected through predetermined circuit lines. The second field effect transistor 20 and the fourth field effect transistor 40 may also be electrically connected to each other through a conductor such as a circuit or a conductive line in the same manner.

A portion (hereinafter, referred to as a first inverter) including a first field effect transistor 10 and a third field effect transistor 30, a second field effect transistor 20, and a fourth field effect transistor 40 are included. The portion 4 (hereinafter referred to as a second inverter) may be coupled to each other crosswise.

)과 전기적으로 연결될 수 있다.The circuit line connecting the first field effect transistor 10 and the third field effect transistor 30 and the circuit line connecting the second field effect transistor 20 and the fourth field effect transistor 40 are respectively read. And a bit line BL to which data for a write operation is transmitted.

) Can be electrically connected.

)과, 제1 전계 효과 트랜지스터(10) 및 제3 전계 효과 트랜지스터(30)를 연결하는 회로 라인 사이에 설치되어, 이들 사이의 연결을 제어할 수 있다. 마찬가지로 제6 전계 효과 트랜지스터(60)는 비트 라인(BL)과, 제2 전계 효과 트랜지스터(20) 및 제4 전계 효과 트랜지스터(40)를 연결하는 회로 라인에 설치되어, 이들 사이의 연결을 제어할 수 있다. 제5 트랜지스터(50) 및 제6 트랜지스터(60)는 각각 워드 라인(Word Line)과 전기적으로 연결되어 마련될 수 있다.The fifth field effect transistor 50 has a bit line (

) And a circuit line connecting the first field effect transistor 10 and the third field effect transistor 30 to control the connection therebetween. Similarly, the sixth field effect transistor 60 is provided in a circuit line connecting the bit line BL and the second field effect transistor 20 and the fourth field effect transistor 40 to control the connection therebetween. Can be. The fifth transistor 50 and the sixth transistor 60 may be electrically connected to a word line, respectively.

2 is a side cross-sectional view of one embodiment of a silicon on insulator field effect transistor.

Referring to FIG. 2, the above-described field effect transistors 10 to 60, for example, the first field effect transistor 10 may include a fully depleted silicon on insulator (FD-SOI). It may be manufactured based on a process (eg, a 28 nm fully depleted silicon on insulator process).

When the first field effect transistor 10 is implemented by employing a fully depleted silicon on insulator element, the first field effect transistor 10 is, for example, an n-type substrate 11 and an n-type substrate 11. Buried oxide (12, BOX, Buried Oxide) formed by being stacked on the buried oxide, source 13 and drain (14) provided spaced apart from each other on the buried oxide (12), the source 13 and the drain ( 14 may include a gate 15 that creates a flow of charge between them.

The n-type substrate 11 may be implemented using a silicon substrate, and operate as an n-type semiconductor. The thickness of the n-type substrate 11 may be, for example, 7 nm, but it is arbitrarily determined, and the designer may manufacture the n-type substrate 11 in various thicknesses according to the intention.

The buried oxide 12 is mounted on one surface of the n-type substrate 11, and the other surface opposite to the one surface may be exposed to the outside or combined with another device (eg, a metal wire or a substrate).

The buried oxide 12 is provided to block electrons or holes passing through the channel 11-1 from leaking to the outside (for example, the p-type substrate 11). A source 13 and a drain 14 forming a p + region are provided on one surface of the buried oxide 12, and the other surface opposite to the surface is mounted in contact with one surface of the n-type substrate 11. The thickness of the buried oxide 12 may be, for example, 28 nm, but is not limited thereto.

Each of the source 13 and the drain 14 is installed and mounted insulated from one side of the buried oxide 12. In the first field effect transistor 10, the source 13 and the drain 14 operate as a p-type semiconductor. A channel 11-1 is formed between the source 13 and the drain 14. The channel 11-1 is also formed in contact with one surface of the buried oxide 12. Channel 11-1 provides a path of charge transfer between source 13 and drain 14.

The channel 11-1 is provided with a gate 15, and charges are transferred between the source 13 and the drain 14 according to the voltage applied to the gate 15. As described above, the electric charge is transmitted through the channel 11-1. The gate 15 may be implemented using an oxide, in which case the thickness of the gate oxide may be, for example, 1 nm. However, the thickness of the gate oxide may also be variously determined according to the designer's intention.

In addition, the first field effect transistor 10 may use a conventional well type back-gate as a back-gate. For example, an n-well may be employed.

Like the first field effect transistor 10, the second field effect transistor 20 may be implemented based on a fully depleted silicon on insulator process. For example, the second field effect transistor 20 may also include an n-type substrate, buried oxide, a source portion, a gate portion, a channel portion, and a drain portion in the same or partially modified form as the first field effect transistor 10. Can be.

Meanwhile, the third and fourth field effect transistors 30 and 40 may also be implemented based on a fully depleted silicon on insulator process. However, unlike the first and second field effect transistors 10 and 20, the third and fourth field effect transistors 30 to 40 include a p-type substrate instead of an n-type substrate, and have a source portion and a drain. The part may be implemented by n + region instead of p + region. That is, the source and drain portions of the third and fourth field effect transistors 30 to 40 operate as n-type semiconductors. In addition, for the third and fourth field effect transistors 30 to 40, a p-well type back gate may be used instead of the n-well type.

The fifth and sixth field effect transistors 50 and 60 may also be implemented based on a fully depleted silicon on insulator process, and according to embodiments, the third and fourth field effect transistors 30 to 40 In the same manner, the p-type substrate and / or the p-well type back-gate may be implemented, and the source and drain portions may be implemented in the n + region. Accordingly, the source and drain portions of the fifth and sixth field effect transistors 50 and 60 also operate as n-type semiconductors.

In addition, since the specific structures of the second to sixth field effect transistors 20 to 60 are the same as or substantially similar to the first field effect transistor 10 described above, a detailed description thereof will be omitted.

When transistors 10 to 60 are implemented using a fully depleted silicon-on-insulator process, the hold, read and write stability of the semiconductor storage device 1 (e.g. 6T-SRAM) of the static memory cell is total ionized. It changes in response to dose.

Hereinafter, a bias dependency according to the total ionization dose of the semiconductor storage device 1 will be described with reference to FIGS. 3 to 5, but the semiconductor of the static memory cell including the first to sixth field effect transistors 10 to 60 is described. The storage device 1 is irradiated with radiation and described based on an experimental result of at least one operation failure of the first to sixth field effect transistors 10 to 60 due to irradiation. Here, the operation of each of the transistors 10 to 60 may include a hold operation, a read operation, and / or a write operation.

In order to perform an experiment on at least one of the semiconductor storage device 1 or the transistors 10 to 60 of the static memory cell, for example, the first to fourth transistors 10 to 40, for example, two Branch data patterns may be used. Here, the data pattern may include a data pattern (hereinafter referred to as a stress pattern) used in the radiation stress and a data pattern (hereinafter referred to as an opposite pattern) that is mutually secure to the stress pattern.

3 to 5 each show the experimental results for the opposite pattern opposite to the stress pattern and the failure of the hold operation, the read operation and the write operation in the stress pattern for the SRAM (SRAM, Static RAM) biased during the radiation exposure. It is a graph drawing sequentially. 3 to 5, the x-axis represents the total ionization dose Krad (SiO ₂ ), and the y-axis is the number of hold failures, read failures, and write failures sequentially measured. The solid lines of FIGS. 3 and 4 connect the number of failures measured in the same pattern (stress pattern) as the bias pattern during irradiation according to the total ionizing dose, and the dotted line indicates the bias pattern during irradiation according to the total ionizing dose. It is the concatenation of the number of failures in the opposite pattern.

The experimental results of FIGS. 3 to 5 specifically show that the semiconductor storage device 1 or the cell 2 is formed using a Co-60 isotope having a dose rate of 10 krad (SiO 2) / hour as a radiation source. During irradiation, the number of hold, read, and write failures was recorded every four hours. While the biased irradiation is performed, the stress voltage is obtained with the technical nominal voltage maintained at 1V (ie, V _{dd, stress} = 1V). Also, so that the number of failures can be counted more clearly, the test voltage for the hold operation is set to 0.35V, and the test voltage for the read operation and the test voltage for the write operation are equally set to 0.5V (that is, Vdd, Hold = 0.35V, Vdd, Read = 0.5V and Vdd, Write = 0.5V). Hold stability In addition, the frequencies were all set to 100 KHz equally. The analysis was performed after stopping at the voltage of V _{dd, hold} for 2 msec. In addition, irradiation bias dependency is such that the first and third field effect transistors 10 and 30 are kept low (Q = 0) while the irradiation is performed, and the second and third The four field effect transistors 20 and 40 were analyzed after maintaining the high state (Q = 1). Here, the low state includes a case in which the first field effect transistor 10 is in an off state Poff, and the third field effect transistor 30 corresponding thereto is in an on state Non. The field effect transistors 20 and 40 in the high state are biased opposite to each other. For example, when the second field effect transistor 20 is in an on state, the fourth field effect transistor 40 is biased in an off state. Meanwhile, in the analysis process, bit flips that occur accidentally while operating in the stress mode may be compensated by scrubbing data with a predetermined stress pattern every 20 minutes. The total time used for the scrubbing and count failure bits was designed not to exceed 10 minutes. As a result, the time spent on scrubbing and counting failure bits can be ignored as compared to the stress time of 20 hours. Of course, the experimental conditions of the designer or the experimenter can be changed according to the situation.

3 to 5, it is possible to determine the bias dependency on the total ionization dose in two data patterns (ie, a pattern opposite to a stress pattern). The number of failures in all operations (hold operation, read operation and write operation) tends to increase with the total ionization dose. Referring to the solid and dashed lines shown in Figs. 3 to 5, the number of failures in all operations depends on the data pattern. However, in the case of a read operation, unlike a write operation or a hold operation, the failure when performed under the opposite pattern is measured similar to the stress pattern, and the failure when performed under the stress pattern is similar to the opposite pattern. Was measured. In this regard, it can be seen that an imprint effect appears when a hold fails or a read fails, whereas an inverse imprint effect appears when a write fails with reference to FIG. 5. In other words, an imprint effect is observed for hold and read stability while an inverse imprint effect is observed for write stability.

In this case, if the T-cad simulation is performed, the above-described measurement results can be analyzed.

6 to 9 show T-cad simulations of the respective field effect transistors 10 to 40 when the semiconductor storage device 1 of the static memory cell using the silicon on insulator process has a value of 1 stored therein. As a result, specifically, the first field effect transistor 10 in the off state, the second field effect transistor 20 in the on state, the third field effect transistor 30 in the on state, and the fourth field in the off state. One example of T-cad simulation results for the electric field of the effect transistor 40 is shown in sequence. Each color represents the magnitude of the electric field. The closer to red, the relatively stronger the field, and the closer to blue, the weaker the field.

As illustrated in FIG. 6, when the first field effect transistor 10 (p field effect transistor) is in an off state, the n-type substrate 11, the source 13, and the gate of the first field effect transistor 10 ( 15) A voltage of 1V may be applied to each, and a voltage of 0V may be formed in the drain 14. In this case, the electric field is formed relatively strongly in the region adjacent to the n-type substrate 11 and the source 13 in the buried oxide 12, and relatively weak in the region adjacent to the drain 14. Is formed. In other words, the closer the drain 14 is, the weaker the electric field is.

In the case of the second field effect transistor 20 (p field effect transistor) in the on state (for example, a voltage of 1 V is applied to the n-type substrate 21, the source 23, and the drain 24, and the gate 25 is applied. In the case where 0 V is applied), as shown in FIG. 7, the electric field is uniformly distributed throughout the buried oxide 22 without showing a specific direction.

In the case of the third field effect transistor 30 (n field effect transistor) in the off state, as shown in FIG. 8, the electric field exhibits a generally uniform distribution without directivity in the buried oxide 32. In the off state, a voltage of 0 V may be applied to each of the p-type substrate 31, the source 33, and the drain 34 of the third field effect transistor 30, and a voltage of 1 V may be applied only to the gate 35. have.

Meanwhile, as shown in FIG. 9, the electric field in the buried oxide 42 of the fourth field effect transistor 40 (n field effect transistor) set to the on state is a region in which the p-type substrate 41 and the drain 44 are located. However, it is relatively strong at the periphery thereof and, on the contrary, is relatively weakly formed at the periphery of the region in which the source 43 is located. In other words, the closer the source 43 is, the weaker the electric field is. In this case, a voltage of 0 V may be applied to the p-type substrate 41, the source 43, and the gate 45 of the fourth field effect transistor 40, and a voltage of 1 V may be applied to the drain 44.

In other words, the buried in each of the second field effect transistor 20 in the on state (that is, the p field effect transistor in the on state) and the third field effect transistor 30 in the on state (that is, the n field effect transistor in the on state) is embedded. The direction of the electric field of the oxide is formed opposite to each other.

When electron hole pairs are generated by radiation in the oxides 12, 22, 32, and 42, the holes tend to remain at a fixed oxide charge (Not). On the other hand, electrons are lost due to their light effective mass. Therefore, considering the above, it can be seen that the electric field attracts holes near the interface of the back channel, thereby accelerating the effect of the total ionization dose.

The direction of the electric field affecting the total ionization dose can be more clearly explained by the energy band diagram for one face obtained by cutting in the vertical direction in the middle of the channel.

10 is an example of an energy band diagram for an n field effect transistor and a p field effect transistor, respectively, in an on state and an off state under conditions biased by irradiation. In FIG. 10, the x axis represents height (nm) and the y axis represents energy band (eV). In addition, the red line means an energy band in the p field effect transistor (for example, the first field effect transistor 10 and the second field effect transistor 20), and the blue line indicates the n field effect transistor (for example, the third field field). The energy band in the effect transistor 30 and the fourth field effect transistor 40 is meant. The solid line means the on state and the dotted line means the off state.

Referring to FIG. 10, the energy band of the p field effect transistor (eg, the second field effect transistor 20) is formed such that the positive charge accumulates to the extent required by the interface around the buried oxides 12 and 22. Specifically, for example, the potential gradients of the n field effect transistors (for example, the third field effect transistor 30 and the fourth field effect transistor 40) may change the hole from the interface regardless of whether it is on-state or off-state. While formed to push away, the potential gradient of buried oxide 22 of second field effect transistor 20 is formed to attract holes close to the back channel interface. Therefore, for both the on-state and off-state, the first and second field effect transistors 10, 20 deteriorate more than the on-state and off-state of the third and fourth field effect transistors 30, 40. do. In view of this, the lowering of the driving current is more important than the third and fourth field effect transistors 30 and 40 in the first and second field effect transistors 10 and 20 in the silicon on insulator. .

11 is a graph showing an example of the vertical component of the electric field around the buried oxide interface for the p field effect transistor in the on state and the p field effect transistor in the off state. Specifically, FIG. 11 shows the vertical component of the electric field Fy around the cut plane of the buried oxide interface cut in the source, channel and drain directions (ie, in the longitudinal direction of the channel). In FIG. 11, the x axis represents a width (nm) and the y axis represents an energy band (x10 ^ 6 V / cm). In addition, the solid line means the vertical component of the electric field with respect to the p field effect transistor (for example, the second field effect transistor 20) in the on state, and the dotted line indicates the p field effect transistor (for example, the first field effect transistor in the off state). (10) means the vertical component of the electric field.

As shown in FIG. 11, the vertical component of the electric field for the p field effect transistor 10 in the off state is higher than the vertical component of the electric field for the p field effect transistor 20 in the on state. It is relatively strong near, but relatively weaker near drains 14 and 24. In this case, considering the imprint effect of FIGS. 3 and 4, the stress condition is relatively worse than that of the p field effect transistor 10 in the off state and the p field effect transistor 10 in the off state. In addition, the pull-up intensity of the p-field effect transistor 20 in the on state is relatively weaker than the pull-up intensity of the p-field effect transistor 10.

12 is a graph illustrating an example of a mixed mode simulation result of a voltage transfer curve (VTC) between irradiation and non-irradiation. In FIG. 12, black is an example of voltage transfer curves for the field effect transistors 10 to 40 in the semiconductor storage device 1 or the cell 2 in the absence of radiation, and red is a case where radiation is irradiated. An example of a voltage transfer curve. In addition, the voltage transfer curve H (VTC _H ) and the voltage transfer curve L (VTC _L ) are respectively the voltage transfer curve at the high output connected to the p field effect transistor 20 in the on state and the p field effect transistor 10 in the off state. Voltage transfer curve at the low output connected to.

Hold stability and read stability are correlated with hold static noise margin (SNM) and read static noise margin, which are distorted by the total ionization dose. This distortion of static noise margin is also found in bulk SRAMs, but its mechanism of operation is different from that of a fully depleted silicon on insulator SRAM. In the case of bulk SRAMs, the total ionization dose tends to increase the driving and leakage currents of the n field effect transistor to enhance pull-down.

As shown in FIG. 12, when the mixed mode simulation is performed on the voltage transfer curve, the distortion of the static noise margin can be visualized, thereby enabling an intuitive and specific grasp of the distortion. The positive charge density produced is proportional to the total ionization dose. For this reason, if higher positive charges are added in the regions of the buried oxides 12 and 22, the performance is further degraded. Therefore, as shown in FIG. 12, the left shift of the voltage transfer curve H caused by the p field effect transistor 20 in the on state is the voltage transfer curve L due to the p field effect transistor 10 in the off state. It is larger than the lower side shift of, which causes the static noise margin H to be smaller than the static noise margin L. Because of this, as shown in Figures 3 and 4, hold and read bit failures increase with the total ionization tendency.

FIG. 13 is a graph showing an example of a transient output curve for writing 1 and 0 in a cell with a fixed oxide density voltage. In FIG. 13, the black line is a transient output curve when 1 and 0 are written for cells having the same fixed oxide charge in the buried oxide of the field effect transistor in the on state and the off state, and the red line is the on state and the off state. Transient output curve when 1 and 0 are written for a cell with a larger fixed oxide charge in the buried oxide of the field effect transistor in the state.

The write failure may be analyzed through timing simulation as shown in FIG. 13. As described above, the p field effect transistors 10 and 20 tend to be weakened due to the total ionization dose in a fully depleted silicon on insulator. Unlike the hold stability and the read stability, the weakened p field effect transistors 10 and 20 were expected to improve the write stability. This is because the write stability of the six transistor SRAM is determined by the competition between the pull-up p field effect transistor and the access n field effect transistor. However, according to the timing simulation results described above, the weakened p-field effect transistors 10 and 20 decrease the rise time of the memory node that changes the value written from 0 to 1, and thus the write stability is lowered as expected. Will appear. In addition, the pull-up intensity of the p-field effect transistor 20 in the on state becomes weaker than the pull-up intensity of the p-field effect transistor 10 in the off state. As a result, the rise time required to bring the drain node of the p field effect transistor 20 in the on state to the high state is the rise time required to bring the drain node of the p field effect transistor 10 in the off state to a high state. It becomes even slower, and as a result, as shown in FIG. 5, an inverse imprint effect in the writing process occurs.

Total ionization dose reduces the stability of the SRAM. In particular, the total ionization dose effect on SRAM using a 28 nm fully depleted silicon on insulator has a more significant significance compared to the total ionization dose effect on bulk CMOSs. Because fully depleted silicon on insulators use buried oxide with a thickness of tens of nanometers that can accommodate significant holes, the bulk oxide gate oxides are formed very thin using submicron technology.

It has conventionally been believed that such a decrease in the stability of the SRAM is due to the influence of the total ionization dose mainly on the n field effect transistor. However, according to the above analysis results, contrary to the conventional belief, the p field effect transistors 10 and 20 are significantly weakened by the total ionization dose. In other words, the total ionization dose effect for the p field effect transistor of the fully depleted silicon on insulator is stronger than the total ionization dose effect for the n field effect transistor. In addition, the weakened p field effect transistor reduces the static noise margin of hold and read to reduce the stability of the hold and read, and also increases the delay of the write operation and thus weakens the write stability as well.

As described above, the semiconductor memory device 1 may include two p field effect transistors 10 and 20 and two n field effect transistors 30 and 40, and may include at least one p field effect transistor ( 10, 20) are generally affected by the total ionizing dose. This results in relatively poor hold, read, and write stability. In view of such a point, it is possible to design and manufacture the semiconductor memory device 1 that is robust against the total ionization dose and has excellent radiation resistance performance. In addition, it is also possible to construct an electronic circuit having a relatively small influence by the total ionization dose based on such a semiconductor memory device 1.

Hereinafter, an embodiment of a method of measuring the total ionization dose effect of a semiconductor memory device will be described with reference to FIG. 14.

14 is a flowchart of one embodiment of a method of measuring the total ionization dose effect of a semiconductor memory device.

As shown in FIG. 14, in order to measure the total ionization dose effect of the semiconductor memory device, radiation may be first irradiated to the cell or the semiconductor storage device including the cell (101).

In this case, the cell may include four field effect transistors, as shown in FIG. 1, and more specifically, two n field effect transistors respectively connected to two p field effect transistors and two p field effect transistors. It may include. As described above, the two p field effect transistors may include a first field effect transistor and a second field effect transistor, and the two n field effect transistors may include a third field effect transistor corresponding to the first field effect transistor, and And a fourth field effect transistor corresponding to the second field effect transistor. According to an embodiment, the first field effect transistor and the fourth field effect transistor may be set to an off state, and the second field effect transistor and the third field effect transistor may be set to an on state. The field effect transistor (s) may be implemented using a fully depleted silicon on insulator.

Sequentially or aperiodically, the failures generated in the two p field effect transistors and the two n field effect transistors are sequentially counted according to irradiation of radiation. In this case, the failure is measured 102 during at least one of a hold operation, a read operation, and a write operation.

In addition, the measurement of the failure counts the failure generated in the p field effect transistor and the n field effect transistor by irradiation based on the above-described stress pattern and / or p according to the irradiation of radiation based on the above-mentioned opposite pattern. This can be done by counting the failures occurring in the field effect transistor and the n field effect transistor.

According to this measurement, while each operation depends on the total ionization dose, it can be seen that an imprint effect occurs at a hold failure or a read failure, and conversely, an inverse imprint effect appears at the write failure.

In addition, the method of measuring the total ionization dose effect may further include performing a T-cad simulation for each of the four field effect transistors (103). According to the T-cad simulation results, each of the on-field effect transistors (for example, the second field effect transistor of FIG. 1) and the on-state n field effect transistors (for example, the third field effect transistor of FIG. 1) is embedded. It can be seen that the electric fields formed in the oxides are formed in opposite directions.

In addition, the method of measuring the total ionization dose effect may further include obtaining an energy band diagram for at least one of the four field effect transistors (104). In this case, the energy band diagram may represent an energy band for one surface cut in the vertical direction from the middle of the channel with respect to the at least one field effect transistor. The energy band diagram may be performed after setting at least one of the four field effect transistors described above to at least one of an on state and an off state.

In addition, mixed mode simulation may be performed on the voltage transfer curve for radiation and non-irradiation cases (105). Mixed-mode simulation enables visual identification of distortion of static noise margins distorted by the total ionization dose. The static noise margin may include at least one of a hold static noise margin and a read static noise margin.

In addition, for the case where the cell has a fixed oxide density voltage, transient output curves for writes of 1 and 0 through timing simulation may be further obtained (106). The timing simulation and transient output curves show that the rise time required to bring the drain node of the on-state p field effect transistor high is delayed, resulting in a reverse imprint effect during the write process.

14 shows the failure measurement step 102 according to the hold, read and write operations, the T-cad simulation step 103, the energy band acquisition and analysis step 104, the mixed mode simulation step 105 and the timing. Although the obtaining step 106 of the transient output curve according to the simulation is described as being performed sequentially, the processing order of each of these steps 102 to 106 is not necessarily limited thereto. Each of the steps 102-106 may be performed previously and / or concurrently with respect to other steps 102-106 that are different from those shown. For example, at least one of performing the T-cad simulation or acquiring the transient output curve 106 according to the timing simulation may be performed simultaneously with the counting step 102 of failure in each operation described above, and And / or may precede this.

The above-described method for measuring the total ionizing dose effect may be implemented in the form of a computer program. In addition, a program that implements a method for measuring the total ionization dose effect may be stored in a recording medium capable of recording a program and recalled and executed by a computer device.

The various embodiments of the semiconductor memory device, the electronic circuit device using the semiconductor memory device, and the method for measuring the total ionization dose effect for the device have been described. However, the semiconductor memory device, the electronic circuit device using the semiconductor memory device, and the The method of measuring the total ionization dose effect on the device is not limited to only the above-described embodiment. Various devices or methods that can be modified and modified by those skilled in the art based on the above-described embodiments may also be examples of the above-described devices and methods. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than the described method, or other components or Even if replaced or replaced by an equivalent, the above-described semiconductor memory device, the electronic circuit device using the semiconductor memory device, and the method of measuring the total ionization dose effect on the device can be provided.

1: semiconductor storage device 2: cell
10: first field effect transistor 20: second field effect transistor
30: third field effect transistor 40: fourth field effect transistor
50: fifth field effect transistor 60: sixth field effect transistor

Claims (13)

Irradiating radiation to a cell or a semiconductor storage device including the cell, wherein the cell comprises six field effect transistors at least two of which are electrically connected; And
Counting a failure occurring in at least one of the six field effect transistors according to the irradiation of the radiation, the failure comprising at least one of a failure in a hold operation, a failure in a read operation, and a failure in a write operation. Including;
The six field effect transistors,
A first field effect transistor comprising a p field effect transistor that can be set to an off state;
A second field effect transistor comprising a p field effect transistor that can be set to an on state;
A third field effect transistor comprising an n field effect transistor corresponding to the first field effect transistor and set to an on state; And
And a fourth field effect transistor corresponding to the second field effect transistor and including an n field effect transistor that can be set to an off state.
And the first field effect transistor and the fourth field effect transistor are set to an off state, and the second field effect transistor and the third field effect transistor are set to an on state. delete delete The method of claim 1,
Counting failures generated in at least one of the six field effect transistors in accordance with the irradiation of radiation,
Counting a failure occurring in at least one of the first field effect transistor or the fourth field effect transistor according to the irradiation of the radiation under a stress pattern; And
Counting a failure occurring in at least one of the first field effect transistor or the fourth field effect transistor in response to the irradiation of the radiation under a pattern opposite to the stress pattern; A method of measuring the total ionizing dose effect comprising at least one of. The method of claim 1,
And performing a T-cad simulation on at least one of the first to fourth field effect transistors. The method of claim 5,
According to the T-cad simulation, an electric field direction formed in the buried oxide of each of the first field effect transistor in the on state and the buried oxide of the third field effect transistor in the on state obtains a result that is opposite to each other, or the And obtaining a result in which a second field effect transistor and an electric field direction formed in the buried oxide of each of the fourth field effect transistors in an on state are opposite to each other. The method of claim 1,
Setting at least one of the first field effect transistor to the fourth field effect transistor to at least one of an on state and an off state; And
And obtaining an energy band diagram of one surface cut in the vertical direction from the middle of the channel with respect to at least one of the first to fourth field effect transistors. The method of claim 1,
The effect of the total ionization dose on the first field effect transistor or the second field effect transistor is greater than the effect on the total ionization dose on the third field effect transistor or the fourth field effect transistor. The method of measuring the ionizing dose effect further comprising. The method of claim 8,
The effect of the total ionization dose on the first field effect transistor or the second field effect transistor is greater than the effect on the total ionization dose on the third field effect transistor or the fourth field effect transistor. The steps are,
And obtaining a result that the stability of the read, hold, and write operations of the first field effect transistor or the second field effect transistor decreases according to the influence of the total ionization dose. The method of claim 1,
And performing mixed mode simulation on the voltage transfer curve for each of the irradiated case and the non-irradiated case. delete delete delete

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