KR102009330B1 - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of preventing a short circuit of signal links. The present invention relates to a light emitting device disposed in an active region; A plurality of signal links disposed on a substrate in a bending region, the signal links being in contact with the substrate; By providing a protective layer disposed along the signal link on the signal links to expose the substrate between the plurality of signal links disposed in the bending area, a short circuit between the signal links can be prevented.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to an organic light emitting display device capable of preventing a short circuit of signal links.

Video display devices that realize various information as screens are the core technologies of the information and communication era, and are developing in a direction of thinner, lighter, portable and high performance. Accordingly, an organic light emitting display device that can reduce weight and volume, which is a disadvantage of a cathode ray tube (CRT), has been in the spotlight. The organic light emitting diode OLED is a self-luminous element and has low power consumption, high response speed, high luminous efficiency, high luminance, and a wide viewing angle.

As the resolution of the organic light emitting diode display increases, the area of each sub-pixel decreases. In this case, the spacing between the signal links connected to the sub-pixels is also reduced, which causes a short circuit between the signal links. In particular, when the organic light emitting diode display is implemented as a flexible display, the thickness of the bending area where the substrate is bent is reduced to facilitate bending. In this case, a step difference between the bending area and the active area where the image is implemented is large, resulting in process failure. That is, when the signal link is formed, a conductive residual film is mainly generated in the bending region adjacent to the active region, and a short circuit occurs between the signal links disposed in the bending region due to the conductive residual film.

The present invention has been made to solve the above problems, and the present invention is to provide an organic light emitting display device that can prevent a short circuit of the signal links.

In order to achieve the above object, the organic light emitting diode display according to the present invention includes a light emitting element disposed in the active region; A plurality of signal links disposed on a substrate in a bending region, the signal links being in contact with the substrate; By providing a protective layer disposed along the signal link on the signal links to expose the substrate between the plurality of signal links disposed in the bending area, a short circuit between the signal links can be prevented.

According to the present invention, there is provided a protective film having a protrusion disposed on the signal link along the signal link and a trench exposing a substrate between the protrusions. During the trench formation of the protective film, the conductive remaining film remaining between the signal links is removed, thereby preventing a defect in which the signal links are short-circuited due to the conductive remaining film.

1 is a block diagram illustrating a display device according to the present invention.
FIG. 2 is a cross-sectional view illustrating the display device taken along the line “I-I ′” in FIG. 1.
3 is a plan view illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.
4 is a cross-sectional view illustrating an organic light emitting diode display cut along lines II-II 'and III-III' of FIG. 3.
5 is a cross-sectional view illustrating another exemplary embodiment of the organic light emitting diode display illustrated in FIG. 3.
6A and 6B are plan views illustrating embodiments of a signal link disposed in the bending area illustrated in FIG. 3.
7A and 7B are perspective views illustrating the signal link and the protective film shown in FIG. 3 in detail.
8A through 8I are cross-sectional views illustrating a method of manufacturing the OLED display illustrated in FIG. 3.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a display device according to the present invention, and FIG. 2 is a cross-sectional view illustrating the display device according to the present invention.

1 and 2 include a display panel 200, a scan driver 202, and a data driver 204.

The display panel 200 is divided into an active region AA provided on the substrate 101 and an inactive region NA disposed around the active region AA. The substrate 101 is formed of a plastic material having flexibility to allow bending. For example, the substrate 101 may be formed of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), and ciclic- olefin copolymer).

The active area AA displays an image through unit pixels arranged in a matrix. The unit pixel is composed of red (R), green (G), and blue (B) sub pixels, or is composed of red (R), green (G), blue (B), and white (W) sub pixels.

At least one of the data driver 204 and the scan driver 202 may be disposed in the inactive area NA.

The scan driver 202 drives the scan line of the display panel 200. The scan driver 202 is configured using at least one of a thin film transistor having an oxide semiconductor layer and a thin film transistor having a polycrystalline semiconductor layer. In this case, the thin film transistor of the scan driver 202 is simultaneously formed in the same process as at least one thin film transistor disposed in each sub-pixel of the active area AA.

The data driver 204 drives the data line of the display panel 200. The data driver 204 is mounted on the substrate 101 in the form of a chip or in the form of a chip on the signal transmission film 206 and attached to the inactive area NA of the display panel 200. A plurality of signal pads PAD are disposed in the inactive region NA to be electrically connected to the signal transmission film 206. Signal lines in which driving signals generated by the data driver 204, the scan driver 202, the power supply (not shown), and the timing controller (not shown) are disposed in the active area AA through the signal pad PAD. Supplied to.

The inactive area NA includes a bending area BA that can bend or fold the display panel 200. The bending area BA corresponds to an area that is bent in order to position an area that does not have a display function, such as the scan driver 202 and the data driver 204, behind the active area AA. As shown in FIG. 1, the bending area BA corresponds between the active area AA and the data driver 204 and between the active area AA and the scan driver 202. In addition, the bending area BA may be disposed in at least one of the upper, lower, left, and right sides of the inactive area NA. Accordingly, the area occupied by the active area AA is maximized on the entire screen of the display device, and the area corresponding to the inactive area NA is minimized.

At least one opening 212 is disposed in the bending area BA to easily bend the bending area BA, as shown in FIG. 2. The opening 212 is formed by removing a plurality of inorganic insulating layers 210 that cause cracks disposed in the bending area BA. Specifically, when the substrate 101 is bent, continuous bending stress is applied to the inorganic insulating layer 210 disposed in the bending area BA. Since the inorganic insulating layer 210 has a lower elastic force than the organic insulating material, cracks are likely to occur in the inorganic insulating layer 210. Cracks generated in the inorganic insulating layer 210 are propagated along the inorganic insulating layer 210 to the active region AA to cause line defects and device driving failures. Therefore, at least one planarization layer 208 made of an organic insulating material having a higher elasticity than the inorganic insulating layer 210 is disposed in the bending area BA. The planarization layer 208 may reduce bending stress generated when the substrate 101 is bent, thereby preventing cracks from occurring.

The display device having the bending area BA may be applied to a liquid crystal display or an organic light emitting display.

In the present invention, an embodiment in which the display device having the bending area BA is applied to the organic light emitting display device will be described.

3 and 4 are divided into an active area AA provided on the substrate 101 and an inactive area NA disposed around the active area AA. The substrate 101 is formed of a plastic material having flexibility to allow bending.

In the active area AA, a plurality of sub pixels are arranged in a matrix to display an image. Each sub-pixel PXL includes a pixel driving circuit and a light emitting element 120 connected to the pixel driving circuit.

As shown in FIG. 3, the pixel driving circuit includes a switching transistor TS, a driving transistor TD, and a storage capacitor Cst. In the present invention, the pixel driving circuit has two transistors T and one capacitor C as an example, but the present invention is not limited thereto. That is, a pixel driving circuit having a 3T1C structure or a 3TDC structure including three or more transistors T and one or more capacitors C may be used.

 When the scan pulse is supplied to the scan line SL, the switching transistor TS is turned on to supply the data signal supplied to the data line DL to the storage capacitor Cst and the gate electrode of the driving transistor TD. To this end, the switching transistor TS is connected to the gate electrode GE connected to the scan line SL, the source electrode SE connected to the data line DL, and the driving transistor as shown in FIG. 3. And a semiconductor layer ACT forming a channel between the drain electrode DE and the source and drain electrodes.

The driving transistor TD controls the current supplied from the high voltage VDD supply line VL to the light emitting element 130 in response to a data signal supplied to the gate electrode of the driving transistor TD to emit light from the light emitting element 100. The amount of light emitted is controlled. In addition, even when the switching transistor TS is turned off, the driving transistor TD supplies a constant current until the data signal of the next frame is supplied by the voltage charged in the storage capacitor Cst so that the light emitting device 130 Keeps light emission.

To this end, the driving transistor TD may include a semiconductor layer 104 disposed on the active buffer layer 114 and a gate insulating layer 112 interposed therebetween, as shown in FIGS. 3 and 4. A gate electrode 102 overlapping with each other, and source and drain electrodes 106 and 108 formed on the interlayer insulating layer 116 and in contact with the semiconductor layer 104.

The semiconductor layer 104 is formed of at least one of an amorphous semiconductor material, a polycrystalline semiconductor material, and an oxide semiconductor material. The semiconductor layer 104 is formed on the active buffer layer 114. The semiconductor layer 104 includes a channel region, a source region and a drain region. The channel region overlaps the gate electrode 102 with the gate insulating layer 112 therebetween to form a channel region between the source and drain electrodes 106 and 108. The source region is electrically connected to the source electrode 106 through the source contact hole 110S passing through the gate insulating layer 112 and the interlayer insulating layer 116. The drain region is electrically connected to the drain electrode 108 through the drain contact hole 110D passing through the gate insulating layer 112 and the interlayer insulating layer 116. The multi buffer layer 140 and the active buffer layer 114 are disposed between the semiconductor layer 104 and the substrate 101. The multi buffer layer 140 delays diffusion of moisture and / or oxygen penetrated into the substrate 101. The active buffer layer 114 protects the semiconductor layer 104 and functions to block various kinds of defects introduced from the substrate 101.

In this case, an uppermost layer of the multi buffer layer 140 in contact with the active buffer layer 114 may have different etching characteristics from the remaining layers of the multi buffer layer 140, the active buffer layer 114, the gate insulating layer 112, and the interlayer insulating layer 116. It is made of material. The uppermost layer of the multi buffer layer 140 in contact with the active buffer layer 114 is formed of any one of SiNx and SiOx, and the remaining layers of the multi buffer layer 140, the active buffer layer 114, the gate insulating layer 112, and the interlayer insulating layer 116. ) Is formed with the other of SiNx and SiOx. For example, the top layer of the multi buffer layer 140 in contact with the active buffer layer 114 is formed of SiNx, and the remaining layers of the multi buffer layer 140, the active buffer layer 114, the gate insulating layer 112, and the interlayer insulating layer 116. ) Is formed of SiOx.

The gate electrode 102 is formed on the gate insulating layer 112 and overlaps the channel region of the semiconductor layer 104 with the gate insulating layer 112 therebetween. The gate electrode 102 may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a single layer or multiple layers made of an alloy of, but is not limited thereto.

The source electrode 106 is connected to the source region of the semiconductor layer 104 exposed through the source contact hole 110S passing through the gate insulating layer 112 and the interlayer insulating layer 116. The drain electrode 108 faces the source electrode 106 and is connected to the drain region of the semiconductor layer 104 through the drain contact hole 110D passing through the gate insulating layer 112 and the interlayer insulating layer 116. The source and drain electrodes 106 and 108 may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a single layer or multiple layers of one or an alloy thereof, but is not limited thereto.

The light emitting device 130 includes an anode electrode 132, at least one light emitting stack 134 formed on the anode electrode 132, and a cathode electrode 136 formed on the light emitting stack 134.

The anode electrode 132 is electrically connected to the drain electrode 108 of the driving transistor TD exposed through the pixel contact hole 120 passing through the passivation layer 118 and the planarization layer 128. In addition, the anode electrode 132 may be connected to the drain electrode 108 through the pixel auxiliary electrode 142 as shown in FIG. 5. The pixel auxiliary electrode 142 illustrated in FIG. 5 is electrically connected to the drain electrode 108 of the driving transistor TD exposed through the pixel contact hole 120 passing through the passivation layer 118 and the planarization layer 128. The anode electrode 132 is electrically connected to the pixel auxiliary electrode 142 exposed through the second pixel contact hole 140 penetrating the second planarization layer 148.

The anode electrode 132 of each sub pixel is formed to be exposed by the bank 138. The bank 138 may be formed of an opaque material (eg, black) to prevent optical interference between adjacent sub pixels. In this case, the bank 138 includes a light blocking material made of at least one of color pigment, organic black, and carbon.

At least one light emitting stack 134 is formed on the anode electrode 132 of the light emitting region provided by the bank 138. At least one light emitting stack 134 is formed on the anode 132 by laminating a hole related layer, an organic light emitting layer, and an electron related layer in the reverse order. In addition, the light emitting stack 134 may include first and second light emitting stacks facing each other with the charge generation layer therebetween. In this case, the organic light emitting layer of any one of the first and second light emitting stacks generates blue light, and the other organic light emitting layer of the first and second light emitting stacks generates yellow-green light, thereby forming the first and second light emitting stacks. White light is produced through this. Since the white light generated by the light emitting stack 134 is incident on the color filter positioned above or below the light emitting stack 134, a color image may be realized. In addition, a color image may be implemented by generating color light corresponding to each sub-pixel in each light emitting stack 134 without a separate color filter. That is, the light emitting stack 134 of the red (R) subpixel generates red light, the light emitting stack 134 of the green (G) subpixel generates green light, and the light emitting stack 134 of the blue (B) subpixel generates blue light. You may.

The cathode electrode 136 is formed to face the anode electrode 132 with the light emitting stack 134 interposed therebetween, and is connected to a low voltage (VSS) supply line.

The inactive area NA includes a data pad DP connected to the data line DL, a scan pad SP connected to the scan line SL, a low voltage VSS supply line, and a high voltage VDD supply line. Power pads (not shown) to be connected are arranged. The data pad DP, the scan pad SP, and the power pad are disposed in the inactive area NA disposed in at least one of one side and the other area of the substrate 101, or the data pad DP and the scan pad. The pad SP and the power pad may be disposed in different inactive regions NA. The data pad DP, the scan pad SP, and the power pad are not limited to the structure of FIG. 3, and may be variously changed according to the design of the display device.

The inactive area NA in which the data pad DP, the scan pad SP, and the power pad are disposed includes a bending area BA that can bend or fold the substrate 101.

An opening 126 is formed in the bending area BA to expose the substrate 101 of the bending area BA so that the bending area BA is easily bent. The opening 126 is formed by removing the inorganic insulating layers, which have a higher hardness than the organic insulating material and are easily cracked due to bending stress. For example, the opening 126 may include a lower insulating layer BIL including a multi buffer layer 140, an active buffer layer 114, a gate insulating layer 112, and an interlayer insulating layer 116 disposed under the signal link 122. It is formed by removing it. The side surface of the multi-buffer film 140, which is a side surface of the lower insulating film BIL exposed by the opening 126, or the side surface of the substrate 101, and the upper surface of the substrate 101 exposed by the opening 126. The bending area BA is bent to the active area AA based on the bending line BL which is the boundary line.

On the substrate 101 of the bending area exposed by the opening 126, a signal link 122 in contact with the substrate 101 is disposed. The signal link 122 may connect each of the data pad DP, the scan pad SP, and the power pad, and each of the data line DL, the scan line SL, and the power line VL disposed in the active area AA. Connect. When the signal link 122 is formed in a straight line along the bending direction BD, cracks or disconnections may be generated in the signal link 122 under the greatest bending stress. Therefore, the signal link 122 of the present invention widens the area in the direction crossing the bending direction BD to minimize the bending stress.

To this end, as shown in FIGS. 6A and 6B, the signal link 122 is formed in a straight line to the variable point CP spaced apart from the bending line BL by a predetermined distance. In addition, the signal link 122 is formed in a zigzag or sinusoidal shape as shown in FIG. 6A from the variable point CP to the end point of the bending area BA, or as shown in FIG. 6B, the center area is empty. Polygonal shapes are formed in a line connected to each other.

The passivation layer 118 extending from the active area AA to the bending BA area is formed on the signal links 122 to cover the signal link 122. The passivation layer 118 may include a protrusion 118a disposed on the signal link 122 along the signal link 122 in the bending area BA, and a trench 124 that exposes the substrate 101 between the protrusions 118a. ).

In this case, when the passivation layer 118 is formed to be disposed only on the upper surface of the signal link 122, the separation distance of the protrusions 118a of the passivation layer is the same as the separation distance of the signal links 122. And, when the passivation layer 118 is formed to be disposed on the upper surface and the side of the signal link 122, the separation distance of the protrusions (118a) of the passivation layer is smaller than the separation distance of the signal links 122. Meanwhile, when the separation distance of the protrusions 118a of the passivation layer is greater than the separation distance of the signal links 122, the signal link 122 is damaged by the etching gas of the passivation layer 118 when the protrusion 118a of the passivation layer is formed. Can be.

The trench 124 exposes not only the substrate 101 between the signal links 122 disposed in the bending area BA, but also the side surface of the lower insulating layer BIL between the signal links 122. By the trench 124, the conductive residual film generated between the signal links 122 near the bending line BL may be removed. This will be described in detail with reference to FIGS. 7A and 7B.

The signal links 122 are formed on the interlayer insulating layer 116, the side surfaces of the lower insulating layer BIL, and the upper surface of the substrate 101, as shown in FIG. 7A. The signal link 122 is formed by depositing an opaque conductive layer on the substrate 101 and patterning it through a photolithography process and an etching process. At this time, due to a poor substrate surface state and / or lack of process margin, the opaque conductive layer is electrically conductive near the bending line BL, which is a boundary line between the side surface of the lower insulating film BIL and the upper surface of the substrate 101. The remaining film 144 remains. The conductive residual film 144 lowers the resistance between the adjacent signal links 122 so that the signal links 122 are shorted, resulting in line defects.

Thereafter, after the entire surface of the inorganic insulating material is deposited on the substrate 101 on which the conductive residual film 144 is generated, the inorganic insulating material is patterned through a photolithography process and an etching process. Accordingly, as shown in FIG. 7B, the passivation layer 118 having the protrusion 118a and the trench 124 is formed. To form the trench 124, during the etching process of the inorganic insulating material constituting the protective film 118, the conductive residual film 144 also reacts with the dry etching gas of the protective film 118 to be removed together with the inorganic insulating material. To this end, the conductive residual film 144 and the protective film 118 that are generated when the signal link 122 is formed and are made of the same material as the signal link 122 are made of a material capable of dry etching. Accordingly, in the present invention, it is possible to prevent a line defect in which the signal links 122 are shorted by the conductive residual film 144.

Meanwhile, the protrusion 118a protrudes from the passivation layer 118 disposed to cover the top surface of the interlayer insulating layer 116 as shown in FIG. 7B. In this case, the trench 124 exposes the inclined side surfaces of the interlayer insulating layer 116, the gate insulating layer 112, the active buffer layer 114, and the multi buffer layer 140, and the substrate 101 between the protrusions 118a. Let's do it.

In addition, the protrusion 118a may be disposed to cover not only an upper surface of the interlayer insulating layer 116 but also at least one side surface of the interlayer insulating layer 116, the gate insulating layer 112, and the active buffer layer 114 and the multi buffer layer 140. It protrudes from the protective film 118 which becomes. In this case, the trench 124 exposes the substrate 101 between the inclined side surfaces of the gate insulating layer 112, the active buffer layer 114, and the multi buffer layer 140 and the protrusions 118a, or the protrusions 118a. Expose only the substrate 101 between the ().

The planarization layer 128 extending from the active area AA to the bending area BA is disposed on the passivation layer 118 having the trench 124 and the protrusion 118a. This planarization layer 128 is disposed on the substrate 101 between the protrusions 118a exposed by the trench 124. Since the planarization layer 128 is formed of an organic insulating material, the bending stress is alleviated, and thus the bending stress can be prevented from being applied to the passivation layer 118 and the signal link 122 disposed in the bending area BA.

As described above, in the present invention, a protective film having a protrusion 118a disposed along the signal link 122 on the signal link 122 and a trench 124 exposing the substrate 101 between the protrusions 118a. 118 is provided. When the trench 124 is formed in the passivation layer 118, the conductive residual layer 144 remaining between the signal links 122 is removed to prevent a defect in which the signal links 122 are short-circuited by the conductive residual layer 144. can do.

8A through 8I are cross-sectional views illustrating a method of manufacturing the OLED display illustrated in FIG. 4.

Referring to FIG. 8A, the multi buffer layer 140, the active buffer layer 114, and the semiconductor layer 104 are sequentially formed on the substrate 101.

Specifically, the multi buffer layer 140 is formed by alternately stacking SiOx and SiNx on the substrate 101 at least once. Then, SiOx or SiNx is deposited on the multi-buffer layer 140 to form an active buffer layer 114. Then, an amorphous silicon thin film is formed on the substrate 101 on which the active buffer layer 114 is formed by a low pressure chemical vapor deposition (LPCVD), a plasma enhanced chemical vapor deposition (PECVD), or the like. Then, the amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film. The semiconductor layer 104 is formed by patterning the polycrystalline silicon thin film in a photolithography process and an etching process using a first mask.

Referring to FIG. 8B, a gate insulating layer 112 is formed on a substrate 101 on which a semiconductor layer 104 is formed, and a gate electrode 102 is formed on the gate insulating layer 112.

Specifically, the gate insulating layer 112 is formed by depositing an inorganic insulating material such as SiNx or SiOx on the substrate 101 on which the semiconductor layer 104 is formed. Thereafter, after the first conductive layer is entirely deposited on the gate insulating layer 112, the first conductive layer is patterned through a photolithography process and an etching process to form the gate electrode 102.

Referring to FIG. 8C, at least one interlayer insulating layer 116 is formed on the substrate 101 on which the gate electrode 102 is formed, and an opening 126 is formed in the bending area BA.

Specifically, an interlayer insulating layer 116 is formed by depositing an inorganic insulating material such as SiNx or SiOx on the substrate 101 on which the gate electrode 102 is formed. Thereafter, the multi buffer layer 140, the active buffer layer 114, the gate insulating layer 112, and the interlayer insulating layer 116 are patterned through one photolithography process and a plurality of etching processes to open the openings 126 in the bending area BA. ) Is formed. In this case, an uppermost layer of the multi buffer layer 140 in contact with the active buffer layer 114 may have different etching characteristics from the remaining layers of the multi buffer layer 140, the active buffer layer 114, the gate insulating layer 112, and the interlayer insulating layer 116. It is made of material. Since the uppermost layer of the multi buffer layer 140 has different etching characteristics from the remaining layers of the multi buffer layer 140, the active buffer layer 114, the gate insulating layer 112, and the interlayer insulating layer 116, a plurality of etching processes may be performed. In the inactive region, the multi buffer layer 140, the active buffer layer 114, the gate insulating layer 112, and the interlayer insulating layer 116 are formed to form a stepped side surface.

Referring to FIG. 8D, source and drain contact holes 110S and 110D are formed on the substrate 101 on which the opening 126 is formed.

Specifically, a photoresist pattern is formed on the substrate 101 on which the opening is formed through a photolithography process. The gate insulating layer 112 and the interlayer insulating layer 116 are patterned through an etching process using the photoresist pattern as a mask to form source and drain contact holes 110S and 110D.

Referring to FIG. 8E, the source and drain electrodes 106 and 108 and the signal link 122 are formed on the substrate 101 on which the source and drain contact holes 110S and 110D are formed.

In detail, a second conductive layer such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is deposited on the substrate 101 on which the source and drain contact holes 110S and 110D are formed. Then, the second conductive layer is patterned through a photolithography process and an etching process to form the source and drain electrodes 106 and 108 and the signal link 122.

Referring to FIG. 8F, a passivation layer 118 having source and drain electrodes 106 and 108 and a pixel contact hole 120, a trench 124, and a protrusion 118a on a substrate 101 on which a signal link 122 is formed. Is formed.

Specifically, the protective film 118 is formed by depositing an inorganic insulating material such as SiNx or SiOx on the source and drain electrodes 106 and 108 and the substrate 101 on which the signal link 122 is formed. Then, the passivation layer 118 is patterned through a photolithography process and an etching process to form the pixel contact hole 120, the trench 124, and the protrusion 118a. The protrusion 118a is formed along the signal link on the signal link of the bending area, and the pixel contact hole 120 penetrates the passivation layer 118 to expose the drain electrode 108, and the trench 124 has the protrusion 118a. The substrate 101 is exposed through the passivation layer 118 between the layers.

Referring to FIG. 8G, the planarization layer 128 is formed on the substrate 101 on which the passivation layer 118 is formed.

Specifically, the planarization layer 128 is formed by depositing the entire surface of the organic insulating material such as an acrylic resin on the substrate 101 on which the protective film 118 is formed. Then, the planarization layer 128 is patterned through a photolithography process using a mask, so that the pixel contact hole 120 is formed to penetrate the planarization layer 128.

Referring to FIG. 8H, an anode electrode 132 is formed on the substrate 101 on which the planarization layer 128 is formed.

Specifically, a third conductive layer is deposited on the entire surface of the substrate 101 on which the planarization layer 128 is formed. As the third conductive layer, a transparent conductive film and an opaque conductive film are used. Then, the anode electrode 132 is formed by patterning the third conductive layer through a photolithography process and an etching process.

Referring to FIG. 8I, the bank 138, the organic light emitting stack 134, and the cathode electrode 136 are sequentially formed on the substrate 101 on which the anode electrode 132 is formed.

Specifically, the bank 138 is formed by applying a photosensitive organic film to the substrate 101 on which the anode electrode 132 is formed, and then patterning the photosensitive organic film through a photolithography process. Then, the light emitting stack 134 and the cathode electrode 136 are sequentially formed in the active region AA except for the inactive region NA through a deposition process using a shadow mask.

The above description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed by the claims below, and all techniques within the scope equivalent thereto will be construed as being included in the scope of the present invention.

102 gate electrode 104 semiconductor layer
106 source electrode 108 drain electrode
122: signal link 124: trench
126: opening 130: light emitting element

Claims (16)

A substrate separating the active region and the bending region based on the bending line;
A light emitting element disposed in the active region;
A plurality of signal links disposed on the substrate in a first region of the bending region adjacent the bending line and in a second region of the bending region remote from the bending line;
And a passivation layer disposed on the signal links along the signal links to expose the substrate between the plurality of signal links in the first region except the second region. The method of claim 1,
A thin film transistor connected to the light emitting element;
A lower insulating film of at least one layer disposed between the source and drain electrodes of the thin film transistor and the substrate;
And an opening through the lower insulating layer to expose the substrate in the bending region. The method of claim 2,
An organic light emitting bend of the bending region to the active region based on a side of the lower insulating film exposed by the opening or a side of the substrate and the bending line which is a boundary line between an upper surface of the substrate exposed by the opening Display device. The method of claim 3, wherein
The protective film
A protrusion disposed on the signal link along the signal link in the first region of the bending area;
And a trench for exposing a substrate between the protrusions in the first region of the bending region. The method of claim 4, wherein
The protrusion of the passivation layer protrudes into the bending area rather than the bending line. The method of claim 4, wherein
And the trench exposes side surfaces of the lower insulating layer between the signal links. The method of claim 4, wherein
The passivation layer is disposed between the thin film transistor disposed in the active region and the anode electrode of the light emitting device.
The OLED display extends from the active area to the first area of the bending area. The method of claim 4, wherein
And a planarization layer disposed to cover the substrate exposed between the protrusions by the trench. The method of claim 4, wherein
The lower insulating film of the at least one layer
A multi buffer layer disposed on the substrate;
An active buffer layer disposed on the multi buffer layer;
A gate insulating film disposed between the semiconductor layer of the thin film transistor and the gate electrode of the thin film transistor;
And an interlayer insulating layer disposed between the source and drain electrodes of the thin film transistor and the gate electrode of the thin film transistor. The method of claim 9,
The protrusion protrudes from the passivation layer disposed to cover at least one of an upper surface of the interlayer insulating layer, a side surface of the interlayer insulating layer, a side surface of the gate insulating layer, a side surface of the active buffer layer, and a side surface of the multi buffer layer.
The trench exposes a substrate between at least one of the interlayer insulating layer, the gate insulating layer, the active buffer layer, and the multi buffer layer and the protrusions, or exposes the substrate between the protrusions. . The method of claim 9,
The uppermost layer of the multi buffer layer is made of any one of SiNx and SiOx,
The remaining layer of the multi buffer layer, the active buffer layer, the gate insulating film, and the interlayer insulating film are formed of the remaining one of the SiNx and SiOx. The method of claim 9,
And the signal link and the passivation layer are made of a dry etching material. The method of claim 4, wherein
The trench of the passivation layer is concave to the active area than the bending line. The method of claim 4, wherein
The signal link is formed in a straight line shape in the first area of the bending area, and is formed in a shape different from the straight shape in the second area of the bending area. The method of claim 14,
The protrusion of the passivation layer is disposed along the signal link formed in the straight line in the first region except for the second region. The method of claim 2,
The plurality of signal links overlap the side of the lower insulating layer,
The passivation layer exposes a side surface of the lower insulating film between a plurality of signal links overlapping the side surface of the lower insulating film.

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