KR101995034B1 - Data storage device and operating method thereof - Google Patents

Abstract

The present invention relates to data storage devices, and more particularly, to a method for parallel processing data storage devices. A data storage device according to an embodiment includes a controller configured to control operations of non-volatile memory devices and non-volatile memory devices, wherein the controller is configured to map logical addresses provided from the host device and physical addresses of non- And when it is determined to control the multi-plane operation, the data is remapped to the logical address that is requested to be accessed from the host device based on the location of the page being programmed, and the remapped physical address Lt; RTI ID = 0.0 > interleaving < / RTI >

Description

≪ Desc / Clms Page number 1 > DATA STORAGE DEVICE AND OPERATING METHOD THEREOF &

The present invention relates to a data storage apparatus, and more particularly, to a parallel processing method of a data storage apparatus.

Recently, a paradigm for a computer environment has been transformed into ubiquitous computing, which enables a computer system to be used whenever and wherever. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices typically use a data storage device that utilizes a memory device. The data storage device is used as a main storage device or an auxiliary storage device of a portable electronic device.

The data storage device using the memory device is advantageous in that it has excellent stability and durability because it has no mechanical driving part, has very high access speed of information and low power consumption. A data storage device having such advantages includes a USB (Universal Serial Bus) memory device, a memory card having various interfaces, and a solid state drive (SSD).

BACKGROUND ART [0002] As portable electronic devices reproduce large-capacity files such as music, moving pictures, etc., data storage devices are required to have a large storage capacity. A data storage device includes a plurality of memory devices to increase storage capacity. For a data storage device comprising a plurality of memory devices, a large storage capacity as well as a fast operating speed is one of the important characteristics of the data storage device.

A data storage device including a plurality of memory devices must effectively control a plurality of memory devices for high-speed data processing. A parallel processing method among a plurality of memory devices, for example, an interleaving method, is used as a technique for effectively controlling a plurality of memory devices. That is, the data storage device uses a method of controlling a plurality of memory devices in parallel for high-speed data processing to minimize the idle time of each of the plurality of memory devices.

On the other hand, the data storage device maps the physical address of the memory device to the logical address requested from the host device in which the data storage device is mounted. In a general interleaving method, the physical address corresponding to the logical address provided from the host apparatus is fixed. That is, in the general interleaving method, the address mapping is fixed, and the interleaving method is used based on the fixed address mapping. When the interleaving method is used on the basis of the fixed address mapping, there arises a problem that it is difficult to reflect environmental factors (for example, the request state of the host device, the state of the memory devices, etc.)

An embodiment of the present invention is to provide a data storage apparatus and method using an improved parallel processing method.

A data storage device according to an embodiment of the present invention includes nonvolatile memory devices; And a controller configured to control operations of the non-volatile memory devices, the controller is further configured to map the physical addresses of the non-volatile memory devices with logical addresses provided from the host device, The data is re-mapped to a logical address accessed from the host device based on the location of the programmed page and an interleaving operation for the non-volatile memory devices using the remapped physical address is performed . ≪ / RTI >

A method of operating a data storage device comprising a plurality of nonvolatile memory devices according to an embodiment of the present invention includes mapping logic addresses and physical addresses of the nonvolatile memory devices, Maps the physical address to an address, and performs an interleaving operation on the nonvolatile memory devices using the remapped physical address.

A data storage device according to an embodiment of the present invention includes: non-volatile memory devices; And a controller configured to control operations of the non-volatile memory devices, wherein the controller maps physical addresses of the non-volatile memory devices to logical addresses provided from the host device, Maps the physical address to the logical address requested to be accessed from the host device by reflecting the environmental factor of the non-volatile memory devices, and performs the interleaving operation on the non-volatile memory devices using the remapped physical address.

According to the embodiment of the present invention, the data processing speed of the data storage device can be improved.

1 is a block diagram illustrating an exemplary data processing system including a data storage device in accordance with an embodiment of the present invention.
Figure 2 is a block diagram illustrating an exemplary data storage controller of Figure 1;
FIG. 3 is a diagram for explaining firmware to be driven in the operation memory device of FIG. 2. FIG.
4 and 5 are views for explaining the concept of a dynamic interleaving method according to an embodiment of the present invention.
FIGS. 6 and 7 illustrate a dynamic interleaving method according to an embodiment of the present invention.
FIGS. 8 and 9 illustrate a dynamic interleaving method according to another embodiment of the present invention.
10 and 11 illustrate a dynamic interleaving method according to another embodiment of the present invention.
12 is a block diagram illustrating an exemplary data processing system in accordance with another embodiment of the present invention.
13 is a view illustrating an exemplary memory card according to an embodiment of the present invention.
FIG. 14 is a block diagram exemplarily showing an internal configuration of the memory card shown in FIG. 13 and a connection relationship with the host device.
15 is a block diagram exemplarily showing a solid state drive (SSD) according to an embodiment of the present invention.
16 is a block diagram exemplarily showing the SSD controller shown in FIG.
17 is a block diagram illustrating an exemplary computer system in which a data storage device according to an embodiment of the present invention is mounted.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although specific terms are used herein, It is to be understood that the same is by way of illustration and example only and is not to be taken by way of limitation of the scope of the appended claims.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Also, the expression " coupled / coupled " is used to mean either directly connected to another component or indirectly connected through another component. The singular forms herein include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating an exemplary data processing system including a data storage device in accordance with an embodiment of the present invention. Referring to FIG. 1, a data processing system 100 includes a host device 110 and a data storage device 120.

The host device 110 includes, for example, portable electronic devices such as mobile phones, MP3 players or the like or electronic devices such as laptop computers, desktop computers, game machines, TVs, beam projectors and the like.

The data storage device 120 is configured to operate in response to a request from the host device 110. [ The data storage device 120 is configured to store data accessed by the host device 110. That is, the data storage device 120 may be used as the main storage device or the auxiliary storage device of the host device 110. [ The data storage device 120 includes a controller 130 and a data storage medium 140. The controller 130 and the data storage medium 140 may be a memory card connected to the host device 110 through various interfaces. Alternatively, the controller 130 and the data storage medium 140 may be configured as a solid state drive (SSD).

The controller 130 is configured to control the data storage medium 140 in response to a request from the host device 110. For example, the controller 130 is configured to provide data read from the data storage medium 140 to the host device 110. [ As another example, the controller 130 is configured to store data provided from the host device 110 in the data storage medium 140. For this operation, the controller 130 is configured to control the read, program (or write) and erase operations of the data storage medium 140.

The data storage medium 140 includes nonvolatile memory devices NVM00 to NVM0k and NVMn0 to NVMnk. According to an embodiment of the present invention, each of the non-volatile memory devices NVM00 to NVM0k and NVMn0 to NVMnk will be configured as a NAND flash memory device. However, it will be appreciated that each of the non-volatile memory devices NVM00 to NVM0k and NVMn0 to NVMnk may be configured as other non-volatile memory devices in place of the NAND flash memory device. For example, each of the nonvolatile memory devices NVM00 to NVM0k and NVMn0 to NVMnk may include a NOR flash memory device, a ferroelectric RAM (FRAM) using ferroelectric capacitors, a tunneling magneto-resistive (TMR) ) Magnetic random access memory (MRAM) using ferroelectric random access memory (MRAM), and a phase change memory device (PRAM) using chalcogenide alloys, and the like. have.

The flash memory devices NVM00 to NVM0k and NVMn0 to NVMnk are connected to the controller 130 through the channels CH0 to CHn. The controller 130 can operate the channels CH0 to CHn in parallel. For example, the controller 130 may control the interleaving operation between the channels CH0 to CHn. In addition, the controller 130 may operate the flash memory devices NVM00 to NVM0k or NVMn0 to NVMnk connected to one channel (CH0 or CHn) in parallel. For example, the controller 130 may control the interleaving operation between the flash memory devices NVM00 to NVM0k or NVMn0 to NVMnk.

Meanwhile, although not shown, each of the flash memory devices NVM00 to NVM0k and NVMn0 to NVMnk may be configured in a multi-plane structure. Here, the plane represents a unit for identifying memory blocks that share a page buffer. In this case, the controller 130 can operate the planes included in one flash memory device (for example, two planes) in parallel. For example, the controller 130 may control the interleaving operation between the planes.

In other words, the storage area of the data storage device 120 is divided into flash memory devices NVM00 to NVM0k and NVMn0 to NVMnk connected to the channels CH0 to CHn, channels CH0 to CHn, and flash memory devices (Not shown) included in each of the NVM0 to NVM0k and NVMn0 to NVMnk, respectively. In the data storage device 120 having a plurality of pages, the controller 130 must effectively control a plurality of pages for high-speed data processing. The controller 130 may parallel-process (hereinafter, referred to as "interleaving") a plurality of pages for this purpose.

Figure 2 is a block diagram illustrating an exemplary data storage controller of Figure 1; Referring to FIG. 2, the controller 130 includes a micro controller unit (MCU) 131 and an operation memory unit 135. It will be appreciated, however, that the components of controller 130 are not limited to the components mentioned. For example, the controller 130 may further include a host interface, a memory interface, an error correction unit (ECC), and the like.

The MCU 131 controls all operations of the controller 130. The MCU 131 is configured to drive firmware for controlling all operations of the controller 130. [ This firmware is loaded into the operation memory device 135 and driven. The MCU 131 may provide instructions, addresses, control signals and data for controlling the data storage medium (see 140 in FIG. 1) upon request of the host device (see 110 in FIG. 1).

In the operation memory device 135, firmware and data for controlling the controller 130 are stored. The operational memory device 135 includes at least one of a cache, DRAM, SRAM, ROM, NOR flash memory devices. According to an embodiment of the present invention, the operation memory device 135 stores a Flash Translation Layer (FTL). When there is a request from the host device (see 110 in FIG. 1), the flash translation layer (FTL) is driven by the MCU 131.

FIG. 3 is a diagram for explaining firmware to be driven in the operation memory device of FIG. 2. FIG.

The flash memory device constituting the data storage medium (refer to 140 in FIG. 1) performs a read or program operation on a page basis due to the structural feature. The flash memory device performs an erase operation on a block basis due to a structural feature. Here, a page is an operation unit composed of a plurality of memory cells and a block is an operation unit composed of a plurality of pages. In addition, the flash memory device can not be overwritten. That is, a flash memory cell in which data is stored must be erased to store new data.

Due to the features of such a flash memory device, a data storage device (see 120 in FIG. 1) including a flash memory device as data storage medium 140 may be implemented with disk emulation software which requires additional software called disk emulation software. That is, the data storage device 120 including the flash memory device operates firmware such as a flash conversion layer (FTL) to ensure compatibility with the host device 110.

The flash translation layer (FTL) is a read-only flash memory device, such as a flash memory device, that is readable and writable by the flash memory device so that the data storage device 120 can be operated in response to a requested access from the file system of the host device 110 , Erase operation, and the like. As a result, the file system of the host device 110 can recognize the data storage device 120 including the flash memory device as a general data storage device.

Referring to FIG. 3, the flash translation layer (FTL) includes a plurality of modules (mudules) and management data. For example, the flash translation layer (FTL) may comprise an interleaving module 135_1, an address mapping table 135_2, a ware-leveling module 135_3, and a garbage collection module 135_4. However, it will be appreciated that the configuration of the flash translation layer (FTL) is not limited to the aforementioned modules. For example, the flash translation layer (FTL) may further include a bad block management module for managing a block including a defective memory cell, a permanent power off management module for preparing for an unexpected power shutdown, and the like .

The interleaving module 135_1 performs an interleaving operation (or a deinterleaving operation) of the flash memory devices constituting the data storage medium 140. [ The interleaving module 135_1 manages the data to be programmed in the data storage medium 140 by an interleaving method. For example, the interleaving module 135_1 may divide the data to be stored in the data storage medium 140 into arbitrary sizes, mix the divided data, and reconstitute the data to be actually programmed. The interleaving module 135_1 may program the reconfigured data in parallel to the flash memory devices of the data storage medium 140. [ Also, the interleaving module 135_1 manages the data stored in the data storage medium 140 to be read out by the deinterleaving method. It will be appreciated that the deinterleaving method may be performed in the reverse order of the interleaving method.

In an embodiment of the present invention, the interleaving module 135_1 performs a dynamic interleaving method. Here, the dynamic interleaving method means performing the interleaving method reflecting the environmental factors. This dynamic interleaving method will be described in detail with reference to FIGS. 4 to 11. FIG.

When the host device (see 110 in FIG. 1) accesses the data storage device (120 in FIG. 1) (e.g., requests a read or write operation), the host device 110 generates a logical address To the data storage device (120). The flash translation layer (FTL) converts the provided logical address into the physical address of the data storage medium 140, and performs the requested operation with reference to the converted physical address. The flash translation layer (FTL) manages the address translation data, i.e., the address mapping table 135_2, for this address translation operation.

The wear-leveling module 135_3 manages the wear-level of the blocks of the flash memory devices constituting the data storage medium 140. The wear- The memory cells of the flash memory devices are aged by the program and erase operations. The aged memory cell, i. E., The worn memory cell, will cause defects (e. G., Physical defects). The wear-leveling module 135_3 manages the erase-write cycle of each of the blocks to be leveled so as to prevent a specific block of flash memory devices from being worn out faster than other blocks.

The garbage collection module 135_4 manages blocks in which pieces of fragmented data are stored. The flash memory devices constituting the data storage medium 140 are not overwritable, and the erase unit is larger than the program unit. Therefore, when the storage space reaches a certain limit, the flash memory devices need to collect the valid data, which is dispersed physically in different locations using an arbitrary empty space, in the same address area. The garbage collection module 135_4 performs a plurality of write operations and a plurality of erase operations to collect the fragmented valid data into the same address area.

4 and 5 are views for explaining the concept of a dynamic interleaving method according to an embodiment of the present invention.

Referring to FIG. 4, a flash memory device that constitutes a data storage medium (see 140 in FIG. 1) is shown. For simplicity of explanation, it is assumed that the data storage medium 140 includes four flash memory devices NVM0 to NVM3. The flash memory devices NVM0 and NVM1 are connected to the controller 130 via the channel CHa and the flash memory devices NVM2 and NVM3 are connected to the controller 130 via the channel CHb It is assumed that they are connected. And each of the flash memory devices NVM0 to NVM3 is composed of two planes, and each of the planes is composed of two pages. For example, assuming that the flash memory device NVM0 is composed of two planes PL0 and PL1, and each of the planes PL0 and PL1 is composed of two pages P00 to P01 and P10 to P11 do.

Referring to FIG. 5, there is shown a mapping table that is changed when a dynamic interleaving method is used. 4, the data storage medium 140 consists of a total of 16 pages. The sixteen pages are divided into page addresses P00 to P71, that is, physical addresses. These physical addresses P00 to P71 are mapped to the logical address L provided from the host device (see 110 in FIG. 1).

Referring to the initial address mapping table before the dynamic interleaving method is performed, the initial address mapping is performed so that the idle time of each of the flash memory devices NVM0 to NVM3 is minimized through the interleaving operation, the number of flash memory devices per channel, The number of pages per plane, and the number of pages per plane. For example, the logical address L0 corresponds to the physical address P00, the logical address L1 corresponds to the physical address P20, the logical address L2 corresponds to the physical address P40, and the logical address L3 corresponds to the physical And is mapped to the address P60. It will be appreciated that in the same manner, each of the remaining logical addresses can be mapped to each of the remaining physical addresses.

When the dynamic interleaving method according to the embodiment of the present invention is performed, the address mapping is changed reflecting the environmental element. That is, when the dynamic interleaving method is performed, the physical address mapped to the logical address is changed reflecting the environmental element. Illustratively, referring to the modified mapping table, the physical address mapped to the logical address L2 is changed.

The environmental factors reflected in the dynamic interleaving method include physical elements and logical elements. Physical elements include, but are not limited to, the number of channels and flash memory devices, the operating state of the channel and flash memory devices, the size of the physical page, the location of the data in the programmed physical page (or the location of the programmable physical page) . The logical element means the size of the data requested at present, the size of the data expected to be requested in the future, and the like. According to the dynamic interleaving method, address mapping is changed in consideration of logical elements based on physical elements. This means that the interleaving operation can be generated dynamically, not static. The dynamic interleaving method will be described in detail with reference to FIGS. 6 to 11, assuming arbitrary conditions.

FIGS. 6 and 7 illustrate a dynamic interleaving method according to an embodiment of the present invention. Referring to Figures 6 and 7, a dynamic interleaving method that reflects the operating state (e.g., ready or busy state) of the channel and flash memory devices will be exemplarily described.

6 and 7, for simplicity of explanation, it is assumed that the data storage medium (see 140 in FIG. 1) includes four flash memory devices NVM0 to NVM3 connected to the channels CHa and CHb do. And each of the flash memory devices NVM0 to NVM3 is composed of two planes, and each of the planes is composed of two pages. On the other hand, it is assumed that the flash memory devices NVM0, NVM1, and NVM3 are in a busy state, and the flash memory device NVM2 is in a ready state.

Referring to FIG. 7, the initial address mapping before the dynamic interleaving method is performed is performed so that the idle time of each of the flash memory devices NVM0 to NVM3 is minimized through the interleaving operation, the number of flash memory devices per channel, The number of pages per plane, and the number of pages per plane. For example, the logical address L0 corresponds to the physical address P00, the logical address L1 corresponds to the physical address P20, the logical address L2 corresponds to the physical address P40, and the logical address L3 corresponds to the physical And is mapped to the address P60. It will be appreciated that in the same manner, each of the remaining logical addresses can be mapped to each of the remaining physical addresses.

In this environment, if a data program is requested from the host device (see 110 in FIG. 1) to the physical address P20 corresponding to the logical address L1, that is, When a data program is requested at the address P20, a dynamic interleaving method is performed reflecting the operating state of the flash memory device NVM1. A more detailed explanation is as follows.

Data provided from the host device 110 should be programmed to the physical address P20 corresponding to the logical address L1 but the flash memory device NVM1 to which the physical address P20 is assigned is currently busy . That is, the program request from the host apparatus 110 can not be immediately executed. Therefore, a dynamic interleaving method reflecting the operating state of the channel and the flash memory devices NVM0 to NVM3 is performed. As a result, the logical address L1 will be remapped to the physical address of the flash memory device NVM1 which is ready to immediately execute the program request. For example, the logical address L1 is remapped from the physical address P20 to the physical address P50. And the program request data for the logical address L1 will be programmed to the page corresponding to the physical address P50.

On the other hand, the state of the flash memory device NVM2 (for example, the position of the page on which data is programmed) in which the logical address L1 is remapped to the physical address P50 by the dynamic interleaving method, It will be appreciated that the logical address < RTI ID = 0.0 > L1 < / RTI >

FIGS. 8 and 9 illustrate a dynamic interleaving method according to another embodiment of the present invention. 8 and 9, a dynamic interleaving method that reflects the requested data size based on the size of a physical page and reflects the operating characteristics of the flash memory device will be exemplarily described.

8 and 9, for simplicity of explanation, it is assumed that the data storage medium (see 140 in FIG. 1) includes four flash memory devices (NVM0 to NVM3) connected to the channels CHa and CHb do. And each of the flash memory devices NVM0 to NVM3 is composed of two planes, and each of the planes is composed of two pages. On the other hand, it is assumed that the page size of the flash memory devices NVM0 to NVM3 is 2 KB. And the pages corresponding to the physical addresses P00 and P20 have been previously programmed.

Referring to FIG. 9, the initial address mapping before the dynamic interleaving method is performed is determined by the number of flash memory devices per channel, the number of flash memory devices per flash memory device (NVM0 to NVM3) The number of pages per plane, and the number of pages per plane. For example, the logical address L0 corresponds to the physical address P00, the logical address L1 corresponds to the physical address P20, the logical address L2 corresponds to the physical address P40, and the logical address L3 corresponds to the physical And is mapped to the address P60. It will be appreciated that in the same manner, each of the remaining logical addresses can be mapped to each of the remaining physical addresses.

In this environment, if a data program is requested from the host device (see 110 in FIG. 1) to the physical addresses P40 and P60 respectively corresponding to the sequential logical addresses L2 and L3, A dynamic interleaving method is performed reflecting the size of the requested data and reflecting the operating characteristics of the flash memory device. A more detailed explanation is as follows.

The data sequentially provided from the host device 110 must be programmed to the physical address P40 corresponding to the logical address L2 and the physical address P60 corresponding to the logical address L3. However, if the size of the sequentially provided data is smaller than a page that is a program unit and smaller than a multi-page that can be operated in parallel by a multi-plane operation, the provided data may be programmed in a multi- Can be more effective. Here, the multi-page may be composed of two or more pages that can be operated in parallel by the multi-plane method.

Therefore, a dynamic interleaving method that reflects the size of the requested data based on the size of the physical page and reflects the operation characteristics of the flash memory device is performed. As a result, the logical address L3 will be remapped to the physical address of the flash memory device NVM2. For example, the logical address L3 is remapped from the physical address P60 to the physical address P50. Then, the program request data (2KB) for the logical address L2 and the program request data (2KB) for the logical address L3 are transferred to the pages corresponding to the physical addresses P40 and P50 in the multi- Will be.

On the other hand, although the logical address L3 has been remapped to the physical address P50 by the dynamic interleaving method, the data of the flash memory devices NVM0 to NVM3 are stored in the position of the programmed physical page (or the location of the programmable physical page) It will be appreciated that the logical addresses L2 and L3 may be remapped to different physical addresses according to < / RTI > For example, the logical addresses L2 and L3 may be different physical addresses P10 and P30, other than the physical addresses P10 and P30, which can not be programmed in a multi-plane manner due to the addresses P00 and P20 of the physical page the data is programmed to. Mapped to addresses.

10 and 11 illustrate a dynamic interleaving method according to another embodiment of the present invention. Referring to FIGS. 10 and 11, a dynamic interleaving method that reflects the position of the physical page (or the position of the programmable physical page) and the size of the data to be subsequently requested will be exemplarily described.

10 and 11, for simplicity of explanation, it is assumed that the data storage medium (see 140 in FIG. 1) includes four flash memory devices (NVM0 to NVM3) connected to the channels CHa and CHb do. And each of the flash memory devices NVM0 to NVM3 is composed of two planes, and each of the planes is composed of two pages. On the other hand, it is assumed that the page size of the flash memory devices NVM0 to NVM3 is 2 KB. And the pages corresponding to the physical addresses P00, P20, P40 and P60 have been previously programmed.

Referring to FIG. 11, the initial address mapping before the dynamic interleaving method is performed may include the number of flash memory devices per channel, the number of flash memory devices per flash memory device (NVM0 to NVM3) The number of pages per plane, and the number of pages per plane. For example, the logical address L0 corresponds to the physical address P00, the logical address L1 corresponds to the physical address P20, the logical address L2 corresponds to the physical address P40, and the logical address L3 corresponds to the physical The logical address L4 is mapped to the physical address P10 and the logical address L5 is mapped to the physical address P30 in the address P60. It will be appreciated that in the same manner, each of the remaining logical addresses can be mapped to each of the remaining physical addresses.

In such an environment, a data program is requested from the host device (see 110 in Fig. 1) to the physical addresses P10 and P30 respectively corresponding to the sequential logical addresses L4 and L5, (2 KB) is predicted to be equal to the size of the physical page (2 KB), a dynamic interleaving method is performed. At this time, the position of the physical page on which the data is programmed (or the position of the programmable physical page) and the size of the data to be subsequently requested are reflected in the dynamic interleaving method. A more detailed explanation is as follows.

The data sequentially provided from the host device 110 must be programmed to the physical address P10 corresponding to the logical address L4 and the physical address P30 corresponding to the logical address L5. However, if the size of the sequentially provided data is smaller than a page that is a program unit and smaller than a multi-page that can be operated in parallel by a multi-plane operation, the provided data may be programmed in a multi- Can be more effective. Also, if the size of the data to be requested next is predicted to be equal to the size of one physical page, then the data to be requested may be more effective to program on physical pages that can not be programmed in a multi-plane manner.

Thus, a dynamic interleaving method is performed that reflects the location of the physical page where the data is programmed (or the location of the programmable physical page) and the size of the data to be subsequently requested. As a result, the logical address L4 will be remapped to the physical address P01 of the flash memory device NVM0 and the logical address L5 will be remapped to the physical address P11 of the flash memory device NVM0. The program request data (2KB) for the logical address L4 and the program request data (2KB) for the logical address L5 are transferred to the pages corresponding to the physical addresses P01 and P11 in a multi- Will be. On the other hand, the data of the logical address to be requested next will be remapped to one of the physical addresses P10, P30, P50 or P70. Then, the data to be requested next will be programmed into the page corresponding to the remapped physical address.

On the other hand, although the logical addresses L4 and L5 have been remapped to the physical addresses P01 and P11 by the dynamic interleaving method, the data of the flash memory devices NVM0 to NVM3 have not yet been programmed It will be appreciated that logical addresses L4 and L5 may be remapped to different physical addresses depending on the location of the physical page (s) possible. For example, logical addresses L4 and L5 can be remapped to other physical addresses that can be programmed in a multi-plane manner.

According to embodiments of the present invention, the physical address mapped to the logical address is changed reflecting the environmental element. The dynamic interleaving operation is performed with reference to the changed mapping table. Here, the environmental element includes the number of channels and flash memory devices, the operating state of the channel and flash memory devices, the size of the physical page, the location of the physical page (or the location of the programmable physical page) The size of the requested data, the size of the data expected to be requested in the future, and the like. According to the dynamic interleaving method, the interleaving operation can be effectively performed.

12 is a block diagram illustrating an exemplary data processing system in accordance with another embodiment of the present invention. Referring to FIG. 12, a data processing system 1000 includes a host device 1100 and a data storage device 1200. The data storage device 1200 includes a controller 1210 and a data storage medium 1220. The data storage device 1200 may be connected to and used by a host device 1100 such as a desktop computer, a notebook computer, a digital camera, a mobile phone, an MP3 player, a game machine, and the like. Data storage device 1200 is also referred to as a memory system.

The data storage device 1200 will perform a dynamic interleaving method according to an embodiment of the present invention. Thus, the data processing speed of the data storage device 1200 can be improved.

The controller 1210 is connected to the host device 1100 and the data storage medium 1220. Controller 1210 is configured to access data storage medium 1220 in response to a request from host device 1100. [ For example, the controller 1210 is configured to control the reading, programming, or erasing operations of the data storage medium 1220. The controller 1210 is configured to drive firmware for controlling the data storage medium 1220.

The controller 1210 may include well known components such as a host interface 1211, a central processing unit 1212, a memory interface 1213, a RAM 1214 and an error correction code unit 1215.

The central processing unit 1212 is configured to control all operations of the controller 1210 in response to a request from the host device. The RAM 1214 may be used as a working memory of the central processing unit 1212. The RAM 1214 may temporarily store data read from the data storage medium 1220 or data provided from the host apparatus 1100.

The host interface 1211 is configured to interface the host device 1100 and the controller 1210. For example, the host interface 1211 may include a USB (Universal Serial Bus) protocol, an MMC (Multimedia Card) protocol, a PCI (Peripheral Component Interconnection) protocol, a PCI- The host device 1100 may be configured to communicate with the host device 1100 through one of various interface protocols such as a protocol, SATA (Serial ATA) protocol, SCSI (Small Computer Small Interface) protocol, and IDE (Integrated Drive Electronics) protocol.

The memory interface 1213 is configured to interface the controller 1210 and the data storage medium 1220. The memory interface 1213 is configured to provide commands and addresses to the data storage medium 1220. The memory interface 1213 is configured to exchange data with the data storage medium 1220.

The error correction code unit 1215 is configured to detect an error in the data read from the data storage medium 1220. And the error correction code unit 1215 is configured to correct the detected error if the detected error is within the correction range. On the other hand, the error correction code unit 1215 may be provided in the controller 1210 or may be provided outside according to the memory system 1000.

The controller 1210 and the data storage medium 1220 may be configured as a solid state drive (SSD).

As another example, the controller 1210 and the data storage medium 1220 may be integrated into one semiconductor device and configured as a memory card. For example, the controller 1210 and the data storage medium 1220 may be integrated into a single semiconductor device and may be a personal computer memory card (PCMCIA) card, a compact flash (CF) card, a smart media card, A memory stick, a multi-media card (MMC, RS-MMC, MMC-micro), a secure digital (SD) card (SD, Mini SD, MicroSD) .

As another example, controller 1210 or data storage medium 1220 may be implemented in various types of packages. For example, the controller 1200 or the data storage medium 1900 may include a package on package (POP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP) outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), thin quad flat package (TQFP), system in package (SIP), multi chip package (MCP) WFP), a wafer-level processed stack package (WSP), and the like.

13 is a view illustrating an exemplary memory card according to an embodiment of the present invention. 13 shows the outline of an SD (secure digital) card among memory cards.

13, an SD card includes one command pin (for example, pin 2), one clock pin (for example, pin 5), four data pins (for example, 8, and 9), and three power pins (e.g., pins 3, 4, and 6).

A command and a response signal are transmitted through the command pin (pin 2). Generally, the command is transmitted from the host apparatus to the SD card, and the response signal is transmitted from the SD card to the host apparatus.

The data pins (1, 7, 8, and 9) are divided into receive (Rx) pins for receiving data transmitted from the host device and transmit (Tx) pins for transmitting data to the host device. Receive (Rx) pins and transmit (Tx) pins are each provided in pairs to transmit a differential signal.

The SD card can perform the dynamic interleaving method according to the embodiment of the present invention. Therefore, the data processing speed of the SD card can be improved.

FIG. 14 is a block diagram exemplarily showing an internal configuration of the memory card shown in FIG. 13 and a connection relationship with the host device. Referring to Fig. 14, the data processing system 2000 includes a host device 2100 and a memory card 2200. The host apparatus 2100 includes a host controller 2110 and a host connection unit 2120. The memory card 2200 includes a card connection unit 2210, a card controller 2220, and a memory device 2230.

The host connection unit 2120 and the card connection unit 2210 are composed of a plurality of pins. These pins include a command pin, a clock pin, a data pin, and a power pin. The number of pins varies depending on the type of the memory card 2200.

The host apparatus 2100 stores data in the memory card 2200 or reads data stored in the memory card 2200. [

The host controller 2110 receives the write command CMD, the clock signal CLK generated from the clock generator (not shown) in the host apparatus 2100 and the data DATA via the host connection unit 2120, (2200). The card controller 2220 operates in response to a write command received through the card connection unit 2210. [ The card controller 2220 stores the received data DATA in the memory device 2230 using a clock signal generated from a clock generator (not shown) in the card controller 2220 according to the received clock signal CLK do.

The host controller 2110 transmits a read command CMD and a clock signal CLK generated from a clock generator (not shown) in the host apparatus 2100 to the memory card 2200 through the host connection unit 2120 . The card controller 2220 operates in response to a read command received through the card connection unit 2210. The card controller 2220 reads data from the memory device 2230 using a clock signal generated from a clock generator (not shown) in the card controller 2220 according to the received clock signal CLK, And transmits it to the controller 2110.

15 is a block diagram exemplarily showing a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 15, a data processing system 3000 includes a host device 3100 and a solid state drive (SSD) 3200.

The SSD 3200 includes an SSD controller 3210, a buffer memory device 3220, nonvolatile memory devices 3231-323n, a power supply 3240, a signal connector 3250, and a power connector 3260.

The SSD 3200 operates in response to a request from the host device 3100. That is, the SSD controller 3210 is configured to access the non-volatile memory devices 3231 to 323n in response to a request from the host device 3100. [ For example, the SSD controller 3210 is configured to control the read, program and erase operations of the non-volatile memory devices 3231 through 323n. In addition, the SSD controller 3210 will perform a dynamic interleaving method according to an embodiment of the present invention. Therefore, the data processing speed of the SSD 3200 can be improved.

The buffer memory device 3220 is configured to temporarily store data to be stored in the nonvolatile memory devices 3231 to 323n. In addition, the buffer memory device 3220 is configured to temporarily store data read from the non-volatile memory devices 3231 to 323n. The data temporarily stored in the buffer memory device 3220 is transferred to the host device 3100 or the nonvolatile memory devices 3231 to 323n under the control of the SSD controller 3210. [

The nonvolatile memory devices 3231 to 323n are used as a storage medium of the SSD 3200. Each of the nonvolatile memory devices 3231 to 323n is connected to the SSD controller 3210 through a plurality of channels CH1 to CHn. One channel may be coupled to one or more non-volatile memory devices. Non-volatile memory devices connected to one channel will be connected to the same signal bus and data bus.

The power supply 3240 is configured to provide the power supply PWR input through the power supply connector 3260 into the SSD 3200. The power supply 3240 includes an auxiliary power supply 3241. The auxiliary power supply 3241 is configured to supply power so that the SSD 3200 can be normally shut down when a sudden power off occurs. The auxiliary power supply 3241 may include super capacitors capable of charging the power supply PWR.

The SSD controller 3210 exchanges signals SGL with the host device 3100 through the signal connector 3250. Here, the signal SGL will include a command, an address, data, and the like. The signal connector 3250 may be a parallel advanced technology attachment (PATA), a serial advanced technology attachment (SATA), a small computer small interface (SCSI), a serial SCSI (SAS), or the like depending on the interface method of the host device 3100 and the SSD 3200. [ And the like.

16 is a block diagram exemplarily showing the SSD controller shown in FIG. Referring to FIG. 15, the SSD controller 3210 includes a memory interface 3211, a host interface 3212, an ECC unit 3213, a central processing unit 3214, and a RAM 3215.

The memory interface 3211 is configured to provide commands and addresses to the non-volatile memory devices 3231-323n. The memory interface 3211 is configured to exchange data with the nonvolatile memory devices 3231 to 323n. The memory interface 3211 can perform scattering of data transferred from the buffer memory device 3220 to the respective channels CH1 to CHn under the control of the central processing unit 3214. [ The memory interface 3211 transfers the data read from the nonvolatile memory devices 3231 to 323n to the buffer memory device 3220 under the control of the central processing unit 3214. [

The host interface 3212 is configured to provide interfacing with the SSD 3200 in correspondence with the protocol of the host device 3100. For example, the host interface 3212 may be coupled to the host device 3100 through any one of Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer Small Interface (SCSI) ). ≪ / RTI > The host interface 3212 may perform a disk emulation function to support the host device 3100 to recognize the SSD 3200 as a hard disk drive (HDD).

The ECC unit 3213 is configured to generate parity bits based on data transmitted to the non-volatile memory devices 3231 to 323n. The generated parity bits may be stored in a spare area of the nonvolatile memories 3231 to 323n. ECC unit 3213 is configured to detect errors in the data read from non-volatile memory devices 3231-323n. If the detected error is within the correction range, it is configured to correct the detected error.

The central processing unit 3214 is configured to analyze and process the signal SGL input from the host device 3100. [ The central processing unit 3214 controls all operations of the SSD controller 3210 in response to a request from the host apparatus 3100. [ The central processing unit 3214 controls the operation of the buffer memory device 3220 and the nonvolatile memory devices 3231 to 323n in accordance with the firmware for driving the SSD 3200. RAM 3215 is used as a working memory device to drive such firmware.

17 is a block diagram illustrating an exemplary computer system in which a data storage device according to an embodiment of the present invention is mounted. 17, a computer system 4000 includes a network adapter 4100, a central processing unit 4200, a data storage 4300, a RAM 4400, a ROM 4500 And a user interface 4600. Here, the data storage device 4300 may be composed of the data storage device 120 shown in FIG. 1, the data storage device 1200 shown in FIG. 12, or the SSD 3200 shown in FIG.

The network adapter 4100 provides interfacing between the computer system 4000 and external networks. The central processing unit 4200 performs various operation processes for driving an operating system or an application program residing in the RAM 4400. [

The data storage device 4300 stores necessary data in the computer system 4000. For example, an operating system, an application program, various program modules, program data, and user data for driving the computer system 4000 Is stored in the data storage device 4300.

The RAM 4400 may be used as an operating memory device of the computer system 4000. At the time of booting, the RAM 4400 stores an operating system, an application program, various program modules read from the data storage device 4300, and program data required for driving programs, Is loaded. ROM 4500 stores a basic input / output system (BIOS) which is a basic input / output system activated before the operating system is operated. Information is exchanged between the computer system 2000 and the user via the user interface 4600. [

Although not shown in the drawings, it will be appreciated that the computer system 4000 may further include devices such as a Battery, an Application chipset, a Camera Image Processor (CIS), and the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents. It will be appreciated that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention.

100: Data processing system
110: Host device
120: Data storage device
130: controller
140: Data storage medium

Claims (5)

Nonvolatile memory devices; And
A controller configured to control operation of the non-volatile memory devices,
Wherein the controller maps the physical addresses of the non-volatile memory devices to the logical addresses provided from the host device, and if the data is determined to control the multi-plane operation, Mapping the physical address to a logical address to which the non-volatile memory devices are connected and performing an interleaving operation on the non-volatile memory devices using the remapped physical address,
Wherein the remapped physical address is selected from physical addresses other than physical addresses that can not be programmed in a multi-plane manner by addresses of physical page the data is programmed to. ◈ Claim 2 is abandoned due to payment of registration fee. The method according to claim 1,
Wherein the controller determines to control the multi-plane operation based on the size of the data requested to be accessed. ◈ Claim 3 is abandoned due to the registration fee. The method according to claim 1,
Wherein the controller determines to control the multi-plane operation based on the size of the data to be accessed in the future. ◈ Claim 4 is abandoned due to the registration fee. The method according to claim 1,
Wherein the controller is configured to control multi-plane operation in parallel for two or more pages of a multi-page comprising two or more pages contained in any one of the non-volatile memory devices. delete

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