KR101989362B1 - Pass-Transistor and Buck-Converter including of Pass-Transistor - Google Patents

Abstract

A buck-converter comprises: a switching unit comprising a first transistor-column including a plurality of first type transistors arranged in a first column, a second transistor-column arranged in a second column adjacent to the first column, and including a plurality of second type transistors different from the first type, a third transistor-column, a plurality of the first type transistors, arranged in a third column opposite to the first column with respect to the second column, and a fourth transistor-column, a plurality of the second type transistors, arranged in a fourth column opposite to the second column with respect to the third column; an inductor connected to an output of the switching unit; and a capacitor connected with the inductor in series or in parallel, wherein the first transistor-column and the third transistor-column are connected in parallel, the second transistor-column and the fourth transistor-column are connected in parallel, a gate of the first transistor-column and a gate of the second transistor-column are commonly connected to a control signal, a source terminal of the first transistor-column is connected to a first voltage, and a source terminal of the second transistor-column is connected to a second voltage. Thus, voltage overshoot is reduced.

Description

[0001] The present invention relates to a pass-transistor and a pass-transistor including a pass transistor and a pass transistor,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pass transistor and a buck-converter including the pass transistor, and more particularly to a pass transistor and a buck-converter including the pass transistor.

In order to efficiently manage the battery usage time of wireless communication devices, the use of a buck-converter with high power efficiency is increasing. In such a converter, the switching noise caused by the switching operation lowers the performance of the system, and thus pass-transistors having less switching noise are being studied.

In the case of a DC-DC synchronous buck converter, a pass transistor composed of NMOS and PMOS is mainly used for the switching operation. In this case, the pass transistor has more than hundreds of fingers to provide a large output current. As a result, a large switching current flows through the output terminal of the pass-transistor and a large voltage overshoot occurs. This causes a problem of emission of electromagnetic waves.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pass-transistor and a buck-converter including the pass-transistor for reducing a voltage overshoot in a buck-converter by changing the arrangement of pass-transistors without increasing the layout area.

The problems to be solved by the present invention are not limited to the above-mentioned problem (s), and another problem (s) not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a buck-converter including: a first transistor-column including a plurality of first-type transistors arranged in a first column; A second transistor-column disposed in a second column adjacent to the first column, the second transistor-column comprising a plurality of second type transistors different from the first type; A third transistor disposed in a third column opposite the first column with respect to the second column, the third transistor being a plurality of the first type transistors; And a fourth transistor arranged in a fourth column opposite to the second column with respect to the third column, the fourth transistor being a plurality of the second type transistors; An inductor connected to an output of the switching unit, and a capacitor connected in series or in parallel with the inductor, wherein the first transistors and the third transistors are connected in parallel, and the second transistors and the fourth transistors Wherein a gate of the first transistors and a gate of the second transistors are commonly connected to a control signal and a source terminal of the first transistors is connected to a first voltage, And is connected to the second voltage.

The number of transistors included in the first transistor-column and the number of transistors included in the second transistor-column may be the same.

The first transistor-column may be connected in parallel with the first-type transistors included in the first transistor-column.

According to another aspect of the present invention, there is provided a pass-transistor comprising: a first transistor-column including a plurality of first-type transistors arranged in a first column; A second transistor-column disposed in a second column adjacent to the first column, the second transistor-column comprising a plurality of second type transistors different from the first type; A third transistor disposed in a third column opposite the first column with respect to the second column, the third transistor being a plurality of the first type transistors; And a fourth transistor row arranged in a fourth column opposite the second column with respect to the third column, the fourth transistor row being a plurality of the second type transistors.

By alternately arranging the NMOS and PMOS columns to implement a pass-transistor and a buck-converter including it, the voltage overshoot can be reduced without increasing the overall layout area.

1 is a block diagram of a buck-converter in accordance with an embodiment of the present invention.
2 is a block diagram of a pass-transistor 200 according to an embodiment of the present invention.
3 is a graph showing a change in current flowing in the inductor 110 according to the PWM 310 according to an embodiment of the present invention.
4 is a diagram illustrating voltage overshoot variation at an output terminal according to the arrangement of the PMOS 210 and the NMOS 220 in the pass-transistor 200 according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. For example, without departing from the scope of the present invention, a first component may be termed a second component, and similarly, the term " second component " The second component may also be referred to as the first component. The term < RTI ID = 0.0 > and / or < / RTI > includes any combination of a plurality of related listed items or any of the plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a buck-converter in accordance with an embodiment of the present invention.

The buck-converter 100 according to an embodiment of the present invention includes a pass-transistor 200, an inductor 110, and a capacitor 120.

The pass-transistor 200 is composed of a plurality of transistors of the first type and a plurality of transistors of the second type. In this case, the first type transistor may be a PMOS transistor and the second type transistor may be an NMOS transistor.

The source terminal of the PMOS 210 is connected to the first voltage (for example, Vdd 240), and the PWM terminal 310 is applied to the gate terminal. The drain terminal of the PMOS 210 is connected to the drain terminal of the NMOS 220, which will be described later.

The source terminal of the NMOS 220 is connected to the second voltage (for example, Vss 250), and the PWM terminal 310 is applied to the gate terminal. The drain terminal of the NMOS 220 is connected to the drain terminal of the PMOS 210.

The PMOS 210 and the NMOS 220 are turned on or off according to the PWM 310.

A detailed description of the configuration of the pass transistor 200 will be described later with reference to FIG.

The inductor 110 is connected to the output terminal of the pass-transistor 200, that is, the drain terminal of the NMOS and the PMOS.

Capacitor 120 is connected in series or in parallel with inductor 110 to deliver voltage to the load.

Hereinafter, for convenience of description, a change in the current flowing through the inductor 110 according to the PWM 310 will be described with reference to FIG.

3 is a graph showing a change in current flowing in the inductor 110 according to the PWM 310 according to an embodiment of the present invention.

FIG. 3A is a diagram illustrating a voltage level of the PWM 310, and FIG. 3B is a diagram illustrating a current flowing in an inductor 120. Referring to FIG.

PWM 310 may appear alternating between a voltage small enough to turn on PMOS 210 and a voltage large enough to turn NMOS 220 on.

The PMOS 210 is turned off and the NMOS 220 is turned on when the PWM 310 indicates a voltage equal to or higher than a threshold value (hereinafter, a high signal). Further, when the PWM 310 indicates a voltage lower than a threshold value (hereinafter referred to as a low signal), the PMOS 210 is turned on and the NMOS 220 is turned off. Accordingly, when the PWM 310 indicates a high signal, a current is supplied to the inductor 110 through the NMOS 220 and a current is supplied to the inductor 110 through the PMOS 210 when the PWM 310 indicates a low signal. .

As a result, the buck-converter 100 can output the desired voltage by appropriately adjusting the time at which the PWM 310 indicates a high signal and the time at which a low signal is indicated.

2 is a block diagram of a pass-transistor 200 according to an embodiment of the present invention.

The pass-transistor 200 according to an embodiment of the present invention includes a first transistor-column 211, a second transistor-column 221, a third transistor-column 212 and a fourth transistor-column 222, . ≪ / RTI >

The first transistor row 211 is disposed in the first column 201 and may include a plurality of first type transistors (e.g., PMOS).

The second transistor row 221 is disposed in a second column 202 adjacent to the first column 201 and includes a plurality of second type transistors (e.g., NMOS) different from the first type .

The third transistor-column 212 is disposed in a third column 203 opposite the first column 201 with respect to the second column 203, and a plurality of first-type transistors (e.g., PMOS). ≪ / RTI >

The fourth transistor-row 222 is disposed in a fourth column 204 opposite the second column 202 with respect to the third column 203, and a plurality of second-type transistors (e.g., NMOS).

In this case, the number of transistors included in the first transistor-column 211 and the number of transistors included in the second transistor column 221 are the same and can be connected in parallel.

The gate of the first transistor-column 211 and the gate of the second transistor-column 221 are commonly connected to a control signal and the source terminal of the first transistor-column 211 is connected to the first voltage- And the source terminal of the second transistor-column 221 may be coupled to a second voltage (e.g., Vdd). In addition, the drain terminal of the first transistor-column 211 may be connected to the drain terminal of the second transistor-column 221.

Hereinafter, for convenience of explanation, it is assumed that the first type transistor is a PMOS, the second type transistor is an NMOS, and the pass transistor 200 includes four columns of PMOSs and four columns of NMOSs. At this time, the types of transistors arranged in each column are shown in Table 1 below.

Column number First column Second column Column 3 Fourth column Column 5 Column 6 Column 7 Column 8 type P N P N P N P N

Referring to Table 1, PMOS and NMOS are arranged alternately in each column.

The pass-transistors included in the buck-converter 100 are composed of a large number of fingers in order to output a large current. By alternately arranging the NMOS and PMOS columns constituting the pass-transistor, Thereby reducing the voltage overshoot that occurs and stabilizing the system.

4 is a diagram illustrating voltage overshoot variation at an output terminal according to the arrangement of the PMOS 210 and the NMOS 220 in the pass-transistor 200 according to an embodiment of the present invention.

4A is a pass-transistor in which a PMOS 210 is disposed on the left side and an NMOS 220 is disposed on the right side.

4B is a cross-transistor 200 in which the PMOS 210 and the NMOS 220 are arranged at an intersection as shown in FIG.

FIG. 4C is a graph comparing the voltage overshoot generated at the output terminal of the pass transistor in FIGS. 4A and 4B. FIG.

Referring to FIG. 4, it can be seen that the voltage overshoot at the output terminal of the pass-transistor 200 in which the PMOS 210 and the NMOS 220 are arranged at an intersection is smaller as in FIG. That is, the voltage overshoot can be reduced by changing the arrangement of the PMOS 210 and the NMOS 220 without changing the area of the entire layout.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and / or features of the present invention, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, Modification is possible. Accordingly, the spirit of the present invention should be understood only in accordance with the following claims, and all equivalents or equivalent variations thereof are included in the scope of the present invention.

100: Buck-Converter
110: inductor
120: Capacitor
200: pass-transistor
210: PMOS
220: NMOS

Claims (4)

A first transistor disposed in a first column, the first transistor comprising a plurality of first type transistors;
A second transistor-column disposed in a second column adjacent to the first column, the second transistor-column comprising a plurality of second type transistors different from the first type;
A third transistor disposed in a third column opposite the first column with respect to the second column, the third transistor including a plurality of the first type transistors; And
A fourth transistor arranged in a fourth column opposite to the second column with respect to the third column, the fourth transistor including a plurality of the second type transistors;
An inductor connected to the output of the switching unit and
And a capacitor connected in series or in parallel with the inductor,
Wherein the first transistor-column and the third transistor-column are connected in parallel, the second transistor-column and the fourth transistor-column are connected in parallel,
The gate of the first transistor-column and the gate of the second transistor-column are commonly connected to a control signal, the source terminal of the first transistor-column is connected to the first voltage, and the source terminal of the second transistor- Buck-converter connected to 2 voltage. The method according to claim 1,
Wherein the number of transistors included in the first transistor-column and the number of transistors included in the second transistor-column are the same. The method of claim 1, wherein the first transistor-
And the first type transistors included in the first transistor row are connected in parallel. A first transistor disposed in a first column, the first transistor comprising a plurality of first type transistors;
A second transistor-column disposed in a second column adjacent to the first column, the second transistor-column comprising a plurality of second type transistors different from the first type;
A third transistor disposed in a third column opposite the first column with respect to the second column, the third transistor including a plurality of the first type transistors; And
And a fourth transistor row arranged in a fourth column opposite to the second column with respect to the third column and including a plurality of the second type transistors,
Wherein the first transistor-column and the third transistor-column are connected in parallel, the second transistor-column and the fourth transistor-column are connected in parallel,
The gate of the first transistor-column and the gate of the second transistor-column are commonly connected to a control signal, the source terminal of the first transistor-column is connected to the first voltage, and the source terminal of the second transistor- Pass through 2-voltage transistor

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