KR101983215B1 - Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The present invention relates to a display device having a plurality of gate wirings formed by intersecting a display region having a plurality of pixel regions and a display region on a substrate on which first, second, third and fourth non-display regions are defined, And a data line; A plurality of gate auxiliary wirings formed in the same layer on which the data wirings are formed and connected to any one of the plurality of gate wirings in parallel with the data wirings; A common wiring formed in parallel with the data wiring in the same layer on which the data wiring is formed; A thin film transistor connected to each of the gate wirings and the data wirings and formed in each of the pixel regions; A first protective layer formed on the entire surface of the substrate over the thin film transistor; A planarization layer formed on the display region over the first protective layer; A common electrode formed on the planarization layer in the display region; A second protective layer formed on the entire surface of the substrate over the common electrode; And a pixel electrode having a plurality of first openings formed in a bar shape and connected to one electrode of the thin film transistor in each pixel region over the second passivation layer, And a first connection pattern contacting the protrusion and the gate wiring at the same time, wherein the common wiring and the common electrode are connected to a second connection pattern The present invention also provides an array substrate for a fringe field switching mode liquid crystal display and a method of manufacturing the same.

Description

[0001] The present invention relates to an array substrate for a fringe field switching mode liquid crystal display device and a manufacturing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a fringe field switching mode liquid crystal display device array capable of reducing the width of non-display regions on the left and right sides of a display region, realizing a narrow bezel, Substrate and a method of manufacturing the same.

Recently, liquid crystal display devices have been attracting attention as next generation advanced display devices with low power consumption, good portability, and high value-added.

Of these liquid crystal display devices, an active matrix type liquid crystal display device having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, .

In general, a liquid crystal display device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming thin film transistors and pixel electrodes, and a color filter substrate manufacturing process for forming color filters and common electrodes, And a liquid crystal interposed therebetween.

1, which is an exploded perspective view of a general liquid crystal display device, the array substrate 10 and the color filter substrate 20 are bonded to each other with a liquid crystal layer 30 interposed therebetween The lower array substrate 10 includes a plurality of gate wirings 14 and data wirings 16 that are longitudinally and laterally arranged on the upper surface of a transparent substrate 12 to define a plurality of pixel regions P A thin film transistor T is provided at the intersection of these two wirings 14 and 16 and is connected in a one-to-one correspondence with the pixel electrode 18 provided in each pixel region P.

The upper portion of the color filter substrate 20 facing the array substrate is covered with a non-display region such as the gate wiring 14, the data wiring 16, and the thin film transistor T, Green, and blue color filter layers 26 (red, green, and blue), which are sequentially and repeatedly arranged in correspondence to the respective pixel regions P within these lattices, are formed in the lattice-like black matrix 25 And a transparent common electrode 28 is provided over the entire surface of the black matrix 25 and the red, green and blue color filter layers 26.

Although not shown in the drawing, the array substrate and the color filter substrates 10 and 20 are sealed in a sealant or the like along the edges in order to prevent leakage of the liquid crystal layer 30 interposed therebetween, An upper and a lower alignment films for providing reliability in the molecular alignment direction of the liquid crystal are interposed in the boundary portion between the liquid crystal layer 10 and the liquid crystal layer 30 and at least one outer side face of each substrate 10, Is provided.

In addition to this configuration, a backlight unit (not shown) used as a light source is provided on the outer side surface of the array substrate 10, and is mounted on the array substrate 10 to drive the liquid crystal layer 30 (Not shown).

On the other hand, in the liquid crystal display device having such a configuration, the liquid crystal molecules in the liquid crystal layer are provided on different substrates and are driven by the vertical electric field induced between the opposing pixel electrodes and the common electrode.

However, a liquid crystal display device in which a liquid crystal is driven by a vertical electric field has a problem that the viewing angle characteristics are not excellent. To overcome this problem, a liquid crystal display device of a lateral electric field has been proposed.

In such a transverse electric field liquid crystal display device, the pixel electrode and the common electrode are formed to be staggered on the same substrate, and a horizontal electric field in a direction parallel to the substrate is induced between the two electrodes, so that the liquid crystal molecules are driven by the horizontal electric field, And the transverse electric field type liquid crystal display device which performs such driving has an improved viewing angle as compared with the liquid crystal display device of the vertical electric field type.

However, such a transverse electric field type liquid crystal display device has a disadvantage in that the aperture ratio and the transmittance are low, although the view angle is excellent.

Therefore, a fringe field switching mode liquid crystal display (LCD) driving liquid crystal by a fringe field has been proposed in order to improve the disadvantage of such a lateral electric field liquid crystal display device.

In the fringe field switching mode liquid crystal display device, a common electrode and a pixel electrode are formed on an array substrate with an insulating layer interposed therebetween. An electrode located at an upper portion of the two electrodes is configured to have a plurality of openings in the form of a bar, Field is formed to drive the liquid crystal molecules, and thus the viewing angle characteristics are excellent and the aperture ratio and transmittance are improved as compared with the transverse electric field type liquid crystal display device.

As shown in FIG. 2 (a plan view schematically showing a printed circuit board and an FPC mounted in a conventional fringe field switching mode liquid crystal display device) in a fringe field switching mode liquid crystal display device having such a configuration, A driving unit (not shown) is implemented in a printed circuit board (PCB) 50. The printed circuit board 50 is mounted on a flexible printed circuit board (FPC) Display region NA1 of the array substrate 41 on which the data pad portion alehtl is implemented.

A non-display area NA4 (not shown) of the left side and / or the right side of the display area DA where one end of a gate wiring (not shown) other than the non-display area NA1 on which the printed circuit board 50 is mounted is located. And NA3 are connected to an FPC 61 having a gate driving IC 71 itself or a gate driving IC 71 in contact with a gate pad (not shown) formed at one end of the gate wiring (not shown) .

The fringe field switching mode liquid crystal display device 10 having the above-described configuration is actively applied to various electronic devices such as a TV, a monitor, a notebook computer, a mobile phone, and a PDA.

In recent years, in order to realize a slim design of a final product, for example, a monitor or a TV, a display device is required to be lightweight and thin, and a bezel defined as a width of a non-display area outside the display area, A display device of a narrow bezel type in which the width of a non-display area located at a maximum is reduced.

Therefore, in order to meet this trend, much efforts have been made to realize a narrow bezel, which is a trend required for a display device, even in a fringe field switching mode liquid crystal display device.

In order to reduce the width of the non-display area on the left and right sides of the display area, it is preferable to omit the region where the FPC having the gate IC itself or the gate IC is mounted. To this end, Each of the gate sub-wirings being connected to corresponding one of the gate wirings, a gate pad formed at one end of the gate sub-wirings, and an FPC having gate ICs facing each other with respect to the display region So that the FPC having the data IC is mounted symmetrically.

Therefore, since the FPC is mounted only in correspondence with the non-display regions located above and below the display region, the non-display regions on both sides of the display region can be reduced in width to realize a narrow bezel.

However, since the fringe field switching mode liquid crystal display device having such a structure is further provided with a gate auxiliary wiring connected to the gate wiring in the inside of the array substrate and a constitution for electrically connecting these elements, There is an increasing problem.

The mask process includes a process of applying a photoresist, exposure using an exposure mask, development of a photoresist, etching, and stripping of a photoresist. Such a mask process raises the manufacturing cost of the product, It is desirable to minimize the cost in order to reduce the cost.

However, in order to manufacture an array substrate for a fringe field switching mode liquid crystal display device having the above-described gate auxiliary wiring, a total of seven mask processes are underway.

The seventh mask process includes a first mask process for forming a gate electrode and a gate line, a second mask process for forming a semiconductor layer, a data line, a source and a drain electrode, a third mask process for forming a planarization layer, A fourth mask process for exposing the gate wiring to the protective layer and the gate insulating film, a fifth mask process for forming the common electrode, forming a second protective layer, exposing the drain electrode to the second protective layer and the first protective layer, A sixth mask process for forming the pixel electrode, and a seventh mask process for forming the pixel electrode.

Therefore, in the conventional array substrate for the fringe field switching mode liquid crystal display, which further includes the gate auxiliary wiring connected to the gate wiring for realizing the narrow bezel described above, it is required to reduce the number of mask processes in order to reduce the manufacturing cost It is true.

SUMMARY OF THE INVENTION The present invention has been devised to solve the problems described above, and it is an object of the present invention to provide a display device having a gate auxiliary wiring connected to a gate wiring in order to reduce a width of a non- And an object of the present invention is to provide an array substrate for a fringe field switching mode liquid crystal display device which can be completed through a mask process and a method of manufacturing the same.

According to an aspect of the present invention, there is provided an array substrate for a fringe field switching mode liquid crystal display, including a display region having a plurality of pixel regions, first, second, third, and fourth A plurality of gate wirings and data wirings formed to intersect with each other with the gate insulating film interposed in the display region on the substrate defined in the non-display region; A plurality of gate auxiliary wirings formed in the same layer on which the data wirings are formed and connected to any one of the plurality of gate wirings in parallel with the data wirings; A common wiring formed in parallel with the data wiring in the same layer on which the data wiring is formed; A thin film transistor connected to each of the gate wirings and the data wirings and formed in each of the pixel regions; A first protective layer formed on the entire surface of the substrate over the thin film transistor; A planarization layer formed on the display region over the first protective layer; A common electrode formed on the planarization layer in the display region; A second protective layer formed on the entire surface of the substrate over the common electrode; And a pixel electrode having a plurality of first openings formed in a bar shape and connected to one electrode of the thin film transistor in each pixel region over the second passivation layer, And a first connection pattern contacting the protrusion and the gate wiring at the same time, wherein the common wiring and the common electrode are connected to a second connection pattern And is electrically connected.

At this time, the planarization layer is provided with a gate hole corresponding to the protruding portion and the gate wiring adjacent thereto, and the second and first protective layers are removed inside the gate hole to expose the protruding portion, 1 protection layer and the gate insulating film are removed to expose the gate wiring, and the first connection pattern is in contact with the protruding portion and the gate wiring exposed in the gate hole.

In the planarization layer, a common hole is provided corresponding to the common wiring, and one end of the common electrode is located above the first protection layer inside the common hole, and the second and first protection layers are removed And the second connection pattern is formed so as to contact the common wiring exposed at the inside of the common hole and one end of the common electrode at the same time.

The common electrode includes a second opening corresponding to the thin film transistor, a third opening corresponding to the gate hole and having a larger area than the gate hole, and a fourth opening corresponding to the common hole, And one end of the common wiring located at the boundary of the fourth opening is located inside the gate hole.

A data pad electrode is provided at one end of the data line, and a gate pad electrode having the same stacking configuration as that of the data pad electrode is provided at one end of the gate auxiliary line. The data pad electrode and the gate pad electrode And is located in the first or second non-display area.

And when the two adjacent pixel regions are defined as a first region, the gate wiring is arranged in a pair at a boundary of the first region on a boundary of the first region and adjacent to each other in a side-by-side manner, And the gate sub-lines and the common sub-lines are disposed at two pixel-region boundaries provided in the first regions, respectively.

At this time, only one of the gate auxiliary wiring and the common wiring is formed at the boundary between the two pixel regions in each of the first regions.

On the other hand, the gate auxiliary wiring is formed by an integral multiple of the gate wiring so as to correspond to all gate wirings.

In the first or second non-display area located above or below the display area, an FPC via a data driving IC connected to the data line is mounted. In the first or second non-display area, A gate driving IC connected to the gate auxiliary wiring is mounted, or an FPC via a gate driving IC is mounted.

A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention includes forming a display region having a plurality of pixel regions and defining first, second, third, and fourth non-display regions Forming a plurality of gate wirings and a gate electrode connected to each of the plurality of gate wirings in the display region on the substrate; Forming a gate insulating film over the gate wiring and the gate electrode; A plurality of data lines crossing the plurality of gate wirings over the gate insulating film; and a gate auxiliary wiring disposed in parallel with the data wirings and having protruding portions branched in parallel to any one of the plurality of gate wirings Forming a thin film transistor by forming source and drain electrodes spaced apart from each other on the semiconductor layer and the semiconductor layer corresponding to the gate electrode; Forming a first protective layer on the entire surface of the substrate over the data line; Forming a planarization layer formed on the entire surface of the display region over the first protective layer and having a drain hole and a gate hole corresponding to the drain electrode and the protruding portion and the gate wiring adjacent thereto, ; Forming a common electrode on the planarization layer over the entire surface of the display region, the common electrode having a first opening corresponding to the thin film transistor and having a second opening corresponding to the gate hole; Forming a second protective layer on the entire surface of the substrate over the common electrode, selectively exposing the drain electrode in the drain hole by patterning the gate insulating film of the second protective layer and the first protective layer, Exposing the protrusion and the gate wiring; Forming a pixel electrode having a plurality of third openings in a bar shape in contact with the drain electrode through the drain hole in each pixel region over the second passivation layer, And forming a first connection pattern in contact with the protrusion and the gate wiring.

At this time, the step of forming the data wiring and the gate auxiliary wiring includes a step of forming a common wiring on the gate insulating film in parallel with the data wiring.

And when the two adjacent pixel regions are defined as a first region, the gate wiring is arranged in a pair at a boundary of the first region on a boundary of the first region and adjacent to each other in a side-by-side manner, And the gate auxiliary wiring or the common wiring is arranged at the boundary of two pixel regions provided in each of the first regions, . At this time, only one of the gate auxiliary wiring and the common wiring is formed at the boundary between the two pixel regions in each of the first regions.

The step of forming the planarization layer including the drain hole and the gate hole may include forming a common hole exposing the first protective layer in correspondence with a part of the common wiring.

And forming the common electrode having the first and second openings includes forming a third opening corresponding to the common hole, wherein the boundary of the third hole is located inside the common hole .

The step of exposing the drain electrode in the drain hole and the step of exposing the protrusion and the gate wiring in the gate hole may be performed by patterning the second passivation layer and the first passivation layer, And exposing the side of the common electrode forming the boundary of the opening and the common wiring.

And forming the first connection pattern with the pixel electrode includes forming a second connection pattern in contact with the side end of the common electrode and the common wiring within the common hole.

The forming of the data line and the gate sub wiring may include forming a data pad electrode connected to one end of the data line in the first or second non-display area, And forming a gate pad electrode connected to one end of the gate auxiliary wiring, exposing the drain electrode in the drain hole, and exposing the protrusion and the gate wiring in the gate hole, And exposing the data pad electrode and the gate pad electrode by patterning the first passivation layer and the first passivation layer, wherein forming the first connection pattern with the pixel electrode comprises exposing the data pad electrode and the gate pad electrode, Forming an auxiliary pad electrode and a gate auxiliary pad electrode, respectively.

The array substrate for a liquid crystal display according to the embodiment of the present invention may be configured such that an FPC having a gate driving IC or a gate driving IC is mounted on a non-display area located on the left and right of the display area, And the width of the non-display region located at the left and right of the display region is minimized, thereby realizing the narrow bezel.

Further, in the case of the array substrate completed in the manufacturing method according to the embodiment of the present invention, the mask process is performed only six times in total, so that the conventional mask process can be performed, Thereby reducing the manufacturing cost.

The array substrate for a liquid crystal display according to an embodiment of the present invention is formed in place of the data line in a portion where a gate auxiliary wiring is formed in addition to a general array substrate in a display region but the data wiring is reduced, There is an advantage to be able to do.

1 is an exploded perspective view of a general liquid crystal display device.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a fringe field switching mode liquid crystal display device.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display (LCD) having an array substrate for a fringe field switching mode liquid crystal display, and more particularly,
4 is a plan view schematically showing a part of a display region of an array substrate for a liquid crystal display according to an embodiment of the present invention;
5 is an enlarged view of region A in Fig.
FIG. 6 is a cross-sectional view of the portion cut along line VI-VI of FIG. 5; FIG.
7 is a cross-sectional view of a portion cut along line VII-VII of FIG. 5;
8 is a cross-sectional view of a section cut along the section line VIII-VIII.
Fig. 9 is a cross-sectional view of the portion cut along line IX-IX of Fig. 5; Fig.
FIG. 10 is a cross-sectional view of a data pad unit (or a gate pad unit included in the second non-display region) provided in a first non-display region in a fringe field switching mode liquid crystal display device according to an embodiment of the present invention.
Figs. 11A to 11H are cross-sectional views of the manufacturing process steps of the portion cut along the line VI-VI of Fig. 5;
Figs. 12A to 12H are cross-sectional views showing steps taken along the cutting line VII-VII taken along line VII-VII of Fig. 5;
Figs. 13A to 13H are cross-sectional views showing steps of manufacturing steps of the portion cut along the cutting line VIII-VIII of Fig. 5;
Figs. 14A to 14H are cross-sectional views showing steps of manufacturing steps of the portion cut along line IX-IX of Fig. 5;
FIGS. 15A to 15H are cross-sectional views illustrating a method of fabricating a data pad portion (or a gate pad portion provided in the second non-display region) in a first non-display region in a fringe field switching mode liquid crystal display device according to an embodiment of the present invention. Stepwise process sectional view.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a plan view schematically showing a state in which an FPC having a printed circuit board and a driving IC is mounted in a liquid crystal display device having an array substrate for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention.

As shown in the drawings, in a liquid crystal display device 101 having an array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, the array substrate 110 is provided with a display region DA, NA1, NA2, NA3, and NA4 of the display area DA outside the display area DA, and the first to fourth non-display areas NA1, NA2, NA3, Is connected to the printed circuit board 190 through the FPC 162 having the data driving IC 172 in the first non-display area NA1 located on the upper side of the display area DA, The FPC 163 provided with the gate driving IC 173 is mounted on the second non-display area NA2.

Therefore, the liquid crystal display device 101 having the array substrate 110 according to the embodiment of the present invention includes the first to fourth non-display areas NA1, NA2, NA3, and NA4 outside the display area DA, The fourth and third ratios located on the left and right sides of the display area DA except for the first non-display area NA1 located on the upper side of the display area DA and the second non-display area NA1 located on the lower side, Since the gate driving ICs 173 or the FPCs 163 having the gate driving ICs 173 are not mounted on the display areas NA4 and NA3, these components are arranged in the non-display area on the left or right side of the display area (DA in FIG. NA4, and NA3 of the conventional fringe field switching mode liquid crystal display device (40 of FIG. 2), the width of the narrow bezel is reduced.

At this time, although not shown in the drawing, the printed circuit board 190 or the data driving IC 172 and the gate driving IC 173 are disposed on the left or right side of the display area DA, (Not shown) of a plurality of auxiliary wirings (not shown) provided in the non-display areas NA4 and NA3.

In this case, the plurality of auxiliary wirings (not shown) are electrically connected to a plurality of log wirings (not shown) and a common electrode (not shown) for electrical connection of the gate and data driving ICs 172 and 173 Auxiliary common wiring (not shown), and the like.

The auxiliary wiring (not shown) provided in the third or fourth non-display area NA3 or NA4 is much smaller than the gate pad portion (not shown) for mounting the gate FPC 163 It is not necessary to implement the narrow bezel even if the plurality of auxiliary wirings (not shown) are provided in the third or fourth non-display areas NA3 and NA4.

In the case of the array substrate 110 for the fringe field switching mode liquid crystal display according to the embodiment of the present invention, the FPC 163 having the gate driving IC 173 corresponding to the second non-display area NA2, The gate driving IC 173 may be directly mounted on the array substrate 101 without mediation of the FPC 163 in the second non-display area NA2 as a modification thereof .

The printed circuit board 190 or the data driving IC 172 and the gate driving IC 173 are arranged in the display area DA in the array substrate 110 according to the modification example of this embodiment having such a configuration (Not shown) provided in the fourth and third non-display areas NA4 and NA3 located on the left or right side.

In the case of the array substrate 110 for the fringe field switching mode liquid crystal display according to the embodiment of the present invention having such a configuration or a modification thereof, the first and second ratios, respectively, located on the upper and lower sides of the display area DA, The display areas NA1 and NA2 are respectively connected to an FPC 163 having a data pad (not shown) and a gate driving IC 173 for electrical connection with an FPC 162 having a data driving IC 172 (Not shown) for electrical connection with the driving IC 173 for the gate itself so as to be similar in level to the width of the non-display area of the array substrate for a liquid crystal display device. However, The gate pad portions (not shown) for mounting the gate FPC 163 or the gate driving IC 173 are not required for the fourth and third non-display regions NA4 and NA3, To implement the narrow bezel. It has an advantage.

The narrow bezel structure in which the widths of the non-display areas NA4 and NA3 on the left and right sides of the display area DA can be reduced corresponds to the array substrate for the fringe field switching mode liquid crystal display 110 according to the embodiment of the present invention and its modification The structure of the array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment (and a modification example) of the present invention and a manufacturing method thereof will be described in detail below.

At this time, the array substrate 110 for the fringe field switching mode liquid crystal display according to the embodiment and the modified example of the present invention is provided with the display region (not shown) of the non-display regions NA1, NA2, NA3, and NA4 outside the display region DA The FPC 163 electrically connected to the gate wiring (not shown) in the first and second non-display areas NA1 and NA2 on the upper side or the lower side and the gate driving IC 173 is mounted There is a difference only in whether or not the gate driving IC 173 itself is directly mounted on the array substrate 110 and the difference between the display area DA and the constituent elements provided in the first and second non-display areas NA1 and NA2 And the formation thereof are the same. Therefore, only the constitution and manufacturing method of the array substrate (110 of FIG. 3) according to the embodiment of the present invention will be described with respect to the structure of the following components.

FIG. 4 is a plan view schematically showing a part of a display region of an array substrate for a liquid crystal display according to an embodiment of the present invention, and FIG. 5 is an enlarged view of region A in FIG. 7 is a cross-sectional view taken along the section line VII-VII of FIG. 5, and FIG. 8 is a cross-sectional view taken along the section line VIII- FIG. 9 is a cross-sectional view of a portion cut along line IX-IX in FIG. 5, and FIG. 10 is a cross-sectional view taken along a line IX-IX in FIG. 10 in a fringe field switching mode liquid crystal display device according to an embodiment of the present invention. And a data pad portion (or a gate pad portion provided in the second non-display region) provided in the first non-display region. Here, for convenience of description, a portion where the thin film transistor Tr is formed in each of the pixel regions P1 and P2 is defined as a switching region TrA.

As shown, the array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention includes a low resistance metal material, such as aluminum (Al), in a display area DA on a substrate 110 of a transparent insulating material Al (AlN), copper (Cu), copper alloy, molybdenum and molybdenum alloy (MoTi), and is formed of a material having a first interval (2 A pair of gate wirings 113 composed of first and second gate wirings 113a and 113b are arranged parallel to one another in a direction spaced apart from each other by a distance The major axis of the pixel regions P1 and P2).

Although the first and second gate wirings 113a and 113b are shown as being bent at the boundaries of the pixel regions P1 and P2 in the drawing, the first and second gate wirings 113a and 113b may be formed without being bent.

The first and second gate wirings 113a and 113b are formed to have a plurality of bent portions to efficiently arrange the thin film transistor Tr, the drain holes dch and the gate holes gch so that the aperture ratio and the transmittance .

The gate electrode 114 is formed in each switching region TrA in such a manner as to extend from the first gate wiring 113a or the second gate wiring (not shown) .

Next, (not shown 113a,) of the plurality of the pair of gate wires of the gate electrode 114 over the substrate 110 isolated on the front arms, for materials for example consisting of a silicon oxide (SiO ₂₎ or silicon nitride (SiNx) A gate insulating film 120 is formed.

Aluminum (Al), an aluminum alloy (AlNd), a copper (Cu), a copper alloy, a molybdenum (Mo), and the like are formed on the gate insulating film 120, ) And a molybdenum alloy (MoTi), and a plurality of data lines 130 having a single layer or a multilayer structure are formed.

At this time, the regions surrounded by the pair of gate wirings 113 and the data wirings 130 intersecting with each other are formed in the same pixel line PL as a region Hereinafter, a region captured by the gate wiring 113 and the data wiring 130 is referred to as a first region P).

In addition, an active layer 123a made of pure amorphous silicon and a semiconductor layer 123b made of impurity amorphous silicon and formed of an ohmic contact layer 123b spaced apart from each other are formed in the switching region TrA above the gate insulating layer 120, And the source and drain electrodes 133 and 136 are formed on the semiconductor layer 123 in contact with the ohmic contact layer 123b.

The gate electrode 114, the gate insulating layer 120, the semiconductor layer 123, and the source and drain electrodes 133 and 136, which are sequentially stacked in the switching region TrA, And the source electrode 133 provided in the switching region TrA in each of the pixel regions P1 and P2 is formed in a form branched from the data line (not shown).

On the other hand, as a characteristic feature of the array substrate 110 for a liquid crystal display according to the present invention, two adjacent pixels (pixels) captured by the pair of gate wirings 113a and 113b and the data wirings 130 The gate insulating film 120 is formed at the boundary of the two pixel regions P1 and P2 passing through the center of the first region P made up of the regions P1 and P2 and more precisely, The gate auxiliary wiring 138 and the common wiring 139 are formed in parallel with the data wiring 130.

At this time, only one of the gate sub-wiring 138 or the common wiring 139 is formed in each of the first regions P.

A data pad electrode 137 is provided at one end of the data line 130 and a gate pad electrode having the same configuration as the data pad electrode 137 is formed at one end of the gate sub- The gate pad electrodes (not shown) and the data pad electrodes 137 are provided on the upper and / or lower sides of the display area DA, respectively, and first and / or second non-display areas (NA1, not shown).

As another characteristic configuration of the array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, two wirings 138 and 139 formed through the first region P, The gate sub-wiring 138 is provided with a protrusion 180 which is branched at the boundary of the pixel regions P1 and P2 in the direction in which the gate wiring 113 extends.

The protrusion 180 of the gate auxiliary wiring 138 and the adjacent gate wiring 113a or 113b are electrically connected by the first connection pattern 175. [

Each of the gate auxiliary wirings 138 is electrically connected to one of the gate wirings 113 of all the gate wirings 113 provided in the display area DA, Is preferably formed to have an integral multiple of at least the same as or more than the number of all the gate wirings 113 provided in the display area DA.

Meanwhile, in the display area DA of the array substrate 110 for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention, several to several tens of gate auxiliary wirings 138 are grouped, The common wiring 139 is formed so as to penetrate through the first region P.

 In the drawing, one common wiring line 139 is formed for each of the six gate auxiliary wiring lines 138 by forming six gate auxiliary wiring lines 138 as one group.

Therefore, the data lines 130 are sequentially referred to as first to nth data lines D1, D2, D3, ... from the left to the right of the display area DA, and the numbers D1 to Dn are assigned And the gate auxiliary wiring 138 is also referred to as first to n-th gate auxiliary wirings GA1, GA2, GA3 ....... When the numbers GA1 to GAn are given, The gate auxiliary wiring 138 and the common wiring 139 or Vcom are, for example,

The first data wiring D1, the first gate auxiliary wiring GA1, the second data wiring D2, the second gate auxiliary wiring GA2, the third data wiring D3 and the third gate auxiliary wiring GA3 ) / Fourth data wiring (D4) / fourth gate auxiliary wiring (GA4) / fifth data wiring (D5) / fifth gate auxiliary wiring (GA5) / sixth data wiring (D6) / sixth gate auxiliary wiring GA7 / seventh data wiring D7 / common wiring 139 or Vcom / eighth data wiring D8 / seventh gate auxiliary wiring GA7 /

.

At this time, the number of the common wirings 139 or Vcom can be appropriately adjusted depending on how many groups of the gate auxiliary wirings 138 are grouped.

Furthermore, the common wiring 139 or Vcom need not necessarily be formed in the same number corresponding to the same number of the gate auxiliary wirings 138, and the gate auxiliary wiring 138 may be formed by an integer multiple When the number of the data lines 130 is determined, an area between the data lines 130 to be formed with the gate sub-lines 138 is first determined, then gate assist lines 138 are formed with respect to these areas, The common wiring 139 or Vcom may be disposed corresponding to one region.

In the case of the array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, the pair of first and second gate wirings 113a and 113b intersecting each other, And a region surrounded by the data line 130 constitute a first region P having two neighboring pixel regions P1 and P2, and two adjacent pixel regions P1 and P2 in the first region P The gate auxiliary wiring 138 or the common wiring 70 is disposed at the central boundary of the pixel regions P1 and P2 so that the pair of first and second gate wirings 113a and 113b and the data wirings 130 and common The pixel regions P1 and P2 are defined in a form surrounded by the wiring 139 or Vcom or the gate auxiliary wiring 138, respectively.

The array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention is connected to the gate wiring 113 formed in the horizontal direction of the display region DA, And a gate auxiliary wiring 138 formed in parallel with the gate wiring line 130. The gate signal voltage applied to the gate wiring line 113 can be applied through the gate auxiliary wiring 138 .

Thus, the gate auxiliary wiring 138 is formed to correspond to the data wiring 130, and one end of the gate auxiliary wiring 138 is electrically connected to the second non-display area < RTI ID = 0.0 > (NA2 in FIG. 3), and a gate pad portion (not shown) having a gate pad electrode (not shown) provided at one end of the gate auxiliary wiring 138 is formed in the second non-display region 3) via the gate drive IC (173 in FIG. 3) to a gate pad portion (not shown) provided in the second non-display region (NA2 in FIG. 3) 3), or the gate driver IC (173 in Fig. 3) can be mounted.

Therefore, the FPC (163 in FIG. 3) or the gate driver IC (173 in FIG. 3) of the gate is extended to the fourth and third ratios of the left and right sides of the display area DA, The gate drive IC (71 in FIG. 2) is formed in the fourth and third non-display areas NA4 and NA3 located on the left and right sides of the display area DA because it is unnecessary to be mounted on the display areas NA4 and NA3. The narrow bezel can be realized because the width of the FPC (40 in FIG. 2) can be reduced compared with a general fringe field switching mode liquid crystal display array substrate (40 in FIG.

 Meanwhile, the array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention has a structure in which a gate wiring (not shown) The number of the data lines 113 is doubled and the number of the data lines 130 is reduced to 1/2.

Therefore, the array substrate 110 according to the embodiment of the present invention includes a driving IC (not shown) connected to the data line 130 by reducing the number of the data lines 130 compared to the conventional array substrate 10 The gate auxiliary wiring 138 or the common wiring 139 is formed in a region where the data wiring 130 is to be formed. With this structure, the conventional common fringe field switching mode liquid crystal display And the aperture ratio at the same level as that of the array substrate (40 in Fig. 2).

Generally, in the case of a liquid crystal display device, three pixel regions neighboring each other are expressed as one unit region, and one color is expressed. Three pixel regions located in each unit region display red, green, and blue colors, respectively. And a full color can be realized by a combination of three colors.

Therefore, in general, in the case of an array substrate for a liquid crystal display device, the number of data wirings is three times larger than the number of gate wirings. Further, due to the nature of the display device, Is usually 1.25 times larger than the pixel area (the width-to-width ratio is usually from 5: 4 to 16: 9 based on the cross-sectional aspect ratio of the display area, and is based on 5: 4).

Therefore, in the case of a general liquid crystal display device, the number of data lines is at least 3.75 times larger than the number of gate lines.

Meanwhile, in the array substrate 110 for a liquid crystal display for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, when a gate wiring and a data wiring of a general array substrate (10 in FIG. 1) The wiring is doubled and the data wiring is 1/2 the level.

In other words, assuming that the number of gate wirings of a general array substrate (10 in FIG. 1) is 1, the array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention includes gate wirings 113 The ratio of the data line 130 to the gate line 113 is 1.875 and the portion where the data line 130 is to be formed corresponding to 1.875 times of the gate line 113 remains as a margin.

Therefore, the number of the gate auxiliary wirings 138 corresponding to the number of the gate wirings 113 is provided in correspondence with the margin portion where the data wirings 130 are formed and the number of the gate auxiliary wirings 138 The common wiring 139 can be disposed in the remaining margin portion.

For example, in order to realize full HD, which is the highest resolution of a display device, a unit area of 1080 * 1920 (three neighboring pixel areas become one unit area) is required. In this case, In the case of the substrate, a total of 1080 gate wirings and 5760 (1920 * 3) data wirings are formed.

However, in the array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention, when the same resolution as that of an array substrate for a liquid crystal display device is realized, the gate wiring 113 is 2160 (1080 * 2 ) And the data wiring 130 is 2880 (1920 * 3 * / 2).

Therefore, the number of the data lines 130 is reduced by 2880 compared to the conventional array substrate 10 (FIG. 1), and the portion where the data lines 130 are to be formed becomes empty by the number of the data lines 130, The gate auxiliary wiring 138 can be formed for the 2160 redundant portions corresponding to the number of the gate wirings 113 among the redundant portions and the common wiring 139 can be formed for the remaining 720 redundant portions.

Accordingly, although the array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention has a gate wiring line twice as large as that of an array substrate (10 of FIG. 1) for a general liquid crystal display device, ) Is larger than the increased number of the data lines 113, a sufficient space can be secured to form the gate auxiliary lines 138, which are configured to correspond one-to-one with all the gate lines 113.

On the front surface of the substrate 110 above the thin film transistor Tr, the data wiring 130, the gate auxiliary wiring 138, the common wiring 139, the data pad electrode 137 and the gate pad electrode (not shown) A first protective layer 140 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is provided, and on the first protective layer 140, And a planarization layer 145 made of photo-acryl and having a flat surface.

The planarization layer 145 is provided with a common hole cch exposing the first passivation layer 140 in correspondence with a portion of the common line 139, A gate hole (gch) for exposing the first passivation layer 140 is provided corresponding to the gate line 180 and the gate line 113 adjacent thereto.

A first auxiliary contact hole ch1 for exposing the common line 139 is formed in the first passivation layer 140 in the common hole cch. In the gate hole gch, The first passivation layer 140 and the gate insulating layer are provided with a second auxiliary contact hole ch2 for exposing a part of the protrusion 180 and a part of the gate wiring 113.

A common electrode 150 made of a transparent conductive material is formed on the planarization layer 145 having the common hole cch and the gate hole gch corresponding to the entire display area DA.

At this time, the common electrode 150 is provided with a first opening op1 for exposing the planarization layer 145 by removing a portion corresponding to the thin film transistor Tr, and further includes a gate electrode The second opening op2 is formed and the gate auxiliary wiring 138 is formed inside the gate hole gch corresponding to the gate hole gch. And a third opening (op3) exposing the first passivation layer 140 are formed.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is formed on the entire surface of the substrate 110 over the common electrode 150 having the first, second and third openings op 1, op 2 and op 3. The second protective layer 155 is formed.

A drain hole dch exposing the drain electrode 136 of the thin film transistor Tr is formed in the second passivation layer 155 and the planarization layer 145 and the first passivation layer 140 located below the second passivation layer 155 Respectively.

A third auxiliary contact hole (ch3) exposing one end of the common electrode 150 and the common wiring 139 is formed in the second protective layer 155 in the common hole cch And a second protection layer 155 is formed in the gate hole gch so as to overlap the second auxiliary contact hole ch2 to expose the protrusion 180 and the gate wiring 113 adjacent thereto. 4 auxiliary contact holes ch4 are provided.

Next, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is formed on the second passivation layer 155, And a pixel electrode 170 which is in contact with the drain electrode 136 of the thin film transistor Tr through a hole dch is provided.

At this time, a plurality of fourth openings (op4) having a bar shape are formed on the pixel electrodes 170 at a predetermined interval.

Both ends of the gate hole gch are located above the second passivation layer 155 and are made of the same material as the pixel electrode 170. The protrusion of the gate sub- 180 and a first connection pattern 175 contacting the gate wiring 113 at the same time.

Therefore, the gate auxiliary wiring 138 and the gate wiring 113 are electrically connected by the first connection pattern 175.

In addition, one end of each of the common electrodes 150, which is located above the second passivation layer 155 and is exposed to the outside of the second passivation layer 155, And the second connection pattern 177 is formed in contact with the common wiring 139 exposed by the third auxiliary contact holes ch1 and ch3. The common electrode 150 and the common wiring 139 are electrically connected to each other.

The array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention has four non-display areas (NA1, NA2, NA3, (NA4 and NA3 in Fig. 3) positioned on the right and left sides of the array substrate (NA1, NA2, NA3, and NA4) can be realized. Further, in the display area DA, The gate auxiliary wiring 138 is formed in addition to the data auxiliary wiring 140 of FIG. 1, but the number of the data wiring 130 is reduced, Since the opening 138 is formed, a decrease in the aperture ratio can be suppressed.

A gate hole gch provided for electrical connection between the gate wiring 113 and the gate auxiliary wiring 138 is formed by providing the protrusion 180 disposed in the gate auxiliary wiring 138 in parallel with the gate wiring 113. [ It is possible to suppress the decrease of the aperture ratio by reducing the area of the aperture.

Hereinafter, a method of manufacturing an array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention having the above-described plane and cross-sectional configurations will be described.

Figs. 11A to 11H are cross-sectional views showing steps taken along the cutting line VI-VI of Fig. 5, and Figs. 12A to 12H are cross-sectional views of the portion cut along the cutting line VII- 13A to 13H are cross-sectional views of the manufacturing process of the portion cut along the cutting line VIII-VIII in FIG. 5, and FIGS. 14A to 14H are cross- FIGS. 15A to 15H are cross-sectional views illustrating a method of fabricating a fringe field switching mode liquid crystal display according to an embodiment of the present invention. A gate pad portion which is a gate pad portion). Here, for convenience of description, a portion where the thin film transistor Tr is formed in each of the pixel regions P1 and P2 is defined as a switching region TrA.

First, as shown in FIGS. 11A, 12A, 13A, 14A, and 15A, a low resistance metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and a molybdenum alloy (MoTi) on the entire surface to form a first metal layer (not shown).

Thereafter, the first metal layer (not shown) is exposed to a series of photoresist coating, exposure using a photomask, development of exposed photoresist, etching of the first metal layer (not shown), and strips of photoresist (A distance of about 2 탆 to about 5 탆 at a spacing enough to prevent shorting at the time of patterning) so as to be parallel to the work A pair of gate wirings 113 composed of the first and second gate wirings 113a and 113b are spaced apart from each other by a second interval (the length of the major axis of the pixel regions P1 and P2) larger than the first spacing distance So that they are arranged in a side-by-side manner.

At the same time, a gate electrode 108 connected to the gate line 113 is formed in each switching region TrA. At this time, the gate electrode included in each switching region TrA is branched in the gate wiring 113, or the gate wiring 113 itself has a shape having a larger width than other regions .

At this time, as a characteristic feature of the present invention, a gate pad electrode (not shown) is not formed at one end of each of the gate wirings 113. The array substrate 110 for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention forms gate pad electrodes (not shown) at one end of a gate auxiliary wiring 138 formed in parallel with the data wiring 130 .

The array substrate 110 for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention has a ratio of the ratio of the ratio of the ratio No separate pad portions are formed in the display area (NA4, NA3 in Fig. 3). Therefore, widths of left and right non-display areas (NA4 and NA3 in Fig. 3) of the display area DA are reduced to realize a narrow bezel.

Next, the, the gate wiring 113 and the gate electrode 108 over the inorganic insulating material, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx) as shown in Fig. 11b, 12b, 13b, 14b and 15b And a gate insulating layer 120 is formed on the entire surface of the substrate 110.

A pure amorphous silicon layer 121 and an impurity amorphous silicon layer 122 are sequentially formed on the gate insulating layer 120 and a low resistance metal material such as aluminum (Al) A second metal layer 128 is formed by depositing at least one of aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), and molybdenum alloy (MoTi) on the entire surface.

Thereafter, a photoresist layer (not shown) is formed on the second metal layer 128, and a first photoresist pattern 191a having a first thickness is formed by performing halftone exposure or diffraction exposure, A second photoresist pattern 191b having a second thickness that is thinner is formed.

At this time, the first photoresist pattern 191a is electrically connected to the source and drain electrodes (133 and 136 in FIG. 11H), the data wiring (130 in FIG. 13H), the data pad electrode The second photoresist pattern 191b is formed in correspondence with the portion where the gate electrode (138 in FIG. 13H) and the gate pad electrode (not shown) connected thereto and the common wiring (139 in FIG. 14H) (133, 136 in Fig. 11H).

Next, as shown in Figs. 11C, 12C, 13C, 14C and 15C, the second metal layer (128 in Fig. 11B) exposed to the outside of the first and second photoresist patterns 191a and 191b and the The impurity and the pure amorphous silicon layer (118 and 117 in FIG. 11B) are removed by etching to form a gate insulating film 120 extending in a second direction intersecting with the gate wiring 113 made up of the pair, A plurality of data lines 130 are formed to define a first region P in which two pixel regions P1 and P2 are grouped and a data pad electrode 137 is formed at one end of the data line 130 ).

At the same time, a gate auxiliary wiring 138 and a common wiring 139 which are aligned with the data wiring and define the pixel regions P1 and P2 neighboring to the left and right through the first regions are formed, A gate pad electrode (not shown) is formed at one end of the auxiliary wiring 138.

At this time, the gate auxiliary wiring 138 is provided with a protrusion 180 adjacent to a portion where the gate wiring 113 connected thereto is formed and arranged in parallel with the gate wiring 113, and the common wiring 139, The portion overlapping with the pair of gate wirings 113 is formed so as to have a larger width than the other regions in consideration of the area of the portion to be contacted with the common electrode 150 to be formed later,

The protrusion 180 is formed in the gate auxiliary wiring 138 in order to reduce the area of the gate hole gch in the later formed planarization layer 145. In the common wiring 139, In order to secure a margin for forming a common hole (cch) in the planarization layer 145 in response thereto.

The planarization layer 145 is formed to have a relatively thicker thickness than the thickness of the gate insulating layer or the first and second protective layers 140 and 155 to be formed later, Therefore, the minimum required area for forming the contact hole therebetween, and the minimum area for forming the contact hole to be provided in the planarization layer 145 is larger than the width of a typical wiring, The wiring 139 is formed to have a larger width than other regions corresponding to the portion where the common hole cch is to be formed.

The data pad electrode 137 is formed in the first non-display area NA1 located above the display area DA and the gate pad electrode (not shown) is disposed under the display area DA The data pad electrode 137 is formed in the second non-display area NA2 located below the display area DA, that is, the data pad electrode 137 is formed in the second non-display area NA2, The gate pad electrode (not shown) may be formed in the first non-display area NA1 located above the display area DA.

In general, in the case of an array substrate for a fringe field switching mode liquid crystal display, a gate pad electrode is formed at one end of a gate wiring, and a data pad electrode is formed at one end of a data wiring formed in a layer different from the gate wiring, The array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention has a gate pad electrode (not shown) and a data pad electrode 137 formed by the manufacturing method as described above, Is characterized by having the same lamination form.

The data wiring 130 and the data pad electrode 137, the gate auxiliary wiring 138 and the gate pad electrode (not shown) and the common wiring 139 are formed on the gate insulating film 120, The source and drain patterns 132 connected to the data lines 130 in the switching region TrA and the impurity amorphous silicon patterns 125 sequentially stacked below the source and drain patterns 132 and the active layer 123a of pure amorphous silicon are formed.

The data line 130, the gate auxiliary line 138, the common line 139, and the gate and data pad electrode 137 are formed in the same plane as those of the data lines 130, And a dummy pattern 124 composed of a first pattern 124a of pure amorphous silicon and a second pattern 124b of the impurity amorphous silicon is formed on the gate insulating layer 120. [

Ashing is then performed to remove the second photoresist pattern (191b in Fig. 11C) having the second thickness, as shown in Figs. 11D, 12D, 13D, 14D and 15D.

11C) by removing the second photoresist pattern (191b in FIG. 11C) by etching and removing the central portion of the source drain pattern (132 in FIG. 11C) newly exposed by removing the second photoresist pattern Drain electrodes 133 and 136 are formed.

Subsequently, the impurity amorphous silicon pattern 125 (FIG. 11C) exposed between the source and drain electrodes 133 and 136 is removed by dry etching so that the source and drain electrodes 133 and 136 are separated from each other And an ohmic contact layer 123b is formed to expose the active layer 123a. At this time, the active layer 123a and the ohmic contact layer 123b form a semiconductor layer 123. [

The gate electrode 114, the gate insulating film 120, the semiconductor layer 123, and the source and drain electrodes 133 and 136, which are sequentially stacked in the respective switching regions TrA, Thereby forming a transistor Tr.

Although not shown in the figure, in the step of forming the gate wiring 113 or the step of forming the data wiring 130, the gate wiring 113 or the data A plurality of auxiliary wirings (not shown) can be formed on the same material and in the same layer as the wiring 130.

Next, as shown in FIGS. 11E, 12E, 13E, 14E, and 15E, a strip is advanced to the source and drain electrodes 133 and 136, the data line 130 and the data pad electrode 137 The remaining first photoresist pattern (191a in Figs. 11D, 12D, 13D, 14D, and 15D) is removed.

Thereafter, the source and drain electrodes 133 and 136, the data wiring 130 and the data pad electrode 137, the gate auxiliary wiring 138 and the gate pad electrode (not shown) A first passivation layer 140 is formed on the entire surface of the substrate 110 by depositing an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x).

Then, photo-acryl, which is an organic insulating material, is applied on the entire surface of the substrate 110 on the first passivation layer 140 and the masking process is performed to pattern the planarization layer 145 corresponding to the display area DA, .

At this time, in the planarization layer 145 formed in the display area DA, a part corresponding to the protruding part 180 of the gate auxiliary wiring 138 and a part of the gate wiring 113 to be connected to the gate auxiliary wiring 138 A gate electrode gch for exposing the first passivation layer 140 and a drain electrode 136 of the thin film transistor Tr and a portion of the common wiring 139, A drain hole dch and a common hole cch that expose the first passivation layer 140 are provided, respectively.

Since the planarization layer 145 is formed corresponding to the display area DA, the gate pad electrode (not shown) and the data pad electrode 137 provided in the non-display area naturally have the first passivation layer 140 ) Is exposed.

Next, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is formed on the planarization layer 145 as shown in FIGS. 11F, 12F, 13F, 14F, A common electrode 150 is formed on the entire surface of the display region DA 'over the planarization layer 145 by performing a masking process and patterning on the entire surface of the substrate 110.

The first opening op1 exposes the planarization layer 145 and the first passivation layer 140 corresponding to the thin film transistor Tr formed in each switching region TrA of the common electrode 150, And a second opening exposing the planarization layer 145 and the first passivation layer 140 in correspondence with the gate hole gch provided in the planarization layer 145. [ and a third opening op3 in which the side end is located inside the common hole cch is provided so as to have an area smaller than the common hole cch corresponding to the common hole cch. do.

Accordingly, the side end of the common electrode 150 forming the boundary of the third opening (op3) of the common electrode 150 within the common hole cch is overlapped with the common wiring 139 It is characterized by being located.

Next, as shown in FIGS. 11g, 12g, 13g, 14g, and 15g, on the common electrode 150 provided with the first, second and third openings op1, op2 and op3, by depositing an inorganic insulating material, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx) to form a second protective layer (155).

Thereafter, a masking process is performed on the second passivation layer 155 to pattern the first passivation layer 140 and the gate insulating layer, which are located under the second passivation layer 155, by etching the drain hole dch, The second passivation layer 155 and the first passivation layer 140 are removed to expose the drain electrode 136.

Further, the second and first passivation layers 155 and 140 and the gate insulating layer 120 are etched with respect to the gate hole gch so as to expose the gate wiring 113 located therein. the fourth auxiliary contact hole ch4 exposing the protrusion 180 of the gate auxiliary wiring 138 is formed by etching the second and first passivation layers 155 and 140.

The second protection layer 155 is removed from the common hole cch to expose the side of the common electrode 150 forming the boundary of the third opening op3, The second protection layer 155 and the first protection layer 140 are removed to form the first auxiliary contact hole ch1 in which the common wiring 139 is exposed.

The second and first protective layers 155 and 140 exposed to the outside of the planarization layer 145 in the first and second non-display areas NA1 and NA2 are removed, A data pad contact hole dpch and a gate pad contact hole (not shown) exposing gate pad electrodes (not shown) are formed.

Next, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the second passivation layer 155 as shown in FIGS. 11H, 12H, 13H, Is formed on the entire surface of the substrate 110 and the masking process is performed by patterning the masking process so that the drain electrode 136 is formed in the display region DA through the drain hole dch for each pixel region P1, The pixel electrode 170 is formed.

At this time, in each of the pixel electrodes 170, a plurality of bar-shaped fourth openings op4 are formed to be spaced apart from each other by a predetermined distance.

In the first and second non-display areas NA1 and NA2 provided with the data and gate pad electrodes 137 (not shown), the data pad contact holes dpch A data auxiliary pad electrode 181 which contacts the data pad electrode 137 through a gate pad contact hole (not shown) and a gate auxiliary pad electrode (not shown) which contacts the gate pad electrode ).

(Gch) corresponding to the gate holes (gch) are formed of the same material forming the pixel electrodes 170 in the gate holes gch and exposed through the second and fourth auxiliary contact holes ch2 and ch4 A first connection pattern 175 is formed so as to contact the protruding portion 180 of the gate auxiliary wiring 138 and the gate wiring 113 adjacent thereto at the same time and the first connection pattern 175 is formed so as to correspond to the common hole cch, a common connection line 139 and a second connection pattern 177 which are simultaneously in contact with the exposed ends of the common electrode 150 are formed in the first and third auxiliary contact holes ch1 and ch3, Thereby completing an array substrate 110 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention.

In the case of the array substrate 110 completed in this manufacturing method, only a total of 6 mask processes are performed, so that the conventional 7 mask process can be performed, and a single mask process can be omitted compared to the completed manufacturing process, .

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the present invention.

110: (array) substrate
113a and 113b: first and second gate wirings
120: Gate insulating film
124: dummy pattern
124a, 124b: first and second (dummy) patterns
139: Common wiring
140: first protective layer
145: planarization layer
150: common electrode
155: second protective layer
ch1, ch3: first and third auxiliary contact holes
cch: common hole
DA: Display area

Claims (18)

A plurality of gate wirings and data wirings formed so as to intersect with each other with a gate insulating film interposed between the display region on the substrate having the plurality of pixel regions and the first, second, third and fourth non-display regions defined above, ;
A plurality of gate auxiliary wirings formed in the same layer on which the data wirings are formed and connected to any one of the plurality of gate wirings in parallel with the data wirings;
A common wiring formed in parallel with the data wiring in the same layer on which the data wiring is formed;
A thin film transistor connected to each of the gate wirings and the data wirings and formed in each of the pixel regions;
A first protective layer formed on the entire surface of the substrate over the thin film transistor;
A planarization layer formed on the display region over the first protective layer;
A common electrode formed on the planarization layer in the display region;
A second protective layer formed on the entire surface of the substrate over the common electrode;
A plurality of pixel electrodes having a plurality of first openings formed in a bar shape and connected to one electrode of the thin film transistor,
Wherein the gate auxiliary wiring is provided with a protrusion which is adjacent to the gate wiring connected to the gate wiring and branches off in parallel with the gate wiring and includes a first connection pattern which simultaneously contacts the protrusion and the gate wiring, Wherein the wiring and the common electrode are electrically connected to the second connection pattern contacting at the same time.
The method according to claim 1,
Wherein the planarization layer is provided with a gate hole corresponding to the protrusion and the gate wiring adjacent thereto and the second and first protection layers are removed inside the gate hole to expose the protrusion, Layer and the gate insulating layer are removed to expose the gate wiring, and the first connection pattern is in contact with the protruding portion and the gate wiring exposed in the gate hole.
3. The method of claim 2,
Wherein the planarization layer is provided with a common hole corresponding to the common wiring, and one end of the common electrode is located above the first protection layer inside the common hole, and the second and first protection layers are removed, And the second connection pattern is formed so as to be in contact with the common wiring exposed inside the common hole and one end of the common electrode at the same time.
The method of claim 3,
Wherein the common electrode includes a second opening corresponding to the thin film transistor, a third opening corresponding to the gate hole and having a larger area than the gate hole, and a fourth opening corresponding to the common hole And one end of the common wiring located at the boundary of the fourth opening is located inside the gate hole.
The method according to claim 1,
A data pad electrode is provided at one end of the data line and a gate pad electrode having the same stacking configuration as the data pad electrode is provided at one end of the gate sub line, 1 or the second non-display area. The substrate for a fringe field switching mode liquid crystal display according to claim 1,
The method according to claim 1,
The gate lines are arranged in pairs adjacent to each other at a first interval and spaced apart from each other at a boundary of the first region on the substrate when two neighboring pixel regions are defined as a first region,
Wherein the data line crosses the gate line arranged in pairs and defines the plurality of first regions,
Wherein the gate auxiliary wiring and the common wiring are disposed at two pixel region boundaries provided in the respective first regions.
The method according to claim 6,
Wherein only one of the gate auxiliary wiring and the common wiring is formed at a boundary between two pixel regions in each of the first regions.
The method according to claim 1,
Wherein the gate auxiliary wiring is formed by an integral multiple of the gate wiring to correspond to all the gate wirings.
The method according to claim 1,
An FPC via a data driving IC connected to the data line is mounted in the first or second non-display area located above or below the display area,
Wherein the first or second non-display area is provided with a gate driving IC connected to the gate auxiliary wiring, or an FPC via a gate driving IC is mounted. .
A plurality of gate wirings and a gate electrode connected to each of the plurality of gate wirings are formed in the display region on the substrate having the first, second, third, and fourth non-display regions defined by the display region having a plurality of pixel regions, ; ≪ / RTI >
Forming a gate insulating film over the gate wiring and the gate electrode;
A plurality of data lines crossing the plurality of gate wirings over the gate insulating film; and a gate auxiliary wiring disposed in parallel with the data wirings and having protruding portions branched in parallel to any one of the plurality of gate wirings Forming a thin film transistor by forming source and drain electrodes spaced apart from each other on the semiconductor layer and the semiconductor layer corresponding to the gate electrode;
Forming a first protective layer on the entire surface of the substrate over the data line;
Forming a planarization layer formed on the entire surface of the display region over the first protective layer and having a drain hole and a gate hole corresponding to the drain electrode and the protruding portion and the gate wiring adjacent thereto, ;
Forming a common electrode on the planarization layer over the entire surface of the display region, the common electrode having a first opening corresponding to the thin film transistor and having a second opening corresponding to the gate hole;
Forming a second protective layer on the entire surface of the substrate over the common electrode, selectively exposing the drain electrode in the drain hole by patterning the gate insulating film of the second protective layer and the first protective layer, Exposing the protrusion and the gate wiring;
Forming a pixel electrode having a plurality of third openings in a bar shape in contact with the drain electrode through the drain hole in each pixel region over the second passivation layer, Forming a first connection pattern in contact with the projecting portion and the gate wiring;
And a plurality of fringe field switching mode liquid crystal display devices.
11. The method of claim 10,
Wherein forming the data wiring and the gate auxiliary wiring comprises:
And forming a common interconnection on the gate insulating film in parallel with the data interconnection.
12. The method of claim 11,
The gate lines are arranged in pairs adjacent to each other at a first interval and spaced apart from each other at a boundary of the first region on the substrate when two neighboring pixel regions are defined as a first region,
Wherein the data line crosses the gate line arranged in pairs and defines the plurality of first regions,
And the gate auxiliary wiring or the common wiring is arranged at the boundary of two pixel regions provided in each of the first regions.
13. The method of claim 12,
Wherein only one of the gate auxiliary wiring and the common wiring is formed at a boundary between two pixel regions in each of the first regions.
12. The method of claim 11,
Forming a planarization layer having the drain hole and the gate hole,
And forming a common hole for exposing the first protective layer in correspondence with a part of the common wiring.
15. The method of claim 14,
Wherein forming the common electrode having the first and second openings comprises:
And forming a third opening corresponding to the common hole, wherein the boundary of the third sphere is located inside the common hole.
16. The method of claim 15,
Exposing the drain electrode in the drain hole and exposing the protrusion and the gate wiring in the gate hole,
And exposing the common electrode and the side of the common electrode forming the boundary of the third opening in the common hole by patterning the second protective layer and the first protective layer. A method of manufacturing an array substrate.
17. The method of claim 16,
Wherein forming the first connection pattern with the pixel electrode comprises:
And forming a second connection pattern in contact with the side ends of the common electrode and the common wiring within the common hole.
The method according to claim 10 or 11,
Wherein the step of forming the data line and the gate auxiliary wiring includes forming a data pad electrode connected to one end of the data line in the first or second non-display area, And forming a gate pad electrode connected to one end of the wiring,
Exposing the drain electrode in the drain hole, and exposing the protrusion and the gate wiring in the gate hole, the data pad electrode and the gate pad electrode are exposed by patterning the second passivation layer and the first passivation layer ≪ / RTI >
Wherein the forming of the first connection pattern with the pixel electrode comprises forming a data assist pad electrode and a gate assist pad electrode respectively contacting the data pad electrode and the gate pad electrode, A method of manufacturing an array substrate.

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